Segger J-Link Series User Manual page 17

9.15.5 TMS470M ............................................................................................. 221
9.15.6 OMAP3530............................................................................................ 222
9.15.7 OMAP3550............................................................................................ 222
9.16 Toshiba ................................................................................................ 223
10 Target interfaces and adapters ..................................................................................225
10.1 20-pin JTAG/SWD connector ................................................................... 226
10.1.1 Pinout for JTAG ..................................................................................... 226
10.1.2 Pinout for SWD...................................................................................... 229
10.2 38-pin Mictor JTAG and Trace connector ................................................... 231
10.2.1 Connecting the target board.................................................................... 231
10.2.2 Pinout .................................................................................................. 232
10.2.3 Assignment of trace information pins between ETM architecture versions ...... 234
10.2.4 Trace signals......................................................................................... 234
10.3 19-pin JTAG/SWD and Trace connector..................................................... 236
10.3.1 Target power supply .............................................................................. 237
10.4 9-pin JTAG/SWD connector ..................................................................... 238
10.5 Adapters .............................................................................................. 239
11 Background information .............................................................................................241
11.1 JTAG.................................................................................................... 242
11.1.1 Test access port (TAP)............................................................................ 242
11.1.2 Data registers ....................................................................................... 242
11.1.3 Instruction register ................................................................................ 242
11.1.4 The TAP controller ................................................................................. 243
11.2 Embedded Trace Macrocell (ETM)............................................................. 245
11.2.1 Trigger condition ................................................................................... 245
11.2.2 Code tracing and data tracing.................................................................. 245
11.2.3 J-Trace integration example - IAR Embedded Workbench for ARM ................ 245
11.3 Embedded Trace Buffer (ETB) ................................................................. 249
11.4 Flash programming ................................................................................ 250
11.4.1 How does flash programming via J-Link / J-Trace work?.............................. 250
11.4.2 Data download to RAM ........................................................................... 250
11.4.3 Data download via DCC .......................................................................... 250
11.4.4 Available options for flash programming ................................................... 250
11.5 J-Link / J-Trace firmware ........................................................................ 252
11.5.1 Firmware update ................................................................................... 252
11.5.2 Invalidating the firmware........................................................................ 252
12 Designing the target board for trace ..........................................................................255
12.1 Overview of high-speed board design ....................................................... 256
12.1.1 Avoiding stubs ...................................................................................... 256
12.1.2 Minimizing Signal Skew (Balancing PCB Track Lengths)............................... 256
12.1.3 Minimizing Crosstalk .............................................................................. 256
12.1.4 Using impedance matching and termination .............................................. 256
12.2 Terminating the trace signal.................................................................... 257
12.2.1 Rules for series terminators .................................................................... 257
12.3 Signal requirements ............................................................................... 258
13 Support and FAQs .....................................................................................................259
13.1 Measuring download speed ..................................................................... 260
13.1.1 Test environment .................................................................................. 260
13.2 Troubleshooting .................................................................................... 261
13.2.1 General procedure ................................................................................. 261
13.2.2 Typical problem scenarios ....................................................................... 261
13.3 Contacting support ................................................................................ 263
13.4 Frequently Asked Questions .................................................................... 264
14 Glossary.....................................................................................................................265
J-Link / J-Trace (UM08001) © 2004-2012 SEGGER Microcontroller GmbH & Co. KG
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