Cypress EZ-USB FX3 Technical Reference Manual

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EZ-USB

FX3™ Technical Reference Manual

Document Number: 001-76074 Rev. *F

May 9, 2019

Cypress Semiconductor

198 Champion Court

San Jose, CA 95134-1709

www.cypress.com

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Page 1 ® EZ-USB FX3™ Technical Reference Manual Document Number: 001-76074 Rev. *F May 9, 2019 Cypress Semiconductor 198 Champion Court San Jose, CA 95134-1709 www.cypress.com...
Page 2 High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the High-Risk Device, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any use of a Cypress product as a Critical Component in a High-Risk Device.
Page 3: Table Of Contents
1.4.10.4 Write Protection (WP)..................32 1.4.10.5 SDIO Interrupt .....................32 1.4.10.6 SDIO Read-Wait Feature ................32 1.4.10.7 Boot Options....................32 1.4.11 Clocking ........................33 FX3 CPU Subsystem Features..........................34 Block Diagram ........................35 Functional Overview .......................35 2.3.1 ARM926EJ-S CPU......................35 EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 4 4.3.3 Reset...........................57 4.3.4 Hard Reset ........................57 4.3.5 Soft Reset ........................57 FX3 DMA Subsystem DMA Introduction ........................58 DMA Features.........................58 DMA Block Diagram .......................58 DMA Overview........................59 DMA Subsystem Components....................60 5.5.1 Clocking ........................60 EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 5 UIB Top-Level Register Interface ...................81 USB Function Controllers .......................83 6.6.1 USB 3.0 Function ......................83 6.6.1.1 Clocking.......................83 6.6.1.2 Interrupt Requests ..................83 6.6.1.3 USB 3.0 Functional Description..............84 6.6.2 Physical Layer......................85 6.6.3 Link Layer........................86 EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 6 General Programmable Interface II (GPIF II) Features..........................120 Block Diagram ........................121 Typical GPIF II interface .......................121 Functional Overview ......................122 7.4.1 Actions ........................122 7.4.1.1 Action - IN_DATA ..................124 7.4.1.2 Action - IN_ADDR..................125 EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 7 7.6.8 Macro ........................146 GPIF II Constraints .......................146 7.7.1 Mirror States......................146 7.7.2 Mirror State Rules .....................147 7.7.3 Mirror State Example ....................148 7.7.4 Guidelines for Transition Equation Entry..............149 7.7.5 Intermediate States ....................150 EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 8 8.3.3.1 Reset and Initialization ................177 8.3.3.2 Modes Governing Transfers ..............177 8.3.4 SSN Control Configurations ..................177 8.3.5 Data Transfers......................178 Programming Model ......................178 8.4.1 Register-Based Transfers ..................178 8.4.2 DMA-Based Transfers....................178 Examples ..........................179 EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 9 Configure GPIO[45] as Input Pin and GPIO[21] as Output Pin ....194 8.9.4.3 Configure GPIO[50] to Generate PWM Output .........196 Storage Ports Storage Interface Block Features ..................197 Block Diagram ........................197 Storage Interface (S-Port).....................199 SD/ MMC/ SDIO Interface ....................201 EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 10 10.3.1 VIC_IRQ_STATUS ....................230 10.3.2 VIC_FIQ_STATUS ....................231 10.3.3 VIC_RAW_STATUS .....................232 10.3.4 VIC_INT_SELECT ....................233 10.3.5 VIC_INT_ENABLE ....................234 10.3.6 VIC_INT_CLEAR ....................235 10.3.7 VIC_PRIORITY_MASK ..................236 10.3.8 VIC_VEC_ADDRESS ..................237 10.3.9 VIC_VECT_PRIORITY ..................238 10.3.10 VIC_ADDRESS ....................239 EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 11 PIB_DLL_CTRL ....................295 10.6.10 PIB_WR_THRESHOLD ..................297 10.6.11 PIB_RD_THRESHOLD ..................298 10.6.12 PIB_ID ........................299 10.6.13 PIB_POWER ......................300 10.7 GPIF Registers ........................301 10.7.1 GPIF_CONFIG .....................301 10.7.2 GPIF_BUS_CONFIG ...................303 10.7.3 GPIF_BUS_CONFIG2 ..................305 10.7.4 GPIF_AD_CONFIG ....................306 EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 12 10.7.44 GPIF_LEFT_WAVEFORM ...................353 10.7.45 GPIF_RIGHT_WAVEFORM ................356 10.8 P-Port Registers ........................359 10.8.1 PP_ID ........................359 10.8.2 PP_INIT ........................360 10.8.3 PP_CONFIG ......................361 10.8.4 PP_INTR_MASK ....................363 10.8.5 PP_DRQR5_MASK ....................364 10.8.6 PP_SOCK_MASK ....................365 10.8.7 PP_ERROR ......................366 EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 13 10.12.6 OTG_INTR_MASK ....................416 10.12.7 OTG_TIMER ......................417 10.13 USB End Point Manager Registers ..................418 10.13.1 EEPM_CS ......................418 10.13.2 IEPM_CS ......................420 10.13.3 IEPM_MULT ......................421 10.13.4 EEPM_ENDPOINT ....................422 10.13.5 IEPM_ENDPOINT ....................423 10.13.6 IEPM_FIFO ......................424 EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 14 10.15.3 LNK_INTR_MASK ....................475 10.15.4 LNK_ERROR_CONF ...................477 10.15.5 LNK_ERROR_STATUS ..................479 10.15.6 LNK_ERROR_COUNT ..................481 10.15.7 LNK_ERROR_COUNT_THRESHOLD ..............482 10.15.8 LNK_PHY_CONF ....................483 10.15.9 LNK_PHY_MPLL_STATUS .................484 10.15.10 LNK_PHY_TX_TRIM ...................485 10.15.11 LNK_PHY_ERROR_CONF ..................486 10.15.12 LNK_PHY_ERROR_STATUS ................487 EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 15 10.18.4 I2S_INTR_MASK ....................534 10.18.5 I2S_EGRESS_DATA_LEFT ................535 10.18.6 I2S_EGRESS_DATA_RIGHT ................536 10.18.7 I2S_COUNTER ....................537 10.18.8 I2S_SOCKET .......................538 10.18.9 I2S_ID ........................539 10.18.10 I2S_POWER ......................540 10.19 I2C Registers ........................541 10.19.1 I2C_CONFIG ......................541 10.19.2 I2C_STATUS .......................543 EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 16 10.21.11 SPI_POWER ......................588 10.22 General Purpose IO Block Registers..................589 10.22.1 GPIO_SIMPLE .....................589 10.22.2 GPIO_INVALUE0 ....................591 10.22.3 GPIO_INVALUE1 ....................592 10.22.4 GPIO_INTR0 ......................593 10.22.5 GPIO_INTR1 ......................594 10.22.6 GPIO_INTR ......................595 10.22.7 GPIO_ID .......................596 EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 17 10.26.17 SDMMC_MODE_CFG ..................644 10.26.18 SDMMC_DATA_CFG ..................646 10.26.19 SDMMC_CS ......................647 10.26.20 SDMMC_STATUS ....................649 10.26.21 SDMMC_INTR .....................651 10.26.22 SDMMC_INTR_MASK ..................653 10.26.23 SDMMC_NCR ......................655 10.26.24 SDMMC_NCC_NWR ...................656 10.26.25 SDMMC_NAC ......................657 10.26.26 SDMMC_HW_CTRL ....................658 EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 18 Contents 10.26.27 SDMMC_DLL_CTRL ....................659 Revision History EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 19: Introduction To Ez-Usb Fx3
To provide high-bandwidth access to USB 3.0 data, FX3 contains a hardware unit called General Programmable Interface, Generation 2 (GPIF II). GPIF II is an enhanced version of the GPIF in FX2LP™, Cypress's USB 2.0 product. GPIF II provides easy and glueless connectivity to popular interfaces such as asynchronous SRAM and asynchronous and synchronous address and data multiplexed interfaces.
Page 20: Link Layer
The link layer is responsible for maintaining a reliable and robust communication channel between the host and the device. The Link Training and Status State Machine (LTSSM) at the core of the USB 3.0 link layer establishes the link connectivity EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 21: Protocol Layer
The example on the right indicates the packet sequence necessary to perform two back-to-back SuperSpeed IN transactions, which require only five packets to be exchanged: 1. SuperSpeed uses an ACK header (1) to initiate an IN transaction. 2. The SuperSpeed device returns the data packet (2). EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 22 3. The second data packet (3) initiates the second transaction and delivers data to the device. 4. Device acknowledges receipt of data via an ACK packet (4), completing the sequence. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 23: Data Bursting
(that is, a second ACK packet with NumP=4). In this burst example, the host continues to request additional data by keeping the NumP value at 4. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 24: End-To-End Flow Control
"ERDY" (ready) packet saying that now it is ready to transmit the data. So the host does not need to continue polling. This can significantly reduce SuperSpeed traffic and improve link power management. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 25: Streams
3 ms, and exit requires more than 20 ms. SuperSpeed power management provides finer granularity when entering low-power states and reduces entry and exit times. The device can also initiate the low-power link states when it is idle. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 26: Function Power Management
19.2, 26, 38.4, and 52 MHz ❐ 19.2-MHz crystal input support ❐ Ultra low-power in core power-down mode ■ Less than 60 μA with VBATT on and 20 μA with VBATT off ❐ EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 27 121-ball BGA, 10 x 10 mm, 0.8 mm pitch *All serial interfaces might not be available under all configuration options. Refer to the pin description section in the datasheet for details. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 28: Fx3 Block Diagram
CLKIN CLKIN_32 SRAM XTALIN (512kB/256kB) ARM9 XTALOUT HS/FS/LS OTG_ID OTGHost SSRX + DQ[31:0]/[15:0] SSRX - CTL[15:0] SSTX + Peripheral SSTX - PMODE[2:0] GPIF DMA Interconnect HS/FS Peripheral INT# RESET# UART EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 29: Fx3S Block Diagram
FX3 interrupts are managed through the standard ARM PrimeCell Vectored Interrupt Controller (PL192) block. This interrupt controller provides vectored interrupt support with configurable priorities for all interrupt sources. Examples of the FX3 firmware are available with the Cypress EZ-USB FX3 Development Kit. For more information about the CPU subsystem, refer to the...
Page 30: Dma
■ bidirectional. Cypress's GPIF II Designer tool enables GPIF II designs to be developed quickly and includes examples of common interfaces. For more information about the GPIF II block, refer to the General Programmable Interface II (GPIF II) chapter on page 120.
Page 31: Uart Interface
MMC system specification, MMCA Technical Committee, version 4.41 ■ SD specification, version 3.0 ■ SDIO host controller compliant with SDIO Specification version 3.00 ■ Both storage ports support the following features: EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 32: Sd/Mmc Clock Stop
Boot from I2C ■ Boot from SPI ■ Boot from GPIF II Async ADMux mode ■ Boot from GPIF II Sync ADMux mode ■ Boot from GPIF II Async SRAM mode ■ EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 33: Clocking
19.2-MHz Input CLK 26-MHz Input CLK 38.4-MHz Input CLK 52-MHz input CLK Clock inputs to FX3 must meet the phase noise and jitter requirements specified in the EZ-USB FX3 datasheet. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 34: Fx3 Cpu Subsystem
2. FX3 CPU Subsystem The EZ-USB FX3 device has an embedded 32-bit ARM926EJ-S core that delivers a processing capability up to 220 MIPS. This ARM core is coupled with instruction and data caches, Tightly Coupled Memories (TCM), and a PL192 vectored interrupt controller (VIC).
Page 35: Block Diagram
(AHB) interfaces for internal instruction and data accesses. It also has separate instruction and data TCM interfaces. Note: The 32-bit ARM instruction set is commonly used in the FX3 SDK from Cypress, as this makes it more convenient to address all of the available device memory.
Page 36: Processor Modes
Run-time stack regions need to be set up for all these modes at system startup. The following code snippet shows how this can be done using ARM assembly language code. This code is provided by the Cypress FX3 firmware library, and rarely needs to be modified.
Page 37: Processor Registers
2.3.1.2 Processor Registers Table 2-2 shows the registers provided by the ARM9 processor core. The CPSR register is used to switch between various processor modes. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 38: Exception Vectors
The data cache on the ARM core can be enabled only if the MMU is enabled. However, most FX3 designs do not use any secondary storage and do not need a virtual memory system. FX3 provides a fixed set of page tables that maps each physical address to the equivalent virtual address. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 39: Cache Memories
/* Initialize the ITCM */ MOV r1, 0x10000011 /* DTCM address is 0x10000000 and size is 8 KB. */ p15, 0, r1, c9, c1, 0 /* Initialize the DTCM */ EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 40: Jtag Interface
The controller is connected to the CPU on the AHB bus and allows you to perform the interrupt configuration through a set of memory mapped registers. Table 2-4 shows the various interrupt sources on the FX3 device, along with their vector numbers. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 41 FIQ), and all the DMA interrupts should be allotted the next high priority level. To enable a specific interrupt source, the firmware has to do the following: Point the VIC_VEC_ADDRESS register to the ISR. ■ EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 42: Cpu Operating Frequency
CPU clock frequency is 192 MHz or 208 MHz, depending on the clock source. Note: While the multipliers used to derive the system clock are programmable, Cypress strongly recommends the use of the previously mentioned default frequencies. The device has not been tested for proper functioning at other frequencies.
Page 43: Timers
Hint: As a single interrupt vector is used for both timers, the ISR needs to check the INTR bits in the WATCHDOG_CS register to identify the timer that triggered the interrupt. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 44: Memory And System Interconnect
Guaranteed and bounded memory access latency for both CPU and DMA accesses ■ Block Diagram Figure 3-1 shows a block diagram of the memory and system interconnect on the FX3 device. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 45: Functional Overview
Single Cycle ARM TCM Access (32 bit x 200 MHz) ITCM DTCM (16 KB) (8 KB) Functional Overview 3.3.1 Memory Regions Figure 3-2 shows the memory map of the FX3 device. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 46 The first 12 KB of this region is reserved for storing DMA-related data structures (descriptors) that are used by the FX3 hardware. The remainder of the System RAM can be used as required by the application. Figure 3-2 shows the commonly used subdivisions for the RAM region. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 47: System Interconnect
FX3 supports low-power operating modes in which the device clocks can be turned off and most of the blocks can be powered off. Table 3-1 shows the state of various FX3 blocks in the different power modes. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 48: Cache Operations
Hint: It is recommended that all DMA buffers be located in a separate memory region within the system RAM. It is also recommended that each DMA buffer occupy an integral number of cache lines (32 bytes) to ensure that an adjacent DMA buffer is not corrupted by a data transfer. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 49: Memory Usage
Memory region reserved for DMA data buffers used by the application; as larger DMA buffers can improve data transfer throughput, it DMA buffer is recommended that as much memory as is possible be allocated to this section EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 50 The memory map for the firmware application is specified through a linker script file. The format of the linker script file used by the standard GNU C compiler for ARM processors is documented here. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 51: Global Controller (Gctl)
However, only one pin from a group can use the complex I/O functions. The rest of the pins in the group are used as block I/O or simple GPIO. Refer to Table 7 in the EZ-USB FX3 datasheet for the GPIO configuration options.
Page 52 * 24- or 32-bit GPIF II bus width is not supported by all FX3 chips. If the FX3 chip does not support more than a 16-bit bus width, then alternate functions are not applicable. Refer to the EZ-USB FX3 datasheet for more details.
Page 53: I/O Drive Strength
O_COMPLEX is used to set the complex GPIO override. Refer to GPIO on page 192 for more details on GPIO configuration. GCTL_GPIO_COMPLEX on page 243. The FX3 SDK API CyU3PDeviceGpioOverride is used to configure the CY_U3P_GCTL_GPIO_COMPLEX register. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 54: I/O Power Observability
Programmable dividers generate clocks in GCTL (except the blocks that contain their own PLL, for example, USB block). All generated clocks have a configurable divide capability and on/off programmability. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 55 CPU clock. Independent 4-bit dividers are provided for both the DMA and MMIO bus clocks. The frequency of the MMIO clock, however, must be an integer divide of the DMA clock frequency. It is not recommended to EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 56: Power Management
LFPS detection on USB 3.0 RX lines, USB connect event, and watchdog timer-timeout event. The always-on global configuration block runs off the standby clock and is turned off only in the lowest power state (core power down). EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 57: Power Modes
CPU resets the CPU program counter. The firmware does not need to be reloaded following a CPU reset. ■ Whole device reset is identical to hard reset. The firmware must be reloaded following a whole device reset. ■ EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 58: Fx3 Dma Subsystem
Buses (AHB, as defined by the ARM System Architecture) are used to interconnect the system elements. The EZ-USB FX3 device architecture includes a DMA fabric that is used to route data between various peripheral interfaces and/ or the system memory of the device.
Page 59: Dma Overview
The DMA adapter is essentially a local DMA controller that initiates DMA transactions to and from the system memory on behalf of the peripheral that it services. With hardware synchronization between DMA adapters, data transfers can occur seamlessly between peripherals. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 60: Dma Subsystem Components
A typical dma_bus_clk_i frequency is set to one-half the CPU clock during device initialization. For example, if the CPU clock is set to 192 MHz, the register setting GCTL_CPU_CLK_CFG.DMA_DIV=1 (divider = 2) will result in a 96 MHz of dma_bus_clk_i frequency. Table 5-1 summarizes the DMA clock information. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 61: Descriptors Buffers, And Sockets
Descriptors are data structures that keep track of the resources (memory buffers and sockets) used for a DMA transfer. This data structure is directly interpreted by the DMA hardware on FX3, and has to be located in a specific memory region of the EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 62 This data structure contains the fields that make up a DMA descriptor on the FX3 device. Each structure member is composed of multiple fields as shown below. Refer to the sock_regs.h header file for the definitions used. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 63: Dma Buffer
The ARM 926EJ-S core on the device also includes an 8 KB data cache. The data cache is four-way set associative with a cache-line size of 32 bytes and two dirty bits (one for each 16-byte region) per cache line. The EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 64: Memory Corruption Due To Cache Line Overlap
Whenever the CPU wants to commit a buffer containing data for an egress DMA operation, it can clean the region from the cache and then initiate the DMA operation. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 65: Sockets
SCK_SIZE on page 607 sets the amount of data to be transferred. A zero value in this register means the data amount is infinite. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 66 0x30 … 0x78 Reserved 0x7C Reserved ACTIVE_DSCR EVENT For detailed field description, see the following: SCK_DSCR on page 605 ■ SCK_SIZE on page 607 ■ SCK_COUNT on page 608 ■ EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 67 UNIT field in the status value. */ uvint32_t xferCount; /**< The completed transfer count for this socket. */ uvint32_t status; /**< Socket configuration and status register. */ EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 68: Software Manipulation Of Sockets
EVENT(s) will occur. This is normally the case when the socket is waiting for firmware to generate an event, that is, the socket is not coupled to another socket in another adapter. In this case it is not necessary to first suspend the socket. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 69: Inspecting A Socket
This section explains in a high level how DMA descriptors, buffers, and sockets are tied together to achieve the required DMA operation, with the help of an example peripheral-to-peripheral DMA operation. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 70 DMA data read transfers may resume. Go to step (1) 5. If no descriptor is available the socket is suspended. When the software extends the descriptor list and explicitly 'resumes', the IP block operation continues. Go to step (3). EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 71: Interrupt Requests
When a DMA interrupt occurs, the CPU is notified by VIC with the DMA interrupt line specific to the peripheral, as shown in Table 5-4. Then the CPU can check the peripheral's global SCK_INTR register to find the socket number that needs attention. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 72: Programming Sequence
In this case, the consumer socket goes to the stall state and waits for the buffer to become available upon a produce event. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 73: Peripheral To Peripheral Transfer
It also considers the software drivers for the ingress and egress peripherals (that are mutually independent) and the higher level s/w that manages the endpoint. Figure 5-11. Peripheral - Peripheral DMA Transfer EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 74 = 16; if (direction) /* 1=TX: SYSMEM to device dscr->sync = ( (ch << CY_U3P_LPP_CONS_SCK_POS) | (id << CY_U3P_LPP_CONS_IP_POS) | (CPU_SCK_NUM << CY_U3P_LPP_PROD_SCK_POS) | (CPU_IP_NUM << CY_U3P_LP- P_PROD_IP_POS) | EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 75 (((epNum & 0x0F) == 0) && (IsNewCtrlRqtReceived ())) /* This request has been aborted due to a new control request. Just reset the USB socket and return an error. */ EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 76: Cpu Intervention In Between Ingress And Egress
This mode should only be used to handle special case stream requirements or to implement processing of the actual data by the CPU such as DSP applications. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 77: Concept Of Dma Channels
DMA Features on page 58, it is called a manual DMA channel. For more details on DMA channels and types of DMA channels supported, refer DMA Engine section in FX3 Programmer’s Manual. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 78: Universal Serial Bus (Usb)
USB 2.0 OTG dual-role device (DRD), with Host Negotiation Protocol (HNP) and Session Request Protocol (SRP) ■ support Block Diagram Figure 6-1 shows the top-level block diagram of the FX3 USB subsystem. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 79: Overview
The FX3 USB 2.0 embedded host is simpler than a full-featured PC-based controller. Embedded USB hosts are defined to support a limited peripheral list and to operate with limited memory (compared to a PC). In essence, the host controller EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 80: Usb Otg Controller
VBUS sensing for connection detection ■ Sampling of the USB_ID input for detection of A-device or B-device connection ■ Charging and discharging of DP line for starting a session as B-device ■ EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 81: Usb 3.0 Phy
/* 0xe0031810 */ uvint32_t otg_intr_mask; /* 0xe0031814 */ uvint32_t otg_timer; /* 0xe0031818 */ uvint32_t rsrvd3[249]; uvint32_t eepm_cs; /* 0xe0031c00 */ uvint32_t iepm_cs; /* 0xe0031c04 */ uvint32_t iepm_mult; /* 0xe0031c08 */ EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 82 /* 0xe0032800 */ uvint32_t shdl_ehci1; /* 0xe0032804 */ uvint32_t shdl_ehci2; /* 0xe0032808 */ } ehci_shdl[64]; uvint32_t rsrvd8[5376]; uvint32_t id; /* 0xe0037f00 */ uvint32_t power; /* 0xe0037f04 */ uvint32_t rsrvd9[62]; struct EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 83: Usb Function Controllers
GCTL_UIB_CORE_CLK.CLK_EN. 6.6.1.2 Interrupt Requests The UIB block has three global interrupt sources to the VIC, listed in Table 6-2, which are shared among USB 3.0, USB 2.0, and OTG controllers. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 84: Usb 3.0 Functional Description
6-2, the rows (device or host, protocol, link, physical) represent the communication layers of the SuperSpeed interconnect, namely: Physical (PHY) layer ■ Link layer ■ Protocol layer ■ The FX3 USB 3.0 function controller design follows the same basic SuperSpeed architecture. ■ EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 85: Physical Layer
10-bit symbols, and decoded and descrambled, producing 8-bit data that is then sent to the link layer for further processing. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 86: Link Layer
/* 0xe003302c */ uvint32_t reserved1[3]; uvint32_t lnk_phy_tx_trim; /* 0xe003303c */ uvint32_t lnk_phy_error_conf; /* 0xe0033040 */ uvint32_t lnk_phy_error_status; /* 0xe0033044 */ uvint32_t reserved2[2]; uvint32_t lnk_device_power_control; /* 0xe0033050 */ uvint32_t lnk_ltssm_state; /* 0xe0033054 */ EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 87: Protocol Layer
The protocol provides for the device to direct which data stream is active on the pipe. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 88 /* 0xe0033640 */ uvint32_t prot_epo_unmapped_stream[16]; /* 0xe0033680 */ uvint32_t prot_epo_mapped_stream[16]; /* 0xe00336c0 */ uvint32_t prot_stream_error_disable; /* 0xe0033700 */ uvint32_t prot_stream_error_status; /* 0xe0033704 */ } USB3PROT_REGS_T, *PUSB3PROT_REGS_T; #define USB3PROT ((PUSB3PROT_REGS_T) USB3PROT_BASE_ADDR) EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 89: Usb 2.0 Function
The TP handles most of the protocol described in chapter 8 of the USB specification. It receives the USB basic protocol commands from the host and generates the appropriate sequence of responses by synchronizing the frame timer, receiving/ EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 90: Usb 2.0 Function Registers
SETUP packets (to endpoint 0) are received by the SIE and reported to the TP. The SETUP data is stored in registers DEV_SETUPDAT0 and DEV_SETUPDAT0 1. The SUDAV bit in the DEV_CTL_INTR register is set, as is the SUTOK bit if the EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 91: In Packet
Note that USB 3.0 PHY on the FX3 needs to be turned off when VBus is removed or a host disconnect is discovered by other means. If the 3.0 PHY is left turned on, the 3.0 link startup is liable to fail when connected again to the host. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 92: Usb Function Programming Model
UIB->intr_mask &= ~(CY_U3P_UIB_DEV_CTL_INT | CY_U3P_UIB_DEV_EP_INT | CY_U3P_UIB_LNK_INT CY_U3P_UIB_PROT_INT | CY_U3P_UIB_PROT_EP_INT | CY_U3P_UIB_EPM_URUN); /* Enable the Vbus detection interrupt at this stage. */ GCTL->iopwr_intr = 0xFFFFFFFF; GCTL->iopwr_intr_mask = CY_U3P_VBUS; CyU3PVicEnableInt (CY_U3P_VIC_GCTL_PWR_VECTOR); EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 93: Usb 3.0 Enable
USB3LNK->lnk_conf = (USB3LNK->lnk_conf & ~CY_U3P_UIB_EPM_FIRST_DELAY_MASK) | (12 << CY_U3P_UIB_EPM_FIRST_DELAY_POS) | CY_U3P_UIB_LDN_DETECTION; USB3LNK->lnk_phy_mpll_status = 0x00310018 | CY_U3P_UIB_SSC_EN; CyFx3UsbWritePhyReg (0x0030, 0x00C0); CyU3PBusyWait (20); UIB->intr_mask |= (CY_U3P_UIB_DEV_CTL_INT | CY_U3P_UIB_DEV_EP_INT | CY_U3P_UIB_LNK_INT | CY_U3P_UIB_PROT_INT | CY_U3P_UIB_PROT_EP_INT | CY_U3P_UIB_EPM_URUN); EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 94: Usb 3.0 Fallback To Usb 2.0
CyU3PDmaChannelReset (&glUibChHandle); CyU3PDmaChannelReset (&glUibChHandleOut); /* Clear and disable USB 3.0 interrupts. */ USB3LNK->lnk_intr_mask = 0x00000000; USB3LNK->lnk_intr = 0xFFFFFFFF; USB3PROT->prot_intr_mask = 0x00000000; USB3PROT->prot_intr = 0xFFFFFFFF; UIB->intr_mask |= (CY_U3P_UIB_DEV_CTL_INT | CY_U3P_UIB_DEV_EP_INT | EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 95: Usb Reset
/* Control EP transfer size is 512 bytes. */ USB3PROT->prot_epo_cs1[0] |= CY_U3P_UIB_SSEPO_VALID; UIB->iepm_endpoint[0] = 0x200; /* Control EP transfer size is 512 bytes. */ CyU3PUsbResetEp (0x00); CyU3PUsbFlushEp (0x00); CyU3PUsbResetEp (0x80); CyU3PUsbFlushEp (0x80); EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 96: Usb Connect
= USB3LNK->lnk_ltssm_state & CY_U3P_UIB_LTSSM_STATE_MASK; while ((UIB->otg_ctrl & CY_U3P_UIB_SSDEV_ENABLE) && (state == CY_U3P_UIB_LNK_STATE_POLLING_LFPS)) CyU3PThreadRelinquish (); state = USB3LNK->lnk_ltssm_state & CY_U3P_UIB_LTSSM_STATE_MASK; if (state == CY_U3P_UIB_LNK_STATE_COMP) if (!glUibDeviceInfo.ssCmdSeen) CyU3PUsbAddToEventLog (CYU3P_USB_LOG_USBSS_DISCONNECT); CyU3PUsbSSDisConnecthandler (); return; EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 97 /* Control EP transfer size is 512 bytes. */ /* Propagate the event to the application. */ if (glUsbEvtCb != NULL) glUsbEvtCb (CY_U3P_USB_EVENT_CONNECT, 0x01); /* Configure the EPs for super-speed operation. */ EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 98: Usb Disconnect
= CY_U3P_USB_CONFIGURED; glUibDeviceInfo.usbSpeed = CY_U3P_NOT_CONNECTED; glUibDeviceInfo.isConnected = CyFalse; if (glUsbEvtCb != NULL) glUsbEvtCb (CY_U3P_USB_EVENT_USB3_LNKFAIL, 0); else CyU3PUsbPhyEnable (CyFalse); else /* If no VBUS, disconnect and turn off PHYs. */ EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 99: Control Request
CyU3PEventSet (&glUibEvent, CY_U3P_UIB_EVT_TRY_UX_EXIT, CYU3P_EVENT_OR); status = 0; else /* If USB-SS is enabled, set a flag indicating that the 3.0 PHY should * be turned on at the next bus reset. */ EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 100 UIB->dev_epo_xfer_cnt[0] = wLength; /* Default setting: Don't send status event notifications. */ glUibDeviceInfo.sendStatusEvent = CyFalse; /* Clear the inReset flag. */ UIB->dev_ctl_intr_mask &= ~CY_U3P_UIB_URESET; glUibDeviceInfo.inReset = 0; glUibDeviceInfo.newCtrlRqt = CyFalse; EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 101 CY_U3P_USB_SC_GET_STATUS: /* Let the setup callback handle GET_STATUS requests addressed to the inter- face. */ if (bTarget == CY_U3P_USB_TARGET_INTF) if (glUsbSetupCb) isHandled = glUsbSetupCb (setupdat0, setupdat1); if (isHandled) break; EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 102 /* Handle all Device specific SET Feature commands automatically. */ if (bTarget == CY_U3P_USB_TARGET_DEVICE) /* All device level SET_FEATURE requests except for OTG requests are han- dled in firmware. */ EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 103 ((!isHandled) && (bTarget == CY_U3P_USB_TARGET_ENDPT) && (wValue == CY_U3P_USBX_FS_EP_HALT)) if ((CyU3PUsbStall (wIndex, CyTrue, CyFalse)) == CY_U3P_SUCCESS) CyU3PUsbAckSetup (); isHandled = CyTrue; break; case CY_U3P_USB_SC_GET_DESCRIPTOR: isHandled = CyU3PUibSendDescr (setupdat0, setupdat1); break; case CY_U3P_USB_SC_GET_CONFIGURATION: EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 104 = CY_U3P_ERROR_BAD_ARGUMENT; break; break; case CY_U3P_USB_SC_GET_INTERFACE: if (glUsbSetupCb) isHandled = glUsbSetupCb (setupdat0, setupdat1); if (isHandled) break; isHandled = CyTrue; status = CyU3PUsbSendEP0Data (1, (uint8_t *)&glUibDeviceInfo.usbAltSet- ting); break; case CY_U3P_USB_SC_SET_INTERFACE: EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 105 ((glUsbEvtCb != NULL) && (status == CY_U3P_SUCCESS)) glUsbEvtCb (CY_U3P_USB_EVENT_SET_SEL, 0x00); else isHandled = CyFalse; break; case CY_U3P_USB_SC_SET_ISOC_DELAY: if ((CyU3PUsbGetSpeed () == CY_U3P_SUPER_SPEED) && (wIndex == 0) && (wLength == 0)) isHandled = CyTrue; CyU3PUsbAckSetup (); EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 106: Usb Embedded Host
USB 2.0 host endpoint interrupts are located in UIB_HOST_EP_INTR. UIB_INTR.HOST_EP_INT is the logical OR of the interrupt sources in UIB_HOST_EP_INTR. USB charger detect interrupts are located in UIB_CHGDET_INTR. UIB_INTR.CHGDET_INT is the logical OR of the interrupt sources in UIB_CHGDET_INTR. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 107: Functional Description
The periodic list pointer points to the first entry in the periodic list. It always starts from the lowest address of each scheduler memory. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 108 /* 0xe0032038 */ uvint32_t ohci_fm_interval; /* 0xe003203c */ uvint32_t ohci_fm_remaining; /* 0xe0032040 */ uvint32_t ohci_fm_number; /* 0xe0032044 */ uvint32_t ohci_periodic_start; /* 0xe0032048 */ uvint32_t ohci_ls_threshold; /* 0xe003204c */ EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 109: Embedded Host Programming Model
TOWNER bit to 1. At this point, the connect signal to the EHCI interface is cleared, and the EHCI interface sees a discon- nect and generates another interrupt request. 6.9.11.2 Host Disconnect These steps are followed when the device is disconnected from the host: EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 110: Managing Transfers
Setup transaction: N number of OUT data transactions followed by 1 IN token (ZLP) Setup transaction: N number of IN data transactions followed by 1 OUT token (ZLP) Setup transaction: 1 IN token (ZLP) EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 111 6.9.11.3.1.6 Status Phase (OUT) Once an EP0 OUT ZLP has been successfully received by the device, the scheduler deactivates the EP0 entry if the trns_mode of the scheduler entry is "0". EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 112: Usb Otg Controller
The FX3 OTG controller needs to be initialized before it can handle OTG events. The following code example implements the OTG controller start and stop sequence. CyU3PReturnStatus_t CyU3POtgStart ( CyU3POtgConfig_t *cfg) EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 113 /* Enable and set the EPM clock to bus clock (100MHz). */ GCTL->uib_core_clk = (CY_U3P_GCTL_UIBCLK_CLK_EN | CY_U3P_GCTL_UIB_CORE_CLK_DEFAULT); GCTLAON->control |= CY_U3P_GCTL_USB_POWER_EN; CyU3PBusyWait (100); CyU3PUsbPowerOn (); /* Enable OTG and charger detection interrupts. */ UIB->otg_intr = ~CY_U3P_UIB_OTG_INTR_DEFAULT; UIB->otg_intr_mask = CY_U3P_UIB_OTG_TIMER_TIMEOUT; EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 114 /* Enable and set the EPM clock to bus clock (100MHz). */ GCTL->uib_core_clk = (CY_U3P_GCTL_UIBCLK_CLK_EN | CY_U3P_GCTL_UIB_CORE_CLK_DEFAULT); GCTLAON->control |= CY_U3P_GCTL_USB_POWER_EN; CyU3PBusyWait (100); CyU3PUsbPowerOn (); UIB->otg_ctrl = CY_U3P_UIB_OTG_CTRL_DEFAULT; GCTL->iomatrix &= ~CY_U3P_CARKIT; UIB->chgdet_ctrl = CY_U3P_UIB_CARKIT; EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 115 /* Disable the UIB block. */ UIB->power &= ~CY_U3P_UIB_RESETN; CyU3PBusyWait (10); /* Disable the UIB clock. */ GCTL->uib_core_clk &= ~CY_U3P_GCTL_UIBCLK_CLK_EN; GCTLAON->control &= ~CY_U3P_GCTL_USB_POWER_EN; /* Update the state variable. */ glIsOtgEnable = CyFalse; return CY_U3P_SUCCESS; EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 116: Session Request Protocol
* Here we are first configuring the PHY as a device and doing a DP * pull-up to send a high. To send a low, the PHY is configured as host EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 117 UIB->ehci_configflag = CY_U3P_UIB_CF; CyU3PBusyWait (10); if (CyU3POtgIsDeviceMode ()) UIB->otg_ctrl &= CY_U3P_UIB_OTG_ENABLE; UIB->otg_ctrl |= CY_U3P_UIB_DEV_ENABLE; /* Enable and set the EPM clock to bus clock (100MHz). */ GCTL->uib_core_clk = (CY_U3P_GCTL_UIBCLK_CLK_EN | CY_U3P_GCTL_UIB_CORE_CLK_DEFAULT); EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 118: Host Negotiation Protocol
An OTG A-device acts as the host initially in a USB session. To allow a peripheral to assume the role of a host, the initial host must first configure the peripheral to enable HNP support through USB commands (SetFeature(b_hnp_enable)). To start the EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 119 3. Disable the USB device logic and enable the USB host logic. 4. Wait for a connect interrupt from the USB host logic. 5. Generate a USB bus reset and begin enumerating the peripheral. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 120: General Programmable Interface Ii (Gpif Ii)
7. General Programmable Interface II (GPIF II) EZ-USB FX3 integrates a high-performance interface, GPIF II, which enables functionality similar to but more advanced than the FX2LP GPIF and Slave FIFO interfaces. GPIF II is a programmable state machine that provides the flexibility to design a variety of interfaces to outside entities.
Page 121: Block Diagram
Interrupt or control signal The GPIF II control signals (CTL[12:0]) can be configured as outputs to control the external peripheral device, or as inputs to read the status from an external peripheral device. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 122: Functional Overview
Actions can be internal, such as reading or writing to a buffer. They can also be external, such as driving an output high or low. Table 7-2 lists the GPIF II actions. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 123 This action is generally used with COUNT_CTRL and the CTRL_CNT_HIT trigger. The count value can also be programmed by the firmware application using CyU3PGpifInitCtrlCounter(). The value programmed into the register at the time of execution of the state machine will be used. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 124: Action - In_Data
These options are made available to satisfy certain protocols when the data on the bus may lead a strobe signal that indicates data availability. Figure 7-4. IN_DATA Action Settings Dialog Box The following parameters are associated with this action: EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 125: Action - In_Addr
See the firmware API CyU3PGpifWriteDataWords(). Note that the option for selecting the source as the thread number is available only when the source is the DMA channel with the addressing mode selected as Thread selected by State machine (Number of address lines =0). EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 126: Action - Dr_Addr
Figure 7-7. DR_ADDR Action Settings Dialog Box The following parameters are associated with this action: Address Source-Register/AddressCounter/ThreadSocket. ■ Thread Number-Thread0 to 3 (available only when number of address bits is set to 0). ■ EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 127: Action - Commit
30 ns. The GPIO driven using the action is deasserted during the transition to the next state. Figure 7-9. DR_GPIO Action Settings Dialog Box The following parameters are associated with this action: EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 128: Action - Ld_Addr_Count
This action loads the counter with initial settings. The initial settings are loaded when the state machine starts. This value needs to be the same in all states within a given state machine diagram. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 129: Action - Ld_Ctrl_Count
Multiple values are not allowed. Figure 7-12. LD_CTRL_COUNT Action Settings Dialog Box The following parameters are associated with this action: EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 130: Action - Count_Addr
Comparison value-Value against which to compare the address. ■ Comparator mask event-When you deselect this parameter, it will cause an event to be generated to the firmware applica- ■ tion on a comparator match. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 131: Action - Cmp_Data
7.4.1.15 Action - CMP_CTRL This action compares the control bits with the specified comparison value. Figure 7-15. CMP_CTRL Action Settings Dialog Box The following parameters are associated with this action: EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 132: Action - Intr_Cpu
On assertion from the external processor on the DACK pin of FX3 ■ On deassertion from the external processor on the DACK pin of FX3 ■ From the state machine using the DR_DRQ action ■ EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 133: Triggers
They are the control input signals to GPIF II and are driven by an external device. The transition conditions are formed with these signals. The left transition condition is (!CE&&!RE) (a read operation), and the right EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 134: Gpif Ii Designer Tool
You can also make minor customizations to these designs to suit the target environment. A detailed description of the tool and its use is provided in the GPIF II Designer User Guide, which is available when you install the tool with the EZ-USB FX3 Software Development Kit.
Page 135: Counters
In this mode, all the sockets are connected to a single thread inside the GPIF II. PP_MODE=0 enables all four threads described in the previous section, as shown in Figure 7-18. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 136 Then when data access begins, the data is automatically routed through thread 0, to and from whichever socket number was specified earlier in the register, as shown in Figure 7-19. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 137: Addressing
Note that in this case, the corresponding GPIF_THREAD_CONFIG(x) register must be programmed using the API with the active socket to be accessed. Thread_in_state: Thread address from GPIF II state ■ EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 138: Async/Sync
7-20). As you select and deselect options, the center panel changes to reflect a "living schematic" of the interface. This saves you the trouble of figuring out the FX3 pin mapping because the FX3 signals are labeled in the FX3 block. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 139 It is not possible to implement both modes in a single configuration. If an address bus is part of the electrical interface, this will serve as an input for slave mode designs and as an output for master mode designs. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 140 DACK input signal. DACK: DMA Acknowledge. This is not a separate special function, but an input that is used to control the behavior of the DRQ signal. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 141: Gpif Ii State Machine Implementation
Add a State A right-click anywhere on the canvas displays the State Machine menu. Select Add State to add a state to the canvas as shown in the figure below. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 142: Add Actions To A State
Position the mouse cursor inside the source state, from which the transition will originate. The cursor changes its shape to “+.” Press the left mouse button, drag the mouse cursor to the destination state, and release it. The result of this step is shown in the figure below. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 143: Add A Transition Equation
IDs generated by the tool are generated by the tool as part of the header generation. The Repeat Count property indicates the number of clock cycles to continue inside the state before evaluating any outgoing transition equation. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 144: Analyzing The Signal Timing Of The Gpif Ii Interface
You can simulate the state machine to view the relative timing and value of the signals in the form of a timing diagram. Select the state machine path whose behavior is to be simulated. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 145 A saved scenario can be selected from this menu and modified or deleted. The Timing Simulation menu allows you to delete or modify the scenario. Figure 7-28. Modify Scenario Dialog Box EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 146: Macro
Cypress Support for assistance. 7.7.1 Mirror States The mirror state machine technique uses a GPIF II feature that facilitates state machine designs that do not conform to the previously described rules. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 147: Mirror State Rules
The GPIF hardware allows up to eight mirror state machines to be created, so that the active mirror is selected based on the current value of up to three input signals. The input signals that are used to select the active mirror state machine are called "global triggers." EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 148: Mirror State Example
The ZLP state, where a zero-length write operation is handled (no data, only end-of-packet signaling). This transition is triggered by END asserting while RD and WR are both deasserted. The COMMIT action is associated with this state. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 149: Guidelines For Transition Equation Entry
EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 150: Intermediate States
7-36. Here Sx and Sy are dummy states that have been inserted to meet the constraint that each state can have only two outgoing transitions. Figure 7-36. GPIF II Implementation for Multiple Transitions Avoiding Mirror States EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 151: Initialization And Configuration Of Gpif Ii Block
An existing project can be opened by choosing the File menu item Open Project. The start page also provides links to open the most recently used projects. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 152 No special function signals are needed for this example design. No input, output, and flags are used. ■ Figure 7-37 shows a screen shot of the Interface Definition window with the previous settings. Figure 7-37. Interface Definition Window for Example Project EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 153: Dma Channel Creation In Fx3 Firmware To Perform Gpif Ii To Usb Data Transfers
When the DMA_RDY_TH0 flag asserts, the GPIF II state machine moves to the READDATA state. It performs an IN_DATA action in this state. The IN_DATA action reads the data available on the data bus and places it in the DMA buffer of socket 0. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 154: Dma Channel Creation In Fx3 Firmware To Perform Usb To Gpif Ii Data Transfers
USB host. So you need to use the consumer socket of the PIB and the producer socket of the UIB. This project allocates four buffers for this data path, and each buffer is 16384 bytes. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 155: Gpif Ii State Machine To Drive Data From Socket As Data Source
When GPIF II tries to read data from the DMA buffer after it is emptied, then a PIB underrun error is flagged for the corresponding thread. The bit fields of the PIB error indicator register let you know if a PIB error is flagged. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 156: Alpha Values
The IN_DATA action reads the data available on the data bus and places it in the GPIF INGRESS register corresponding to socket 0. IN_DATA action settings are shown in Figure 7-43. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 157 The DR_DATA action drives the data available in the GPIF EGRESS register that corresponds to thread 1 onto the GPIF II data bus. The OUT_DATA action settings are shown in Figure 7-45. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 158: Implementing Synchronous Slave Fifo Interface
The packet end signal. It must be asserted to send a short packet to the USB host. Four DMA flags (FLAGA, FLAGB, FLAGC, and FLAGD) are provided to the external peripheral to manage the data flow. Figure 7-46 shows the FLAGA settings. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 159 The WaterMark value needs to be set using the CyU3PGpifSocketConfigure API. With this API, the active socket for each thread and its properties can be selected by the user at run time. Figure 7-48 shows the FLAGC settings. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 160 Figure 7-48. FLAGC Settings Figure 7-49 shows the FLAGD settings. Figure 7-49. FLAGD Settings A screen shot of the Interface Definition window with the previous settings is shown in Figure 7-50. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 161: Synchronous Slave Fifo Access Sequence And Interface Timing
FIFO buffers. The external master drives the 2-bit address on the ADDR lines and asserts the read or write strobes. FX3 asserts the FLAG signals to indicate the empty or full condition of the buffer. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 162: Synchronous Slave Fifo Read Sequence Description
FLAG Usage: FLAG signals are monitored by the external processor for flow control. FLAG signals are FX3 outputs that may be configured to show empty/full/partial status for a dedicated thread or the current thread being addressed. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 163 3 cycle latency from SLWR# to FLAG CFLG FLAGB dedicated thread FLAG for Am (1 = Not Full 0= Full) (Am) (Am) D (Am) Data IN High-Z (An) PKTEND SLOE (HIGH) EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 164: Synchronous Slave Fifo Write Sequence Description
FLAG Usage: FLAG signals are monitored by the external processor for flow control. FLAG signals are FX3 outputs that may be configured to show empty/full/partial status for a dedicated thread or the current thread being addressed. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 165: Slave Fifo Interface Logical Diagram
AN65974 - Designing with the EZ-USB FX3 Slave FIFO Interface. Figure 7-54. Slave FIFO Interface Flowchart 7.16.4 GPIF II State Machine of Slave FIFO Interface Figure 7-55 shows the GPIF II state machine of the Slave FIFO interface. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 166 General Programmable Interface II (GPIF II) Figure 7-55. GPIF II State Machine of the Slave FIFO Interface EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 167: Low Performance Peripherals (Lpp)
DMA sockets, but only two sockets can be active or enabled at a time for a block. All eight DMA sockets can be active together. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 168: I2C Interface
All the resets need to be deasserted for the block to be operational. I2C Interface 8.1.1 I2C Block Features The I2C block offers the following features: Operates in master mode ■ EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 169: I2C Interface Overview
FX3 can function in multimaster I2C bus environments, as it is capable of carrying out negotiations with other masters on the bus using SDA-based arbitration. Additionally, FX3 supports the repeated START feature to communicate with multiple slave EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 170: Fx3 I2C Operations Overview
DMA_MODE bit of the I2C_CONFIG register determines whether the I2C core is configured for DMA mode or register mode transfers. 8.2.3.1 Programming Model The FX3 I2C controller divides I2C transactions into two phases. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 171: Register-Based I2C Transfers
2. Program the I2C Byte count register to indicate the number of bytes to be transferred in the data phase. If you want the data phase to continue without any limit on the number of bytes, then program 0xFFFFFFFF. In this case, the data phase EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 172: Terminating Transactions: Software And Hardware Aborts
DMA-based transfers from FX3. APIs to perform read and write accesses to an I2C device are provided with the FX3 SDK. Refer to the Cyu3i2c.c file, which is located at C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\firmware\lpp_source (after FX3 SDK installation) for the source code of I2C-related APIs. Refer to FX3APIGuide.pdf located at C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\doc for more details on FX3 APIs.
Page 173: Configure I2C Block
((byteCount % glI2cPageSize) != 0) pageCount ++; resCount = byteCount % glI2cPageSize; while (pageCount != 0) if (isRead) /* Read */ /* Update the preamble information. */ preamble.length = 4; preamble.buffer[0] = devAddr; EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 174: Reads And Writes Using Dma Transfers
= (byteCount / glI2cPageSize); CyU3PReturnStatus_t status = CY_U3P_SUCCESS; if ((byteCount % glI2cPageSize) != 0) pageCount ++; /* Update the buffer address. */ buf_p.buffer = buffer; buf_p.status = 0; EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 175: Serial Peripheral Interface
Complies with the Motorola SPI specification in chapter 8 of the MC68HC11 reference manual ■ Supports register-based and DMA-based transfers ■ Supports programmable data unit length of 4 bit, 8 bit,16 bit, and 32 bit, MSB or LSB first ■ EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 176: Spi Interface Overview
Provides the Chip Select (CS#) signal ■ Provides SPI clock up to 33 MHz ■ FX3 can boot from SPI flash/ EEPROM (refer to AN76405 - EZ-USB FX3 Boot Options for more information) ■ 8.3.2 SPI Interface Overview The SPI bus is a synchronous serial data link interface, named by Motorola, which operates in full duplex mode. Devices communicate in master/slave mode where the master device initiates the data frame and provides the clock.
Page 177: Fx3 Spi Operations Overview
FX3 SS# output pin). The DESELCT bit in SPI_CONFIG has to be set while accessing nondefault slaves, logically disconnecting the default slave. The firmware can assert and deassert the GPIO line to select alternate slaves. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 178: Data Transfers
SPI_RX_BYTE_COUNT), then an end of transfer is indicated to the DMA adapter by setting the RX_DONE or TX_DONE flag to 1 respectively (of SPI_STATUS and SPI_INTR) in DMA-based transfers. As SPI protocol is very simple, no special error handling is required apart from handling FIFO overflow and underflow. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 179: Examples
FX3. APIs to perform read and write accesses to an SPI device are provided with the FX3 SDK. Refer to the Cyu3spi.c file located at C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\firmware\lpp_source (after FX3 SDK installation) for the source code of SPI-related APIs. Refer to FX3APIGuide.pdf located at C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\doc for more details on FX3 APIs.
Page 180: Reads And Writes Using Register Transfers
= 0x02; /* Write command */ status = CyFxSpiWaitForStatus (); CyU3PSpiSetSsnLine (CyFalse); status = CyU3PSpiTransmitWords (location, 4); if (status != CY_U3P_SUCCESS) CyU3PDebugPrint (2, "SPI WRITE command failed\r\n"); CyU3PSpiSetSsnLine (CyTrue); EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 181: Reads And Writes Using Dma Transfers
(isRead) /* Read */ location[0] = 0x03; /* Read command. */ buf_p.size = glSpiPageSize; buf_p.count = glSpiPageSize; status = CyFxSpiWaitForStatus (); CyU3PSpiSetSsnLine (CyFalse); status = CyU3PSpiTransmitWords (location, 4); if (status != CY_U3P_SUCCESS) EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 182 CyU3PSpiSetSsnLine (CyTrue); status = CyU3PDmaChannelWaitForCompletion(&glSpiTxHandle, 5000); if (status != CY_U3P_SUCCESS) CyU3PSpiSetSsnLine (CyTrue); CyU3PSpiSetSsnLine (CyTrue); CyU3PSpiDisableBlockXfer (CyTrue, CyFalse); /* Update the parameters */ byteAddress += glSpiPageSize; buf_p.buffer += glSpiPageSize; pageCount --; EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 183: Universal Asynchronous Receiver Transmitter
External interface devices must be used to convert the logic level signals of the UART to and from the external voltage signaling standards, such as RS-232, RS-422, and RS-485. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 184: Fx3 Uart Operations Overview
The UART_TX_BYTE_COUNT register specifies the number of bytes to be written out during DMA transfer. The UART_RX_BYTE_COUNT register is used to read the number of bytes received. Register mode transfers are always treated as infinite-length transfers. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 185: Error Conditions
This section shows the example codes to receive and transfer data from the FX3 UART block APIs to access the UART block are provided with the FX3 SDK. Refer to the Cyu3uart.c file located at C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\firmware\lpp_source (after FX3 SDK installation) for the source code of UART-related APIs. Refer to FX3APIGuide.pdf located at C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\doc for more details on FX3 APIs.
Page 186 RX_DONE event. The received data is printed back on the HyperTerminal and the DMA buffer is cleared for receiving the next set of data from the HyperTerminal. void uartIntrCb(CyU3PUartEvt_t evt, CyU3PUartError_t error) if (evt == CY_U3P_UART_EVENT_RX_DONE) EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 187: Integrated Interchip Sound Interface
I2S SCK Transmitter Receiver I2S WS I2S SD 1. WS: The word select line indicates the channel being transmitted: WS = 0; channel 1 (left) WS = 1; channel 2 (right) EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 188: Fx3 I2S Operations Overview
1. When Pause is asserted, transmit the current word pair, and then stop the data flow into the I2S block and transmit zeros. However, receive the data and buffer it for the previous request(s). Pause has priority over Mute if both are asserted. 2. Assert the PAUSED bit in the I2S_STATUS register. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 189: Buffer Underflow
SDK\1.3\firmware\lpp_source (after FX3 SDK installation) for the source code of the UART=related APIs. Refer to FX3APIGuide.pdf located at C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\doc for more details about the FX3 APIs. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 190: Initialize I2S Block
/* Identify the usb speed. Once that is identified, create a DMA channel and start the transfer on this. Based on the Bus Speed configure the endpoint packet size */ switch (usbSpeed) case CY_U3P_FULL_SPEED: size = 64; break; case CY_U3P_HIGH_SPEED: size = 512; EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 191 CyU3PDmaChannelCreate (&glI2sRightCh, CY_U3P_DMA_TYPE_AUTO, &dmaCfg); /* Flush the Endpoint memory */ CyU3PUsbFlushEp(CY_FX_EP_PRODUCER_1); CyU3PUsbFlushEp(CY_FX_EP_PRODUCER_2); /* Set DMA Channel transfer size to infinite. */ status = CyU3PDmaChannelSetXfer (&glI2sLeftCh, 0); status = CyU3PDmaChannelSetXfer (&glI2sRightCh, 0); EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 192: Gpio
GPIO. It uses the values from three registers. TIMER is the value of the PIN_TIMER register, THRESHOLD is the value of the PIN_THRESHOLD register, and MODE is from the PIN_STATUS register. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 193: Examples
This section shows an example code to configure and use FX3 GPIOs.. APIs to access the GPIO block are provided with the FX3 SDK. Refer to the Cyu3gpio.c file located at C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\firmware\lpp_source (after FX3 SDK installation) for the source code of GPIO-related APIs. Refer to FX3APIGuide.pdf located at C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\doc for more details on the FX3 APIs.
Page 194: Configure Gpio[45] As Input Pin And Gpio[21] As Output Pin
FAST clock. The frequency of this clock is determined by the simpleDiv value. The FAST clock is configured as half of the system clock, and the SLOW clock is disabled (set to zero). Interrupt callback can be registered using CyU3PGpioInit, but this example does not use it. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 195 /* Set the GPIO 21 to high */ CyU3PGpioSetValue (21, CyTrue); GPIO[21] can be driven low by changing the second parameter of the CyU3PGpioSetValue API. /* Set the GPIO 21 to low */ CyU3PGpioSetValue (21, CyFalse); EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 196: Configure Gpio[50] To Generate Pwm Output
The following code changes the PWM duty cycle to 75 percent. /* Change the PWM duty cycle to 75%. */ CyU3PGpioComplexUpdate (50, CY_FX_PWM_75P_THRESHOLD, CY_FX_PWM_PERIOD); /* CY_FX_PWM_75P_- THRESHOLD = (151200 - 1) */ EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 197: Storage Ports
SPI, UART, I2C, I2S, and GPIO. The SIB generates commands and accepts responses at the SD/MMC interface based on the configuration provided by the firmware. SIB contains two storage port controllers (S0 and S1) that can be independently configured to support different protocols. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 198 DMA adapter is the thread. A thread controller converts the simple request-data interface from the core to the required transactions on the DMA adapter. The DMA data enters the DMA adapter through two distinct pipes, named Thread EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 199: Storage Interface (S-Port)
UART + SPI + I2S interface. ■ Figure 9-2 shows the dual-SD/MMC/SDIO configuration, and Table 9-1 shows the S-port mapping in all configurations. Figure 9-2. Dual-SD/SDIO/MMC Configuration FX3S SDIO S0_DAT[7:0] S0_CMD S0_CLK S1_CLK S1_CMD S1_DAT[7:0] EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 200 8 bytes and greater than or equal to 16 bytes. The FAST_IO (CMD39) command should be used to transfer small amounts data from/to SDIO devices. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 201: Sd/ Mmc/ Sdio Interface
MMC card as an example. Similar operations apply to the SD protocol as well, with a change in data bus width. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 202 *Note: Bus width for the block read operation in the SD card would be 4 bits using the DAT0-3 lines. Figure 9-5. "No Response" and "No Data" Operations* * Source: eMMC Specification 4.3 For more details, refer to the SD/MMC specification. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 203: Sdio Interface Overview
1. Storage driver that identifies and initializes the storage peripherals connected to FX3S, as well as interrupt services asso- ciated with the storage interface 2. A set of APIs (storage API library) that allows users to query peripheral properties and perform data transfers to/from these peripherals EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 204: S-Port Initialization And Configuration
/* Don't care as no GPIO is selected. */ intfParams.cardDetType = CY_U3P_SIB_DETECT_DAT_3; /* Card detect based on SD_DAT[3]. */ intfParams.writeProtEnable = CyTrue; /* Write protect handling enabled.*/ intfParams.lowVoltage = CyTrue; /* Low voltage operation enabled. */ EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 205: Starting The Storage Driver
/**< MMC/eMMC device */ CY_U3P_SIB_DEV_SD, /**< SD Memory card */ CY_U3P_SIB_DEV_SDIO, /**< SDIO IO only Device.*/ CY_U3P_SIB_DEV_SDIO_COMBO /**< SDIO Combo Device. Data transfers to the combo card are not supported. */ } CyU3PSibDevType; EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 206: Setting The S-Port Clock
For bit definitions, refer to SDMMC_CMD_IDX register on page 632, SDMMC_CMD_RESP_FMT register on page 641, SDMMC_CMD_ARG0 register on page 633 SDMMC_CMD_ARG1 register on page 634. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 207 /* Run through each of the units present and check how many data partitions are present. We skip all boot partitions in this application. for (j = 0; j < glDevInfo[i].numUnits; j++) EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 208: Handling Sib Events
The SIB events are based on the bits of the SD/MMC/SDIO interrupt request register (SDMMC_INTR). These bits are set to 1 whenever a bit in SDMMC_STATUS changes from 0 to 1. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 209 = 0; glMscResidue = 0; glSensePtr[portId] = CY_FX_MSC_SENSE_OK; CyU3PEventSet (&glMscAppEvent, CY_FX_MSC_SIBCB_EVENT_FLAG, CYU3P_EVENT_OR); if (evt == CY_U3P_SIB_EVENT_INSERT) uint8_t i = 0; CyU3PDebugPrint (2, "Insert event on port %d\r\n", portId); EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 210: Reads And Writes To Sd/ Mmc Using Dma Transfers
/**< S-port socket number 1. */ CY_U3P_SIB_SOCKET_2, /**< S-port socket number 2. */ CY_U3P_SIB_SOCKET_3, /**< S-port socket number 3. */ CY_U3P_SIB_SOCKET_4, /**< S-port socket number 4. */ CY_U3P_SIB_SOCKET_5, /**< S-port socket number 5. */ EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 211 The socket number to be passed as a parameter to the function CyU3PSibReadWriteRequest is the offset with respect to CY_U3P_SIB_SOCKET_0. For example, if CY_U3P_SIB_SOCKET_1 is used to create the DMA channel, then the socket EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 212: Sending Vendor Commands To Sd/ Mmc
Void CyFxMscApplnSibCB ( uint8_t portId, CyU3PSibEventType evt, CyU3PReturnStatus_t status) if ((evt == CY_U3P_SIB_EVENT_DATA_ERROR) || (evt == CY_U3P_SIB_EVENT_ABORT)) /* Transfer has failed. Reset the DMA channel. */ if (glCmdDirection) CyU3PDmaChannelReset ((CyU3PDmaChannel *) &glChHandleMscOut); EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 213: Working With Sdio Cards
Function Number and the Register Address to the host. The data byte is returned in the response, R5. If this bit is set to 1, the command will write the bytes in the Write Data field to the I/O location EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 214 CMD52 command transmission is initiated in the same manner as explained in 9.5.1.5 Sending SD/MMC/SDIO Commands on page 206. The 1-byte response data of the CMD52 read register command is contained in the lower 8 bits of the SDMMC_RESP_REG register. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 215 Address field. Data is transferred on the DAT[0] or DAT[3:0] lines as defined for SD memory cards. Figure 9-9. IO_RW_EXTENDED Command Command Function Block Register Byte/ Block Index CRC7 Flag Number Mode Code Address Count 110101b * Source: SDIO Specification, version 2.0 EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 216 Inside this API, the block length and number of blocks, calculated from the parameters passed to it, are set in the appropriate registers: SDMMC_BLOCKLEN and SDMMC_BLOCK_COUNT. The logic for the same is as follows. if (blockmode == CY_U3P_SDIO_RW_BLOCK_MODE) noOfBlocks = transferCount; EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 217 = ((length+511)/512)*512; /* make sure that size is 512 aligned */ dmaBuffer.size size; dmaBuffer.buffer = buff; dmaBuffer.count = 0; dmaBuffer.status = 0; status = CyU3PDmaChannelSetupRecvBuffer (&glChHandleSdiotoCpu, &dmaBuffer); if (status != CY_U3P_SUCCESS) ERROR_PRINT (6, "CyU3PDmaChannelSetupSendBuffer error status = %d\r\n", status); EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 218: Setting Function Block Size
The interrupt period ends at the next clock from the end bit of a command that transfers data block(s) using DAT[x] lines. It resumes two clocks after the completion of the last data block transfer in a transaction. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 219: Enabling And Disabling Sdio Interrupts
= CyU3PSibRegisterCbk (CyFxSDIOUARTApplnSibCB); /* SIB Callback for handling SIB events */ void CyFxSDIOUARTApplnSibCB ( uint8_t portId, CyU3PSibEventType evt, CyU3PReturnStatus_t status) if (evt == CY_U3P_SIB_EVENT_SDIO_INTR) /* Handle SDIO interrupt event */ EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 220: Fx3S-Specific Features
VIO2 power domain (see Table 9-1); if S0 and S1 are at different voltage levels, the pin cannot be used as S1_INS. Figure 9-11 depicts this mechanism. Figure 9-11. Card Detection Using GPIO EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 221: Handling Card Detection In Software
4.1 GPIO Pins on page 51 for more details. /* Register a callback for SIB events. */ status = CyU3PSibRegisterCbk (CyFxSDIOUARTApplnSibCB); /* SIB Callback for handling SIB events */ void EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 222: Write Protection
To eliminate this limitation, the SDIO specification adds the read-wait control to enable the host to issue CMD52 during a multiple read cycle. Read-wait uses the DAT[2] line to allow the host to signal the card to temporarily halt the sending of read EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 223: Suspend-Resume Feature
SDMMC DLL control register. Increment these values from 0 until a point where the tuning data reception does not lead to a CRC16 error. When the phase values exceed the maximum possible value (15), all 16 phase values possible have returned CRC16 errors and hence a fatal error is reported. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 224: Normal And Alternate Emmc4.4 Boot
Once all boot data is read, the host pulls the CMD line HIGH, as illustrated in Figure 9-13. Figure 9-13. Normal Boot* * Source: eMMC Specification, version 4.3 EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 225 0XF0F0F0F0). As in the case of normal boot, the termination can occur during block boundary or data transfer. The condition for termination described previously for normal boot is the same for alternate boot. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 226 Storage Ports Figure 9-15. Alternate Boot * Source: eMMC Specification, version 4.3 The flow chart shown in Figure 9-16 depicts the alternate boot operation flow. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 227 Storage Ports Figure 9-16. Flow Chart for Alternate Boot Operation * EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 228: Registers
0xFC00 GCTL Global Controller register map 0x5FC00 0x0400 ARM CPU register map (BIST only) Detailed descriptions of all the registers in each IP block are provided in the following sections. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 229: Register Conventions
Gray, empty cells indicate reserved bits. Do not read from or write to these bits. ■ EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 230: Vectored Interrupt Controller (Vic) Registers
VIC_IRQ_STATUS IRQ Status after Masking IRQ_STATUS[23:16] VIC_IRQ_STATUS IRQ Status after Masking IRQ_STATUS[15:8] VIC_IRQ_STATUS IRQ Status after Masking IRQ_STATUS[7:0] Name Description 31:0 IRQ_STATUS[31:0] IRQ interrupt is raised by the following source: EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 231: Vic_Fiq_Status
FIQ Status after Masking FIQ_STATUS[23:16] VIC_FIQ_STATUS FIQ Status after Masking FIQ_STATUS[15:8] VIC_FIQ_STATUS FIQ Status after Masking FIQ_STATUS[7:0] Name Description 31:0 FIQ_STATUS[31:0] FIQ interrupt is raised at the line corresponding to the bit position. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 232: Vic_Raw_Status
IRQ Status before Masking RAW_STATUS[15:8] VIC_RAW_STATUS IRQ Status before Masking RAW_STATUS[7:0] Name Description 31:0 RAW_STATUS[31:0] FIQ/IRQ interrupt is raised at the line corresponding to the bit position regardless of its masked (disable) state. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 233: Vic_Int_Select
Designate the line corresponding to the bit position as FIQ. The software ensures that this register is a power of 2 (one FIQ only). It writes to this register only after disabling the inter- rupts it intends to change. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 234: Vic_Int_Enable
31:0 INT_ENABLE[31:0] Enable the interrupt at this bit position. All interrupts are disabled at reset. Software cannot write 0 here to disable interrupts. Use the VIC_INT_CLEAR register for this purpose. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 235: Vic_Int_Clear
This register disables the interrupt line and masks it if it was designated IRQ. Name Description 31:0 INT_CLEAR[31:0] Disable the interrupt at this bit position. Mask it if it is designated IRQ. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 236: Vic_Priority_Mask
Per-Priority Interrupt Mask Register PRIO_MASK[7:0] 0xFFFF This register allows you to mask interrupts on a per-priority basis. Name Description 15:0 PRIO_MASK[15:0] Unmasked Interrupt at the priority level = bit position is masked. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 237: Vic_Vec_Address
The firmware accesses this register only after disabling the corresponding interrupt. Holds the address to the ISR for interrupt number = the position of this register in the bank of 32 registers. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 238: Vic_Vect_Priority
16 priorities to the interrupt number. This equals the position of this register in the bank of 32 reg- isters. When any two interrupts with the same priority arrive at the VIC, the one connected to the lower numbered line wins. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 239: Vic_Address
Upon completion, the soft- ware writes any value to this register, which clears the active interrupt. software does not access this register at any other time. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 240: Global Controller Registers
Carkit UART configuration: Use LPP_UART (LPP_UART not available to S1) Use PIB_CTL11/PIB_CTL12 pins for carkit UART (enabling the USB2 PHY for Carkit UART operation must be done separately in UIB_PHY*). EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 241: Gctl_Gpio_Simple
GPIO Override Configuration Register OVERRIDE[47:40] GCTL_GPIO_SIMPLE GPIO Override Configuration Register OVERRIDE[39:32] GCTL_GPIO_SIMPLE GPIO Override Configuration Register OVERRIDE[31:24] GCTL_GPIO_SIMPLE GPIO Override Configuration Register OVERRIDE[23:16] GCTL_GPIO_SIMPLE GPIO Override Configuration Register OVERRIDE[15:8] continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 242 GCTL_GPIO_COMPLEX takes precedence over GCTL_GPIO_SIMPLE. Name Description 60:0 OVERRIDE[60:0 When bit <n> is set, the corresponding pin maps to simple GPIO <n>. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 243: Gctl_Gpio_Complex
GPIO Override Configuration Register OVERRIDE[47:40] GCTL_GPIO_COMPLEX GPIO Override Configuration Register OVERRIDE[39:32] GCTL_GPIO_COMPLEX GPIO Override Configuration Register OVERRIDE[31:24] GCTL_GPIO_SIMPLE GPIO Override Configuration Register OVERRIDE[23:16] GCTL_GPIO_COMPLEX GPIO Override Configuration Register OVERRIDE[15:8] continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 244 When bit <n> is set, the corresponding pin maps to complex GPIO_PIN <n> Mod 8. If multiple pins are mapped onto the same GPIO_PIN the behavior of the hardware is undefined. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 245: Gctl_Ds
C fast-mode 1.2 to 1.5 V, standard-mode 1.2 to 3.6 V (open-drain only) C fast-mode plus (open-drain only) S1LDS[1:0] Drive strength for GPIOs, VIO4 power domain continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 246 Drive strength for GPIOs, VIO3 power domain S0DS[1:0] Drive strength for GPIOs, VIO2 power domain PDS[1:0] Drive strength for P-Port, VIO1 power domain Quarter strength Three quarter strength Half strength Full strength EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 247: Gctl_Wpu_Cfg
I/O Pull-Up Configuration Register WPU[47:40] GCTL_WPU_CFG I/O Pull-Up Configuration Register WPU[39:32] GCTL_WPU_CFG I/O Pull-Up Configuration Register WPU[31:24] GCTL_WPU_CFG I/O Pull-Up Configuration Register WPU[23:16] GCTL_WPU_CFG I/O Pull-Up Configuration Register WPU[15:8] continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 248 Firmware should not enable WPU and WPD simultaneously on a given I/O. A weak pull-up or weak pull-down takes about 5 µs to be effective at the pads. Name Description 59:0 WPU[59:0] When set, a weak pull-up is connected for the pin associated with the corresponding GPIO #. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 249: Gctl_Wpd_Cfg
I/O Pull-Down Configuration Register WPD[47:40] GCTL_WPD_CFG I/O Pull-Down Configuration Register WPD[39:32] GCTL_WPD_CFG I/O Pull-Down Configuration Register WPD[31:24] GCTL_WPD_CFG I/O Pull-Down Configuration Register WPD[23:16] GCTL_WPD_CFG I/O Pull-Down Configuration Register WPD[15:8] continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 250 Firmware should not enable WPU and WPD simultaneously on a given I/O. A weak pull-up or weak pull-down takes about 5 µs to be effective at the pads. Name Description 59:0 WPD[59:0] When set, a weak pull-down is connected for the pin associated with the corresponding GPIO #. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 251: Gctl_Iopower
Enables regulator to output different voltages for the carkit mode. NOT ALLOWED for chip-level carkit UART mode because the regulator 2.5-V supply output is dis- abled, which is not supported by the USB2.0 PHY. Regulator operates normally. continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 252 Indicates all I/O power domains for this block are powered and active. Any time needed for internal voltages to stabilize cells to become active has passed before this bit asserts. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 253: Gctl_Iopower_Intr
Interrupt request. Must be cleared by firmware. USB25REG Interrupt request. Must be cleared by firmware. USB33REG Interrupt request. Must be cleared by firmware. VIO5 Interrupt request. Must be cleared by firmware. continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 254 Interrupt request. Must be cleared by firmware. VIO3 Interrupt request. Must be cleared by firmware. VIO2 Interrupt request. Must be cleared by firmware. VIO1 Interrupt request. Must be cleared by firmware. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 255: Gctl_Iopower_Intr_Mask
Set to 1 to report interrupt to CPU. Note CVDDQ is required for chip operation (clock and reset). This interrupt will never trigger when it is observable. continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 256 Set to 1 to report interrupt to CPU VIO3 Set to 1 to report interrupt to CPU VIO2 Set to 1 to report interrupt to CPU VIO1 Set to 1 to report interrupt to CPU EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 257: Gctl_Sw_Int
This register is a software interrupt register with 31b argument. Name Description SWINT Software interrupt request. Must be set by issuer and cleared by ISR. 30:0 ARGUMENT[30:0] 31-bit argument that can be set by issuer, read by ISR. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 258: Gctl_Pll_Cfg
PLL charge pump configuration 2.5 µA 5 µA 7.5 µA 10 µA The charge pump bit setting varies depending on both the refclk frequency and the configuration divider bits. continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 259 PLL input reference divider configuration. This field must be 0. OUTDIV PLL output divider configuration. This field must be 0. FBDIV PLL feedback divider configuration. This field must be 0x14. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 260: Gctl_Cpu_Clk_Cfg
The actual divider is DIV + 1. Zero (divide by 1) is illegal and results in undefined behavior. In other words, the range of divider values is 2 to 16. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 261: Gctl_Uib_Core_Clk
This field drives a simple clock mux; the actual presence and configuration of the clock inputs used is defined in the appropriate registers. Note In GTM test mode, make sure the USB2 PHY clock is running for at least 40 µs before selecting EPMCLK_SRC = 0. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 262: Gctl_Pib_Core_Clk
Clock divider value. This determines how much to divide the PLL system clock. The actual divider is DIV + 1. Zero (divide by 1) is illegal and results in undefined behavior. In other words, the range of divider values is 2 to 1024. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 263: Gctl_Gpio_Fast_Clk
Note Do not change HALFDIV after CLK_EN is set to 1 at least once, without first applying a hard- ware reset. It can be set together with CLK_EN in a single register write. continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 264 Note Any two writes to GCTL_GPIO_FAST_CLK and GPIO_SLOW_CLK must be spaced at least 35cy @ busclk apart. This holds for back-to-back writes to the same register as well as writes to both of these registers in either order. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 265: Gctl_Gpio_Slow_Clk
Note Any two writes to GCTL_GPIO_FAST_CLK and GPIO_SLOW_CLK must be spaced at least 35cy @ busclk apart. This holds for back-to-back writes to the same register as well as writes to both of these registers in either order. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 266: Gctl_I2C_Core_Clk
Clock divider value. This determines how much to divide the PLL system clock. The actual divider is DIV + 1. Zero (divide by 1) is illegal and results in undefined behavior. In other words, the range of divider values is 2 to 4096. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 267: Gctl_Uart_Core_Clk
Clock divider value. This determines how much to divide the PLL system clock. The actual divider is DIV + 1. Zero (divide by 1) is illegal and results in undefined behavior. In other words, the range of divider values is 2 to 65536. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 268: Gctl_Spi_Core_Clk
Clock divider value. This determines how much to divide the PLL system clock. The actual divider is DIV + 1. Zero (divide by 1) is illegal and results in undefined behavior. In other words, the range of divider values is 2 to 65536. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 269: Gctl_I2S_Core_Clk
Clock divider value. This determines how much to divide the PLL system clock. The actual divider is DIV + 1. Zero (divide by 1) is illegal and results in undefined behavior. In other words, the range of divider values is 2 to 32768. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 270: Global Controller Always On Registers
This wakeup source does not work from standby mode. This wakeup source works from sus- pend only when an external 32-kHz clock source is present. continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 271 This wakeup source works from suspend only when an external 32-kHz clock source is present. EN_PIB_CTRL0 Enables wakeup from the PIB CTL0 pin (CE# typically). Wakeup occurs on any change on this pin after wakeup. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 272: Gctl_Wakeup_Polarity
Wakeup when HIGH POL_UART_CTS Polarity of the UART_CTS signal: Wakeup when LOW Wakeup when HIGH POL_GPIO[44] Polarity of the GPIO[44] signal: Wakeup when LOW Wakeup when HIGH continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 273 Wakeup when HIGH (Not required for SDIO interrupt wakeup) POL_GPIO[34] Polarity of the GPIO[34] signal: Wakeup when LOW (Applicable for SDIO interrupt wakeup) Wakeup when HIGH (Not required for SDIO interrupt wakeup) EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 274: Gctl_Wakeup_Event
Indicates that this wakeup source was the reason for system wakeup from standby/suspend mode. GCTL_WAKEUP_EN for more information. EV_UIB_DM Indicates that this wakeup source was the reason for system wakeup from standby/suspend mode. GCTL_WAKEUP_EN for more information. continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 275 Indicates that this wakeup source was the reason for system wakeup from standby/suspend mode. GCTL_WAKEUP_EN for more information. EV_PIB_CTRL0 Indicates that this wakeup source was the reason for system wakeup from standby/suspend mode. GCTL_WAKEUP_EN for more information. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 276: Gctl_Freeze
Note that states 2 and 3 only override the output value driven to a fixed value, but do not change the drive mode of a pin from off to on. In other words, pins that are currently inputs remain inputs and are not forced to drive. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 277: Gctl_Watchdog_Cs
CPU while the system is powered-up. Refer to the GCTL_WAKEUP_EVENT register when the WDOG timer is used to wake up the system from a power-down state. continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 278 Free-running mode, counter wraps around after 32 bits. Interrupt mode, interrupt when COUNTER & ~((~0)<<BITS) = 0. Reset mode, full chip RESET when COUNTER & ~((~0)<<BITS) = 0. Disable - counter does not run EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 279: Gctl_Watchdog_Timer0
The CPU should not write the same value to this register successively; instead, it should alter the value. If the CPU wants to write value x, every interval, it must write x, x – 1, x, x – 1, … in successive intervals. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 280: Gctl_Watchdog_Timer1
The CPU should not write the same value to this register successively; instead, it should alter the value. If the CPU wants to write value x, every interval, it must write x, x – 1, x, x – 1, … in successive intervals. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 281: Pib Registers
Disabled Enabled PP_CFGMODE Variable indicating initialization mode to Application processor (PP_CONFIG.CFGMODE). Cleared by firmware after P-Port is properly initialized and ready to transact. continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 282 Provides a device ID. This field is visible in PP_INIT registers. This must be provided by Boot ROM. To prevent spoofing, this register is not writable when GCTL_CON- TROL.BOOTROM_EN = 0. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 283: Pib_Intr
Indicates that AP has written to PP_WR_THRESHOLD register. CONFIG_CHANGE AP has written a new value into PP_CONFIG. CLOCK_LOST PIB_CLK is no longer present. See PIB_CLOCK_DETECT for more details. continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 284 PP_EVENT.WR_MB_EMPTY to assert. RD_MB_EMPTY Indicates that the RD_MAILBOX is empty and a new message can be written. This bit sets when AP writes PP_EVENT.RD_MB_FULL = 0. It must be cleared by firmware. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 285: Pib_Intr_Mask
Mask for corresponding interrupt in PIB_INTR CONFIG_CHANGE Mask for corresponding interrupt in PIB_INTR CLOCK_LOST Mask for corresponding interrupt in PIB_INTR DLL_LOST_LOCK Mask for corresponding interrupt in PIB_INTR continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 286 PIB_INTR_MASK (continued) DLL_LOCKED Mask for corresponding interrupt in PIB_INTR GPIF_INTERRUPT Mask for corresponding interrupt in PIB_INTR WR_MB_FULL Mask for corresponding interrupt in PIB_INTR RD_MB_EMPTY Mask for corresponding interrupt in PIB_INTR EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 287: Pib_Clock_Detect
Indicates latest clock presence measurement 19:16 INTF_CYCLES[3:0] Minimum number of positive edges required on PIBCLK pin to declare clock presence during each measurement period. 15:0 BUS_CYCLES[15:0] Number of busclk cycles for each measurement period. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 288: Pib_Rd_Mailbox
Read (Egress) Mailbox Register PP_RD_MAILBOX[47:40] PIB_RD_MAILBOX Read (Egress) Mailbox Register PP_RD_MAILBOX[39:32] PIB_RD_MAILBOX Read (Egress) Mailbox Register PP_RD_MAILBOX[31:24] PIB_RD_MAILBOX Read (Egress) Mailbox Register PP_RD_MAILBOX[23:16] PIB_RD_MAILBOX Read (Egress) Mailbox Register PP_RD_MAILBOX[15:8] continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 289 Writing to the high word of this register sets the PP_EVENT.RD_MB_FULL flag. The procedure to use is described as part of the socket-based link controller section. Name Description 63:0 PP_RD_MAILBOX[63:0] Mailbox message from FX3 to the application processor EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 290: Pib_Wr_Mailbox
Write (Ingress) Mailbox Register PP_WR_MAILBOX[47:40] PIB_WR_MAILBOX Write (Ingress) Mailbox Register PP_WR_MAILBOX[39:32] PIB_WR_MAILBOX Write (Ingress) Mailbox Register PP_WR_MAILBOX[31:24] PIB_WR_MAILBOX Write (Ingress) Mailbox Register PP_WR_MAILBOX[23:16] PIB_WR_MAILBOX Write (Ingress) Mailbox Register PP_WR_MAILBOX[15:8] continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 291 Reading from these registers has no side effect. The procedure to use is described as part of the socket- based link controller section. Name Description 63:0 PP_WR_MAILBOX[63:0] Mailbox message from the application processor to FX3 EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 292: Pib_Error
Attempt to push to the active address thread which is not dma_ready SERIAL_PARITY_ERROR Received data in serial mode has parity error INVALID_STATE_ERROR State machine has transitioned to an invalid state continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 293 Adapter unable to service read request though buffer is available TH3_READ_FORCE_END 0x2D A read socket is wrapped up TH3_READ_BURST_ERR 0x2E A read socket with burstsize > 0 is switched before the 8-byte boundary EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 294: Pib_Eop_Eot
This register specifies how EOP is set in descriptors of ingress P-port sockets and how EOP is interpreted for egress P-port sockets. Name Description 31:0 PIB_EOP_EOT_CFG[31:0] This register specifies how EOP bits are set or interpreted for ingress and egress sockets, respec- tively. Stream mode behavior Packet mode behavior EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 295: Pib_Dll_Ctrl
Hardware does not reset the DLL when DLL code overrun/underrun occurs Hardware resets the DLL when DLL code overrun/underrun occurs DLL_RESET_N Resets the DLL DLL is reset DLL is not reset continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 296 DLL is not in phase lock DLL has achieved phase lock HIGH_FREQ 23 to 80 MHz 70 to 230 MHz ENABLE Drives the DLLEN input DLL is disabled (internally power gated) DLL is enabled EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 297: Pib_Wr_Threshold
The CPU writes to this field during initialization. The value written to this register is made available by hardware in PP_WR_THRESHOLD register. When AP writes to the PP_WR_THRESHOLD register this register is updated with the new value and WR_THRESHOLD interrupt is provided. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 298: Pib_Rd_Threshold
The CPU writes to this field during initialization. The value written to this register is made available by hardware in the PP_RD_THRESHOLD register. When AP writes to the PP_RD_THRESHOLD regis- ter, this register is updated with the new value and the RD_THRESHOLD interrupt is provided. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 299: Pib_Id
These registers are located in the CPU/Interconnect power and clock domains and are accessible even when power/clock of the block is switched off. Name Description 31:16 BLOCK_VERSION[15:0] Version number for the IP 15:0 BLOCK_ID[15:0] A unique number identifying the IP in the memory space EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 300: Pib_Power
For blocks that must perform initialization after reset before becoming operational, this signal will remain deasserted until initialization is complete. In other words, reading ACTIVE = 1 indicates that the block is initialized and ready for operation. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 301: Gpif Registers
PP_MODE = 1. If A7OVERRIDE = 1, register accesses are determined by beta (pp_access) instead. THREAD_IN_STATE Normal operation The thread number for an operation comes from the state description rather than the THREAD_CONFIG register (see GPIF_Modes for more information) continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 302 Inverted clock polarity (clock on negative edge) DATA_COMP_ENABLE Disable the data comparator Enable the data comparator ADDR_COMP_ENABLE Disable the address comparator Enable the address comparator CTRL_COMP_ENABLE Disable the control comparator Enable the control comparator EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 303: Gpif_Bus_Config
Normal operation of INT pin Override INT pin and connect to CTRL[15] DRQ_ASSERT_MODE Do nothing Assert DRQ on rising edge of DMA_READY. Typical case, DRQ_MODE = 2, this bit 1. continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 304 DQ is 24b wide DQ is 32b wide PIN_COUNT[1:0] Number of pins allocated to GPIF interface. Needs to be consistent with GCTL_IOMATRIX: 47-pin interface 43-pin interface 35-pin interface 31-pin interface EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 305: Gpif_Bus_Config2
STATE7 indicates Lambda number to be used for state number bit 7 STATE6 indicates Lambda number to be used for state number bit 6 STATE5 indicates Lambda number to be used for state number bit 5 EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 306: Gpif_Ad_Config
The active socket of thread DATA_THREAD is changed (full 5 bits) DOUT_SELECT Connect DOUT to the socket pointed to by AIN_DATA or EGRESS_DATA register (as determined by beta 'register_access') Connect DOUT to DATA_COUNTER continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 307 Direction controlled by the alpha: “dq_oen” Reserved Note that CTRL[2] can be OE, controlling the data output drivers directly, overriding what's specified here (this field should be set to 0 if that is used) EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 308: Gpif_Status
CPU tried to access waveform memory without clearing WAVEFORM_VALID CTRL_COMP_HIT Control comparator hits DATA_COMP_HIT Data comparator hits ADDR_COMP_HIT Address comparator hits CTRL_COUNT_HIT Control counter is at limit continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 309 Indicates that the SWITCH_TIMEOUT was reached (see WAVEFORM_SWITCH). This bit clears when a new WAVEFORM_SWTICH is initiated. GPIF_INTR Indicates that GPIF state machine has raised an interrupt. GPIF_DONE GPIF has reached the DONE state. Nonsticky. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 310: Gpif_Intr
Interrupt request corresponding to same bit in GPIF_STATUS DATA_COUNT_HIT Interrupt request corresponding to same bit in GPIF_STATUS ADDR_COUNT_HIT Interrupt request corresponding to same bit in GPIF_STATUS continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 311 Interrupt request corresponding to same bit in GPIF_STATUS SWITCH_TIMEOUT Interrupt request corresponding to same bit in GPIF_STATUS GPIF_INTR Interrupt request corresponding to same bit in GPIF_STATUS GPIF_DONE Interrupt request corresponding to same bit in GPIF_STATUS EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 312: Gpif_Intr_Mask
Mask bit that controls reporting of corresponding bit in GPIF_INTR DATA_COUNT_HIT Mask bit that controls reporting of corresponding bit in GPIF_INTR ADDR_COUNT_HIT Mask bit that controls reporting of corresponding bit in GPIF_INTR continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 313 Mask bit that controls reporting of corresponding bit in GPIF_INTR GPIF_INTR Mask bit that controls reporting of corresponding bit in GPIF_INTR GPIF_DONE Mask bit that controls reporting of corresponding bit in GPIF_INTR EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 314: Gpif_Ctrl_Bus_Direction
Two bits specify type of each bit in the 16-bit CTRL/ADDR Bus. Settings specified here may be overridden by GPIF_BUS_- CONFIG bits. Name Description 31:0 DIRECTION[31:0] Bit at (bit_number/2) has following direction: Input Output Bidirectional I/O Open drain I/O EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 315: Gpif_Ctrl_Bus_Default
Control Bus Default Values Register DEFAULT[7:0] Reset/initialization value for the CTRL[15:0] signals. Name Description 15:0 DEFAULT[15:0] One bit for each CTRL signal indicating default value Asserted (see POLARITY) Deasserted (see POLARITY) EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 316: Gpif_Ctrl_Bus_Polarity
Control Bus SIgnal Polarity Register POLARITY[7:0] Polarity of each of the CTRL[15:0] signals. Name Description 15:0 POLARITY[15:0] One bit for each CTRL signal indicating polarity Asserted when 1 Asserted when 0 EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 317: Gpif_Ctrl_Bus_Toggle
Description 15:0 TOGGLE[15:0] One bit for each CTRL signal indicating toggle mode Normal mode, set value from alpha/beta Toggle mode, toggle value when alpha/beta is 1, do nothing when 0 EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 318: Gpif_Ctrl_Bus_Select
Partial flag for thread 0–3 Empty/Full flag for current thread Partial flag for current thread PP_DRQR5 signal (see PP_DRQR5_MASK) 27–31 Connected to logic 0 (cannot be used together with CTRL_BUS_TOGGLE) EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 319: Gpif_Ctrl_Count_Config
Software writes one to reset/load the counter RELOAD Saturate on reaching the limit Reload on reaching the limit DOWN_UP Down count Up count ENABLE This counter is not used. This counter is used. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 320: Gpif_Ctrl_Count_Reset
Control Counter Reset Register RESET_LOAD[7:0] Configures the reset/load value of the control counter. Name Description 15:0 RESET_LOAD[15:0] Reset counter to this value. Reload to this value when limit is reached if specified. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 321: Gpif_Ctrl_Count_Limit
Control Counter Reset Register LIMIT[15:8] GPIF_CTRL_COUNT_LIMIT Control Counter Reset Register LIMIT[7:0] 0xFFFF Configures the limit value of the control counter. Name Description 15:0 LIMIT[15:0] Stop counting when counter reaches this value EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 322: Gpif_Addr_Count_Config
Hardware write 0 to signal that counter has reset Software writes one to reset/load the counter RELOAD Saturate on reaching the limit Reload on reaching the limit ENABLE This counter is not used. This counter is used. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 323: Gpif_Addr_Count_Reset
Address Counter Reset Register RESET_LOAD[7:0] Sets the reset/reload value of the data counter. Name Description 31:0 RESET_LOAD[31:0] Reset counter to this value. Reload to this value when limit is reached if specified. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 324: Gpif_Addr_Count_Limit
Address Counter Limit Register LIMIT[15:8] GPIF_ADDR_COUNT_LIMIT Address Counter Limit Register LIMIT[7:0] 0xFFFF Configures the limit value of the address counter Name Description 31:0 LIMIT[31:0] Stop counting when counter reaches this value. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 325: Gpif_State_Count_Config
Configures the first 16-bit state counter. Name Description SW_RESET Hardware write 0 to signal that counter has reset Software writes one to reset/load the counter ENABLE This counter is not used. This counter is used. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 326: Gpif_State_Count_Limit
LIMIT[7:0] 0xFFFF Configures the reset/load and limit values of counters. Name Description 15:0 LIMIT[15:0] Generate an output tick, reset and start counting again if enabled when this limit is reached. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 327: Gpif_Data_Count_Config
Hardware write 0 to signal that counter has reset Software writes one to reset/load the counter RELOAD Saturate on reaching the limit Reload on reaching the limit ENABLE This counter is not used. This counter is used. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 328: Gpif_Data_Count_Reset
Data Counter Reset Register RESET_LOAD[7:0] Sets the reset/reload value of the data counter. Name Description 31:0 RESET_LOAD[31:0] Reset counter to this value. Reload to this value when limit is reached if specified. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 329: Gpif_Data_Count_Limit
Data Counter Limit Register LIMIT[7:0] 0xFFFF Sets the limit value of the data counter. Name Description 31:0 LIMIT[31:0] Reload data counter if this limit is reached and reload is enabled. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 330: Gpif_Ctrl_Comp_Value
Control Comparator Value Register VALUE[15:8] GPIF_CTRL_COMP_VALUE Control Comparator Value Register VALUE[7:0] Sets the target value for the 16-bit control-bus comparator. Name Description 15:0 VALUE[15:0] Output true when CTRL bus matches this value EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 331: Gpif_Ctrl_Comp_Mask
Sets the comparison mask for the 16-bit control-bus comparator. Name Description 15:0 MASK[15:0] Bit at this bit position is a don't-care for comparison Bit at this bit position in the CTRL bus is to be used in comparison EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 332: Gpif_Data_Comp_Value
Data Counter Limit Register VALUE[15:8] GPIF_DATA_COUNT_LIMIT Data Counter Limit Register VALUE[7:0] Sets the target value for the 32-bit data comparator. Name Description 31:0 VALUE[31:0] Output true when Data bus matches this value. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 333: Gpif_Data_Comp_Mask
Sets the comparison mask for the 32-bit data comparator. Name Description 31:0 MASK[31:0] Bit at this bit position is a don't-care for comparison Bit at this bit position in the Data bus is to be used in comparison EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 334: Gpif_Addr_Comp_Value
Address Comparator Value Register VALUE[15:8] GPIF_ADDR_COMP_VALUE Address Comparator Value Register VALUE[7:0] Sets the target value for the 32-bit address comparator. Name Description 31:0 VALUE[31:0] Output true when Data bus matches this value. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 335: Gpif_Addr_Comp_Mask
Sets the comparison mask for the 32-bit data comparator. Name Description 31:0 MASK[31:0] Bit at this bit position is a don't-care for comparison Bit at this bit position in the CTRL bus is to be used in comparison EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 336: Gpif_Data_Ctrl
Software writes 1 to indicate a valid word is present in the address register. Hardware writes 0 to indi- cate that the data is used and new word can be written. IN_DATA_VALID[3:0] Indicates data available in INGRESS_DATA. Cleared by software when data processed. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 337: Gpif_Ingress_Data
Holds ingress data for the active socket in a thread. Name Description 31:0 DATA[31:0] Ingress Data. This register will hold only one word of GPIF_BUS_CONFIG.BUS_WIDTH. No packing/ unpacking is done. MSBs will be 0. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 338: Gpif_Egress_Data
Holds egress data for the active socket in a thread. Name Description 31:0 DATA[31:0] Egress data. This register will hold only one word of GPIF_BUS_CONFIG.BUS_WIDTH. No packing/ unpacking is done. MSBs are ignored. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 339: Gpif_Ingress_Address
Thread Ingress Address Register ADDRESS[23:16] GPIF_INGRESS_ADDRESS Thread Ingress Address Register ADDRESS[15:8] GPIF_INGRESS_ADDRESS Thread Ingress Address Register ADDRESS[7:0] Holds ingress address for the active socket in a thread. Name Description 31:0 ADDRESS[31:0] Ingress address EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 340: Gpif_Egress_Address
Thread Egress Address Register ADDRESS[23:16] GPIF_EGRESS_ADDRESS Thread Egress Address Register ADDRESS[15:8] GPIF_EGRESS_ADDRESS Thread Egress Address Register ADDRESS[7:0] Holds egress address for the active socket in a thread. Name Description 31:0 ADDRESS[31:0] Egress address EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 341: Gpif_Thread_Config
(as measured from the end of the burst) (3). Any additional group latency between the APs dma controller logic and the interface pins in both directions. continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 342 Can be modified by hardware as result of PP_DMA_XFER accesses (only for thread 0) Can be modified by hardware as result of alpha 'sample AIN' (all threads. Hardware can only modify bits [4:2] of this field) EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 343: Gpif_Lambda_Stat
GPIF_LAMBDA_STAT Lambda Status Register LAMBDA[15:8] GPIF_LAMBDA_STAT Lambda Status Register LAMBDA[7:0] 0x10000000 Provides the current state of the 32 Lambdas (inputs). Name Description 31:0 LAMBDA[31:0] Current value of the Lambda inputs EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 344: Gpif_Alpha_Stat
GPIF_ALPHA_STAT Alpha Status Register GPIF_ALPHA_STAT Alpha Status Register ALPHA[7:0] Provides the current state of the 8 Alphas (state machine early outputs). Name Description ALPHA[7:0] Current value of the Alpha signals EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 345: Gpif_Beta_Stat
Beta Status Register BETA[15:8] GPIF_BETA_STAT Beta Status Register BETA[7:0] Provides the current state of the 32 Betas (state machine late outputs). Name Description 31:0 BETA[31:0] Current value of the Beta signals EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 346: Gpif_Waveform_Ctrl_Stat
An error occurred PAUSE Write 1 here to pause GPIF. 0 to resume where left off. WAVEFORM_VALID Waveforms are no longer valid, stop operation and return outputs to default state EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 347 GPIF_WAVEFORM_CTRL_STAT 0xE0014118 The waveform memory is consistent and valid. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 348: Gpif_Waveform_Switch
Timeout for reaching TERMINAL STATE. Force switch on timeout. Timeout for hanging in current state. Timer resets on each transition. SWITCH_NOW Do not wait for TERMINAL_STATE, switch right away continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 349 10.7.40 GPIF_WAVEFORM_SWITCH (continued) DONE_ENABLE Enable checking for DONE_STATE and generation of GPIF_DONE. WAVEFORM_SWITCH Software sets this bit after programming the switch register. Hardware clears it after the switch is complete. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 350: Gpif_Waveform_Switch_Timeout
Waveform Timeout Register RESET_LOAD[7:0] Defines the timeout counter (in the number of state machine clock) for waveform switching. Effective only when TIME- OUT_ENABLE is set. Name Description 31:0 RESET_LOAD[31:0] Timeout value EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 351: Gpif_Beta_Deassert
BETA_DEASSERT does not apply. Betas remain asserted throughout the state. BETA_DEASSERT from the waveform descriptor applies to this beta. This is not honored for external betas, which always behave as if apply_deassert = 0. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 352: Gpif_Function
Truth table for transition function. Bit position X contains output when the 4 inputs constitute the value X in binary. For example, bit 2 = 1 means in3 = 0, in2 = 0, in1 = 1 and in0 = 0 will evaluate true for this function. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 353: Gpif_Left_Waveform
UNUSED GPIF_LEFT_WAVEFORM Left Edge Waveform Memory Register VALID BETA_DEASSERT REPEAT_COUNT[7:2] GPIF_LEFT_WAVEFORM Left Edge Waveform Memory Register REPEAT_COUNT[1:0] Beta[31:26] GPIF_LEFT_WAVEFORM Left Edge Waveform Memory Register Beta[25:18] continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 354 GPIF_LEFT_WAVEFORM Left Edge Waveform Memory Register Alpha_Left[1:0] f1[4:0] f0[4] GPIF_LEFT_WAVEFORM Left Edge Waveform Memory Register f0[3:0] Fd[4:1] GPIF_LEFT_WAVEFORM Left Edge Waveform Memory Register Fd[0] Fc[4:0] Fb[4:3] continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 355 Fc[4:0] Third input index. 17:13 Fb[4:0] Second input index. 12:8 Fa[4:0] Index to select the first input for transition functions out of 32 choices. NEXT_STATE[7:0] Next state on left transition EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 356: Gpif_Right_Waveform
UNUSED GPIF_RIGHT_WAVEFORM Right Edge Waveform Memory Register VALID BETA_DEASSERT REPEAT_COUNT[7:2] GPIF_RIGHT_WAVEFORM Right Edge Waveform Memory Register REPEAT_COUNT[1:0] Beta[31:26] GPIF_RIGHT_WAVEFORM Right Edge Waveform Memory Register Beta[25:18] continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 357 GPIF_RIGHT_WAVEFORM Right Edge Waveform Memory Register Alpha_Left[1:0] f1[4:0] f0[4] GPIF_RIGHT_WAVEFORM Right Edge Waveform Memory Register f0[3:0] Fd[4:1] GPIF_RIGHT_WAVEFORM Right Edge Waveform Memory Register Fd[0] Fc[4:0] Fb[4:3] continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 358 Fc[4:0] Third input index. 17:13 Fb[4:0] Second input index. 12:8 Fa[4:0] Index to select the first input for transition functions out of 32 choices. NEXT_STATE[7:0] Next state on left transition EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 359: P-Port Registers
Provides device ID information. This must be provided by boot ROM. This register is not writable when GCTL_CON- TROL.BOOTROM_EN = 0 to prevent spoofing. Name Description 15:0 DEVICE_ID[15:0] Provides a device ID. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 360: Pp_Init
Indicates system woke up through a power-on-reset or RESET# pin reset sequence. If firmware does not clear this bit it will stay 1 even through software reset, standby and suspend sequences. This bit is a shadow bit of GCTL_CONTROL. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 361: Pp_Config
After that DRQ may reassert depending on other settings. Burst mode, DRQ will deassert when BURSTSIZE words are transferred and will not reas- sert until DACK is deasserted. continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 362 PIB_CONFIG. BURSTSIZE Size of DMA bursts; only relevant when DRQMODE=1. 0–14 DMA burst size is 2BURSTSIZE words DMA burst size is infinite (DRQ deasserts on last cycle of transfer) EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 363: Pp_Intr_Mask
GPIF_INT Forward EVENT onto INT line SOCK_AGG_BH Forward EVENT onto INT line SOCK_AGG_BL Forward EVENT onto INT line SOCK_AGG_AH Forward EVENT onto INT line SOCK_AGG_AL Forward EVENT onto INT line EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 364: Pp_Drqr5_Mask
GPIF_INT Forward EVENT onto DRQ line SOCK_AGG_BH Forward EVENT onto DRQ line SOCK_AGG_BL Forward EVENT onto DRQ line SOCK_AGG_AH Forward EVENT onto DRQ line SOCK_AGG_AL Forward EVENT onto DRQ line EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 365: Pp_Sock_Mask
These registers contain a mask that indicates which sockets affect the SOCK_AGG_A and SOCK_AGG_B values, respec- tively. Name Description 31:0 SOCK_MASK[31:0] For socket <x>, bit <x> indicates: Socket does not affect SOCK_AGG_A/B Socket does affect SOCK_AGG_A/B EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 366: Pp_Error
P-Port BROS document. This register is also visible to firmware as PIB_ER- ROR. Name Description 14:10 GPIF_ERR_CODE[4:0] Mirror of corresponding field in PIB_ERROR PIB_ERR_CODE[5:0] Mirror of corresponding field in PIB_ERROR EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 367: Pp_Dma_Xfer
Read (Transfer from FX3 – Egress direction) Write (Transfer to FX3 – Ingress direction) DMA_ENABLE Disable ongoing transfer. If no transfer is ongoing ignore disable Enable data transfer DMA_SOCK[7:0] Processor specified socket number for data transfer EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 368: Pp_Dma_Size
The value read from this register is not valid unless DMA_XFER.SIZE_VALID is true. Name Description 15:0 DMA_SIZE[15:0] Size of DMA transfer. Number of bytes available for read/write when read, number of bytes to be read/written when written. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 369: Pp_Wr_Mailbox
P-Port Write (Ingress) Mailbox Registers WR_MAILBOX[39:32] PP_WR_MAILBOX P-Port Write (Ingress) Mailbox Registers WR_MAILBOX[31:24] PP_WR_MAILBOX P-Port Write (Ingress) Mailbox Registers WR_MAILBOX[23:16] PP_WR_MAILBOX P-Port Write (Ingress) Mailbox Registers WR_MAILBOX[15:8] continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 370 PIB_INTR.WR_MB_FULL is set. The expected action is that firmware reads the message and then clears PIB_INTR.WR_M- B_FULL, which will set PP_EVENT.WR_MB_EMPTY to signal AP for the next message (if needed). Name Description 63:0 WR_MAILBOX[63:0] Write mailbox message from AP EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 371: Pp_Mmio_Addr
These registers together form a 32-bit address for accessing the FX3 internal MMIO space. The address can point to any internal FX3 register. The bits PP_MMIO.MMIO_RD, PP_MMIO.MMIO_WR, PP_MMIO.MMIO_DONE are used to control the operation. Name Description 31:0 MMIO_ADDR[31:0] Address in MMIO register space to be used for access. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 372: Pp_Mmio_Data
Reading from these registers will return the data from the last MMIO_RD operation or the data written by Application Proces- sor, whichever is more recent. Name Description 31:0 MMIO_DATA[31:0] 32-bit data word for read or write transaction EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 373: Pp_Mmio
No MMIO operation is pending MMIO operation is being executed MMIO_WR No action Initiate write of MMIO_DATA to MMIO_ADDR MMIO_RD No action Initiate read from MMIO_ADDR, place data in MMIO_DATA EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 374: Pp_Event
The error code is indicated in PP_ERROR.PIB_ERR_CODE GPIF_INT State machine raised host interrupt SOCK_AGG_BH SOCK_STAT_B[15:8] is all zeroes At least one bit set in SOCK_STAT_B[15:8] continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 375 At least one bit set in SOCK_STAT_B[7:0] SOCK_AGG_AH SOCK_STAT_A[15:8] is all zeroes At least one bit set in SOCK_STAT_A[15:8] SOCK_AGG_AL SOCK_STAT_A[7:0] is all zeroes At least one bit set in SOCK_STAT_A[7:0] EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 376: Pp_Rd_Mailbox
P-Port Read (Egress) Mailbox Registers RD_MAILBOX[39:32] PP_RD_MAILBOX P-Port Read (Egress) Mailbox Registers RD_MAILBOX[31:24] PP_RD_MAILBOX P-Port Read (Egress) Mailbox Registers RD_MAILBOX[23:16] PP_RD_MAILBOX P-Port Read (Egress) Mailbox Registers RD_MAILBOX[15:8] continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 377 FULL is set. The expected action is that the Application Processor reads the message and interprets it and then clears PP_EVENT.RD_MB_FULL, which sets PIB_INTR.RD_MB_EMPTY to signal firmware for the next message (if needed). Name Description 63:0 RD_MAILBOX[63:0] Read mailbox message to AP EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 378: Pp_Sock_Stat
SOCK_STAT[31:0] For socket <x>, bit <x> indicates: Socket has no active descriptor or descriptor is not available (empty for write, occupied for read) Socket is available for reading or writing EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 379: Pp_Buf_Size_Cnt
PMMC P-Port space only! No registers exist in the PP space, only the socket registers are read for this from the adapter. The value of PP_BUF_SIZE_CNT is valid only if the PP_SOCK_STAT indicates ready for the corresponding socket. Name Description 15:0 SIZE_CNT[15:0] Buffer size of the corresponding write socket (0..31) EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 380: Usb Port Registers
SuperSpeed Egress EPM Interrupt PROT_EP_INT SuperSpeed Device Endpoint Interrupt PROT_INT SuperSpeed Protocol Layer Interrupt LNK_INT SuperSpeed Link Controller Interrupt CHGDET_INT USB Charger Detect Interrupt OTG_INT USB OTG Interrupt continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 381 UIB_INTR 0xE0030000 10.9.1 UIB_INTR (continued) DEV_CTL_INT Device USB Control Interrupt DEV_EP_INT Device EP Interrupt OHCI_INT OHCI Interrupt EHCI_INT EHCI Interrupt HOST_EP_INT Host EP Interrupt HOST_INT Host INT Status Register Interrupt EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 382: Uib_Intr_Mask
SuperSpeed Protocol Layer Interrupt LNK_INT SuperSpeed Link Controller Interrupt CHGDET_INT USB Charger Detect Interrupt OTG_INT USB OTG Interrupt DEV_CTL_INT Device USB Control Interrupt DEV_EP_INT Device EP Interrupt continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 383 UIB_INTR_MASK 0xE0030004 10.9.2 UIB_INTR_MASK (continued) OHCI_INT OHCI Interrupt EHCI_INT EHCI Interrupt HOST_EP_INT Host EP Interrupt HOST_INT Host INT Status Register Interrupt EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 384: Uib_Id
Name Description 31:16 BLOCK_VERSION[15:0] Version number for the IP 15:8 BLOCK_ID[15:0] A unique number identifying the IP in the memory space EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 385: Uib_Power
For blocks that must perform initialization after reset before becoming operational, this signal will remain deasserted until initialization is complete. In other words, reading active = 1 indicates block is initialized and ready for operation. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 386: Usb2 Hs/Fs/Ls Phy Registers
Vdat source enable for charger detect CHGRDET MIPS PHY Charger Detector Output (0 = host detected, 1 = charger detected) CHGRMODE MIPS PHY Charger Detector Mode continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 387 MIPS PHY Enable Sampling of ID line by PHY VLOAD Vendor Control Register Load Active Low ONCLOCK Enable 480-MHz Clock Output in Suspend DATABUS16_8 Data Bus Size RSVD 16-bit (only 16-bit mode is tested) EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 388: Phy_Conf
FS Driver Rise/Fall Time Control 19:18 LSRFTSEL[1:0] LS Driver Rise/Fall Time Control 17:16 ICPCTRL[1:0] PLL Charge Pump Current Control 15:14 HSTEDVSEL[1:0] Reference Voltage for High Speed Transmission continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 389 10:9 HSDEDVSEL[1:0] Reference Voltage for High Speed Disconnect HSDRVSLOPE[3:0] HS Driver Slope Control HSDRVAMPLITUDE[1:0] HS Driver Amplitude Control HSDRVTIMINGN[1:0] HS NMOS Driver Timing Control HSDRVTIMINGP HS PMOS Driver Timing Control EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 390: Phy_Chirp
5'h03 CHIRP 5'h04 LOOK_FOR_K1 5'h05 LOOK_FOR_J1 5'h06 LOOK_FOR_K2 5'h07 LOOK_FOR_J2 5'h08 LOOK_FOR_K3 5'h09 LOOK_FOR_J3 5'h0A SWITCH_XCVR_TO_FSPD 5'h0B WAIT_END_RESET_FSPD 5'h0D HIGH_SPEED 5'h0E SWITCH_XCVR_TO_FSPD_CHK_RESET 5'h0F CHECK_RESET 5'h10 HIGH_SPEED_SUSPEND 5'h11 WAIT_END_OF_RESUME 5'h12 WAIT_PP_AFTER_RESUME EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 391: Usb2 Device Controller Registers
Allow device to ACK SETUP data/status phase packets 25:23 TEST_MODE[2:0] USB Test Mode Normal operation Test_J Test_K Test_SE0_NAK Test_Packet [USB 2.0, §7.1.20, p 169; §9.4.9, Table 9−7, p 259] continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 392 During the USB RESET, this register will be cleared to zero. 15:8 COUNT[7:0] Number of errors detected To clear the error count write 0 to these bits. Error interrupt limit (COUNT ERR_LIMIT will cause UIB_ERR_INTR.ERRLIMIT interrupt) ERR_LIMIT[7:0] EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 393: Dev_Framecnt
MICROFRAME contains a count 0-7 which indicates which of the eight 125-microsecond microf- rames last occurred. This register is active only when FX3 is operating at High Speed (480 Mbps). EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 394: Dev_Pwr_Cs
Set SIGRSUME = 1 to drive the “K” state onto the USB bus. This should be done only by a device that is capable of remote wakeup, and then only during the SUSPEND state. To signal RESUME, set SIGRSUME = 1, waits 10-15 ms, then set SIGRSUME = 0. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 395: Dev_Setupdat
0xE003140C SETUP_LENGTH[15:8] DEV_SETUPDAT SETUPDAT0/1 Registers SETUP_LENGTH[7:0] DEV_SETUPDAT SETUPDAT0/1 Registers SETUP_INDEX[15:8] DEV_SETUPDAT SETUPDAT0/1 Registers SETUP_INDEX[7:0] DEV_SETUPDAT SETUPDAT0/1 Registers SETUP_VALUE[15:8] DEV_SETUPDAT SETUPDAT0/1 Registers SETUP_VALUE[7:0] DEV_SETUPDAT SETUPDAT0/1 Registers SETUP_REQUEST[7:0] continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 396 8-byte (2-long word) Storage for USB SETUP data on endpoint0. Name Description 63:48 SETUP_LENGTH[15:0] Setup data field 47:32 SETUP_INDEX[15:0] Setup data field 31:16 SETUP_VALUE[15:0] Setup data field 15:8 SETUP_REQUEST[7:0] Setup data field SETUP_REQUEST_TYPE[7:0] Setup data field EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 397: Dev_Toggle
Write ‘1’ to set data toggle to ‘1’. When both R and S are set, behavior is undefined. Write ‘1’ to reset data toggle to ‘0’. When both R and S are set, behavior is undefined. continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 398 DEV_TOGGLE 0xE0031414 10.11.5 DEV_TOGGLE (continued) ENDPOINT[3:0] Endpoint EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 399: Dev_Epi_Cs
Interrupt mask for SHORT bit ZERO_MASK Interrupt mask for ZERO bit DONE_MASK Interrupt mask for DONE bit BNAK_MASK Interrupt mask for BNAK bit COMMIT_MASK Interrupt mask for COMMIT bit continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 400 The End Point Type (Control on EP0 only) Control Isochronous Bulk Interrupt PAYLOAD[9:0] Max number of bytes transferred for each token Value 0 means 1024. Power up default value is 64. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 401: Dev_Epi_Xfer_Cnt
0). The value in this register is used only for generating the DONE interrupt for the endpoint, and does not affect the actual data transfers. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 402: Dev_Epo_Cs
Interrupt mask for SHORT bit ZERO_MASK Interrupt mask for ZERO bit DONE_MASK Interrupt mask for DONE bit BNAK_MASK Interrupt mask for BNAK bit COMMIT_MASK Interrupt mask for COMMIT bit continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 403 The End Point Type (Control on EP0 only) Control Isochronous Bulk Interrupt PAYLOAD[9:0] Max number of bytes transferred for each token Value 0 means 1024. Power up default value is 64. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 404: Dev_Epo_Xfer_Cnt
23:0 BYTES_REMAINING[23:0] Number of bytes remaining in the transfer. This value will never go negative (if more bytes are trans- ferred than remaining in counter, counter value stays at 0). EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 405: Dev_Ctrl_Intr_Mask
Set when the host has initiated USB RESET (2.5 µs single ended 0 on bus) SUSP Set when the host suspends the USB bus (USB SUSPEND) Set whenever a SOF occurs EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 406: Dev_Ctrl_Intr
Set when the host has initiated USB RESET (2.5 µs single ended 0 on bus) SUSP Set when the host suspends the USB (USB SUSPEND) Set whenever a SOF occurs EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 407: Dev_Ep_Intr_Mask
Name Description 31:16 EP_OUT[15:0] Bit <16+x> masks any interrupt from EPO_CS[x]. Enable Interrupt Mask (disable) Interrupt 15:8 EP_IN[15:0] Bit <x> masks any interrupt from EPI_CS[x] Enable Interrupt Mask (disable) Interrupt EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 408: Dev_Ep_Intr
DEV_EPO_CS register. Name Description 31:16 EP_OUT[15:0] Bit <16+x> is set if any interrupts in EPO_CS[x] are active 15:8 EP_IN[15:0] Bit <x> is set if any interrupt in EPI_CS[x] are active EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 409: Usb Controller Miscellaneous Registers
Charger Detect Control and Configuration Register ACA_RTRIM_ PHY_CHG_ ACA_POLL_INTERVAL[3:0] OVERRIDE DETECTED Name Description PHY_CHARGER_DETECT_EN PHY Charger Detection Enable 26:24 ACA_RTRIM[2:0] ACA Comparison Resistor Trim 23:16 ACA_ADC_OUT[7:0] ACA ADC Output continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 410 [ll65aca25 BROS 001-47035*D: Tables 5 & 6, p 32]] ACA_RTRIM_OVERRIDE ACA Comparison Resistor Trim Override ACA_POLL_INTERVAL[3:0] ACA OTG ID Polling Interval in 16ms increments, 0000 = 16ms PHY_CHG_DETECTED PHY USB Charger Present EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 411: Chgdet_Intr
OTG_ID_CHANGE CHANGE R/W1C R/W1C Name Description CHG_DET_CHANGE USB Charger Detect Change Interrupt OTG_ID_CHANGE OTG ID Change Interrupt Indicates that the decoded value of the USB OTG ID signal has changed. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 412: Chgdet_Intr_Mask
Charger Detect Interrupt Mask Register CHGDET_INTR_MASK Charger Detect Interrupt Mask Register CHG_DET_ OTG_ID_CHANGE CHANGE Name Description CHG_DET_CHANGE Mask interrupt Report interrupt to higher level OTG_ID_CHANGE Mask interrupt Report interrupt to higher level EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 413: Otg_Ctrl
Behavior depends on settings of HOST_ENABLE, and DEV_ENABLE fields and is defined in the HOST_ENABLE field. DEV_ENABLE Enables the USB 1.1/2.0 device function. Behavior depends on settings of HOST_ENABLE, and SSDEV_ENABLE fields and is defined in the HOST_ENABLE field. continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 414 VBUS_VALID Vbus Valid Vbus < 4.4V Vbus > 4.7V D– line state D+ line state DP_PD_EN D+ line state DM_PD_EN D– Pull-down Enable DP_PU_EN D+ Pull-up Enable OTG_ENABLE OTG Enable EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 415: Otg_Intr
A B-Device initiated SRP by pulsing the D+ signal. B_END_SESS_INT B_END_SESS Interrupt Set when B_END_SESS goes active B_SESS_VALID_INT B_SESS_VALID Change Interrupt Set when B_SESS_VALID changes. A_SESS_VALID_INT A_SESS_VALID Change Interrupt Set when A_SESS_VALID changes. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 416: Otg_Intr_Mask
Report B_END_SESS Interrupt to higher level Mask B_END_SESS event B_SESS_VALID_INT Report B_SESS_VALID changes to higher level Mask B_SESS_VALID change event A_SESS_VALID_INT Report A_SESS_VALID changes to higher level Mask A_SESS_VALID change event EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 417: Otg_Timer
General timer register to create OTG timeouts. This counter decrements down at 32-kHz standby clock. Name Description 31:0 OTG_TIMER_LOAD_VAL[31:0] Initial counter value. After OTG_TIMER_LOAD_VAL clocks, OTG_TIMER_TIMEOUT will trigger. Disable counter by writing 0 to this register. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 418: Usb End Point Manager Registers
If an under run occurs and the URUN_REPAIR_EN is set and this register bit is set, then EPM will start a timer (16-bit counter). If the repair is not complete after 65535*epm clock, EPM will raise the UIB_INTR.EPM_URUN_TIMEOUT interrupt. continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 419 These bits are cleared when the Protocol Layer 'activates' an End Point (as opposed to 'reactivating' it). In SuperSpeed mode all bits are cleared at once, in High-Speed mode only the bit for the Endpoint being activated is cleared. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 420: Iepm_Cs
This will reset the EPM Mux. EPM_FLUSH This will flush both the Egress and Ingress EPM. 27:16 WRITE_PTR[11:0] Write pointer of the ingress buffer. 11:0 READ_PTR[11:0] Read pointer of the ingress buffer. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 421: Iepm_Mult
(number of packets) is added to NUM_PACKETS in the IEPM_ENDPOINT register. 14:0 MULT_EN[14:0] Mult Enable for EP1-15. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 422: Eepm_Endpoint
26:11 EEPM_BYTE_COUNT[15:0] Number of bytes in the current buffer 10:0 PACKET_SIZE[10:0] Maximum packet size for this end-point. Typically this value is 1024, 512, 64, 1023 (last 2 for USB2 only). EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 423: Iepm_Endpoint
If the computed number of packets available is larger than 16, this number will be assumed to be 16 in the protocol block. 10:0 PACKET_SIZE[10:0] Maximum packet size for this end-point. Typically this value is 1024, 512, 64, 1023 (last 2 for USB2 only). EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 424: Iepm_Fifo
Endpoint number for this packet End of Transfer. Set for by the protocol layer short and zero length packets; forwarded to DMA Adapter. 10:0 BYTES[10:0] Number of bytes in the packet EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 425: Usb2 Host Controller Registers
This register contains device address to which host wishes to communicate. Host sends this address to device using set_address command. This address also used by SIE to append this address with different tokens. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 426: Host_Ep_Intr
Interrupt Requests for IN endpoints 0..15 when the EP is deactivated by Host Controller. 15:8 EPO_IRQ_TOP[15:0] Interrupt Requests for OUT endpoints 0..15 when the EP is deactivated by Host Controller. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 427: Host_Ep_Intr_Mask
This register contains interrupt status bit for 32 EPs. CPU reads this register to determine, which EP has triggered interrupt. Name Description 31:16 EPI_IRQ_MASK[15:0] Report IN endpoint interrupt to CPU 15:8 EPO_IRQ_MASK[15:0] Report OUT endpoint interrupt to CPU EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 428: Host_Toggle
Write ‘1’ to set data toggle to ‘1’ When both R and S are set, behavior is undefined. Write ‘1’ to reset data toggle to ‘0’. When both R and S are set, behavior is undefined. continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 429 HOST_TOGGLE 0xE003200C 10.14.4 DEV_TOGGLE (continued) ENDPOINT[3:0] Endpoint EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 430: Host_Shdl_Cs
This bit is set by software to indicate that periodic schedule is changed, and the scheduler may flip to the alternate schedule at the next frame boundary. This bit is cleared by hardware upon switching to new schedule. continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 431 BULK_CNTRL_PTR0[7:0] Asynchronous list pointer 0. Indicates the first Async schedule entry number in schedule 0. This pointer is used for the lower portion of the scheduler memory (schedule entry location 0-95). EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 432: Host_Shdl_Sleep
ASYNC_SLEEP_TIMMER*sie clock. Per EHCI spec the sleep time should be 10 µs. ASYNC_SLEEP_EN This bit will enable the sleep feature for the EHCI. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 433: Host_Resp_Base
Response Base Address Register BASE_ADDRESS[7:0] Name Description 31:0 BASE_ADDRESS[31:0] Base address where scheduler responses are written into memory. Responses are written in order of completion, wrapping at end of buffer (see UIB_HOST_RESP_CS) EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 434: Host_Resp_Cs
Response entry which, when written, would constitute an overflow error. MAX_ENTRY Maximum number of entries scheduler responses are written into memory. Responses are written in order of completion, wrapping at end of buffer (see UIB_HOST_RESP_CS) EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 435: Host_Active_Ep
This indicates if the OUT-EP is active or not. If there is a new schedule entry, this register needs to be Updated after the ASYNC_SHDL_CHNG or PERI_SHDL_CHNG is being set. Software should first clear the corresponding active bit upon HOST_EP_INTR interrupt and then read HOST_EP_DEAC- TIVATE to clear it. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 436: Ohci_Revision
OHCI Host Controller Revision Number Register 0xE0032010 OHCI_REVISION OHCI Host Controller Revision Number Register OHCI_REVISION OHCI Host Controller Revision Number Register OHCI_REVISION OHCI Host Controller Revision Number Register REV[7:0] 0x10 Name Description REV[7:0] Revision EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 437: Ohci_Control
ControlListEnable IsochronousEnable Note PLE and IE must both be set to 1 for the periodic list to be enabled. There is no difference in behavior between these two bits. PeriodicListEnable EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 438: Ohci_Command_Status
The HC sets this bit to one after it has stopped executing as a result of the Run/Stop bit being set to 0 by software. Run/Stop (Replacing the OwnerShipChangeRequest) Stop 17:16 SchedulingOverrunCount EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 439: Ohci_Interrupt_Status
OHCI Host Controller Interrupt Status Register OHCI_INTERRUPT_STATUS OHCI Host Controller Interrupt Status Register RHSC R/W1C R/W1C R/W1C R/W1C R/W1S R/W1S R/W1S R/W1S Name Description RHSC RootHubStatusChange FrameNumberOverflow ResumeDetected StartofFrame SchedulingOverrun EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 440: Ohci_Interrupt_Enable
This register can be used to enable any of the OHCI interrupts. To clear an interrupt enable bit, write to UIB_OHCI_INTER- RUPT_DISABLE. Name Description Master Interrupt Enable RHSC RootHubStatusChange FrameNumberOverflow ResumeDetected StartofFrame SchedulingOverrun EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 441: Ohci_Interrupt_Disable
This register can be used to disable any of the OHCI interrupts. To clear an interrupt enable bit, write to UIB_OHCI_INTER- RUPT_ENABLE. Name Description Master Interrupt Enable RHSC RootHubStatusChange FrameNumberOverflow ResumeDetected StartofFrame SchedulingOverrun EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 442: Ohci_Fm_Interval
OHCI Frame Control Information Register FSMPS[7:0] 0x27F0 OHCI_FM_INTERVAL OHCI Frame Control Information Register FI[14:8] OHCI_FM_INTERVAL OHCI Frame Control Information Register FI[7:0] 0x752F Name Description FrameIntervalToggle 30:16 FSMPS[14:0] FSLargestDataPacket 14:0 FI[14:0] FrameInterval EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 443: Ohci_Fm_Remaining
Current Value of Remaining Frame Count Register 0xE0032040 OHCI_FM_INTERVAL OHCI Frame Control Information Register OHCI_FM_INTERVAL OHCI Frame Control Information Register FR[14:8] OHCI_FM_INTERVAL OHCI Frame Control Information Register FR[7:0] Name Description FrameRemainingToggle 14:0 FR[14:0] FrameRemaining EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 444: Ohci_Fm_Number
Full Speed Frame Number Register 0xE0032044 OHCI_FM_NUMBER Full Speed Frame Number Register OHCI_FM_NUMBER Full Speed Frame Number Register FN[15:8] OHCI_FM_NUMBER Full Speed Frame Number Register FN[7:0] Name Description 15:0 FN[15:0] FrameNumber EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 445: Ohci_Periodic_Start
Periodic Schedule Start Register PS[7:0] 0x6977 Value indicating time where HC should start executing periodic schedule. Name Description 15:0 PS[15:0] PeriodicStart The Default is: 90% * FI = 90% * 0x752F = 0x6977 EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 446: Ohci_Ls_Threshold
LSTHRESHOLD Register OHCI_LS_THRESHOLD LSTHRESHOLD Register LST[11:8] OHCI_LS_THRESHOLD LSTHRESHOLD Register LST[7:0] 0x628 Value which is compared to the FrameRemaining field prior to initiating a Low Speed. Name Description 11:0 LST[11:0] LSThreshold EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 447: Ohci_Rh_Port_Status
Host Logic that it should do a resume and then go clear the PSS bit. There is no real functionality being added, this is only trying to emulate the OHCI interface better. PRSC PortResetStatusChange PSSC PortSuspendStatusChange PESC PortEnableStatusChange ConnectStatusChange continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 448 OHCI_RH_PORT_STATUS 0xE0032054 10.14.21 OHCI_RH_PORT_STATUS (continued) (read) PortResetStatus (write) SetPortReset (read) PortSuspendStatus (write) SetPortSuspend (read) PortEnableStatus (write) SetPortEnable (read) CurrentConnectStatus (write) ClearPortEnable EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 449: Ohci_Eof
EOF1[7:0] 0x0050 Name Description 31:16 EOF2[15:0] EOF2 Time (default: 10 bit times * 2.5 clocks/bit => 25) 15:0 EOF1[15:0] EOF1 Time (default: 32 bit times * 2.5 clocks/bit => 80) EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 450: Ehci_Hccparams
Isochronous Scheduling Threshold (In this implementation the scheduler will cache 1 micro-frame worth of data. Appropriate value will be programmed to ensure correct functionality). ASYNC_PARK_CAP Asynchronous Schedule Park Capability ADDR_64_BIT_CAP 64-bit Addressing Capability EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 451: Ehci_Usbcmd
ASYNC_SHDL_ PER_SHDL_EN Name Description 23:16 INT_THRESHOLD_CTRL[7:0] Interrupt Threshold Control ASYNC_SHDL_PRK_EN Asynchronous Schedule Park Mode Enable ASYNC_SHDL_PRK_CNT[1:0] Asynchronous Schedule Park Mode Count ASYNC_SHDL_EN Asynchronous Schedule Enable PER_SHDL_EN Periodic Schedule Enable Run/Stop EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 452: Ehci_Usbsts
Note This field does not assert for SETUP+IN(STATUS) qTDs with no data phase. The workaround is to use the HOST_EP_INTR[0] along with the transaction response that gets written into SRAM for HCD. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 453: Ehci_Usbintr
EHCI Interrupt Register HOST_SYS_ERR PORT_CHANGE_ USBERRINT_IE USBINT_IE DET_IE Name Description HOST_SYS_ERR_IE Host System Error Interrupt Enable PORT_CHANGE_DET_IE Port Change Interrupt Enable USBERRINT_IE USB Error Interrupt Enable USBINT_IE USB Interrupt Enable EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 454: Ehci_Frindex
Frame Index Register FRINDEX[7:0] Name Description 13:0 FRINDEX[13:0] The value indicates the Frame on which the scheduler is operating. This value is also used to achieve interrupt endpoint polling duration. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 455: Ehci_Configflag
EHCI_CONFIGFLAG 0xE0032070 10.14.28 EHCI_CONFIGFLAG Configure Flag Register EHCI_CONFIGFLAG Configure Flag Register 0xE0032070 EHCI_CONFIGFLAG Configure Flag Register EHCI_CONFIGFLAG Configure Flag Register EHCI_CONFIGFLAG Configure Flag Register Name Description Configure Flag EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 456: Ehci_Portsc
PORT_CONNECT RESUME R/W1C R/W0C R/W1C R/W1S R/W1S Name Description PORT_RESET_FW Port Reset (virtual register of PORT_RESET from firmware) PORT_RESUME_HW Hardware Initiated Resume Active PORT_OWNER Port Owner continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 457 Port Reset, and also whether the attached device is High-Speed (PORT_EN == 1). PORT_SUSPEND Suspend F_PORT_RESUME Force Port Resume PORT_EN_C Port Enable/Disable Change PORT_EN Port Enabled/Disabled PORT_CONNECT_C Connect Status Change PORT_CONNECT Current Connect Status EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 458: Ehci_Eof
EOF1[7:0] 0x0023 Name Description 31:16 EOF2[15:0] EOF2 Time (default: 64 bit times / 16 bits/clock -> 4) 15:0 EOF1[15:0] EOF1 Time (default: 560 bit times / 16 bits/clock -> 35) EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 459: Shdl_Chng_Type
This register defines when the Scheduler should update its internal active bits with the HOST_ACTIVE_EP register per each Name Description 31:16 EOF2[15:0] Update at Micro-frame boundary Update at Frame boundary 15:0 EOF1[15:0] Update at Micro-frame boundary Update at Frame boundary EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 460: Shdl_State_Machine
Scratch Write state2 SCRATCH_WRITE1 Scratch Write state1 SHDL_WRITE Scheduler write state LAST_EVAL Last Eval State WAIT_TP_STUPD Wait for TP status state EXECUTE Execute State ASYNC_SLEEP Async Sleep state continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 461 READ_EP0_0 Read EP0 state0 LOAD_SHDL_MEM Load scheduler memory state SCRATCH_READ2 Scratch Read state2 SCRATCH_READ1 Scratch Read state1 SCRATCH_READ0 Scratch Read state0 FETCH Fetch State LOAD_PTR Load Pointer State IDLE Idle EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 462: Shdl_Internal_Status
TP_TIMEOUT TP timeout TP_PID_ERROR TP PID error TP_BABBLE TP Babble TP_PORT_ERROR TP Port error TP_PHY_ERROR TP PHY rxerror TP_CRC16_ERROR TP CRC16 Error TP_DT_MISMATCH TP DT mismatch continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 463 TP_STALL TP STALL TP_NYET TP NYET TP_NAK TP NAK TP_ACK TP ACK EP0_IN EP0 IN state EP0_OUT EP0 OUT state EP0_SETUP EP0 SETUP state FRAME_FIT Frame Fit EP_DONE EP Done EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 464: Shdl_Ohci
SHDL_OHCI Scheduler Memory Register, OHCI Format EP0_CODE[1:0] BYPASS_ERROR MMULT[1:0] RESP_RATE[7:5] SHDL_OHCI Scheduler Memory Register, OHCI Format RESP_RATE[4:0] POLLING_RATE[7:5] SHDL_OHCI Scheduler Memory Register, OHCI Format POLLING_RATE[4:0] MAX_PKT_SIZE[10:8] continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 465 In result, the MMIO address for lower section would be x400-x57C and for upper portion would be x580- x6FC. Software can update the appropriate portion of the memory based on the PERI_SHDL_STATUS/ASYNC_SHDL_STA- TUS bits in the UIB_HOST_SHDL_CS register. continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 466 Should be programmed to zero for OHCI. Nak Count Reload (RL). This field contains a value, which is used by the host controller to reload the Nak Counter field. continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 467 [3:0]: EP number, Values: 0-15 [4]: EP Direction, 1: OUT, 0: IN The direction bit is not used for EP0. Scheduler uses the EP0_code to determine the direction of the EP0 transaction. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 468: Shdl_Ehci
SHDL_EHCI Scheduler Memory Register, EHCI Format EP0_CODE[1:0] BYPASS_ERROR MMULT[1:0] RESP_RATE[7:5] SHDL_EHCI Scheduler Memory Register, EHCI Format RESP_RATE[4:0] POLLING_RATE[7:5] SHDL_EHCI Scheduler Memory Register, EHCI Format POLLING_RATE[4:0] MAX_PKT_SIZE[10:8] continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 469 In result, the MMIO address for lower section would be x800-x97C and for upper portion would be x980- xAFC. Software can update the appropriate portion of the memory based on the PERI_SHDL_STATUS/ASYNC_SHDL_STA- TUS bits in the UIB_HOST_SHDL_CS register. continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 470 Do issue ping token for high-speed OUT 22:19 RL[3:0] Nak Count Reload (RL). This field contains a value, which is used by the host controller to reload the Nak Counter field. continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 471 [3:0]: EP number, Values: 0-15 [4]: EP Direction, 1: OUT, 0: IN The direction bit is not used for EP0. Scheduler uses the EP0_code to determine the direction of the EP0 transaction. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 472: Usb3 Link Controller Registers
Enable host LDN detection (see USB ECN#001) FORCE_POWER_PRESENT Force PowerPresent from PHY On LCW_IGNORE_RSVD Check reserved bits in Link Control Word are 0 (LCW) Ignore reserved bits in Link Control Word (LCW) EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 473: Lnk_Intr
U2_INACTIVITY_TIMEOUT U2 Inactivity Timeout Interrupt PHY_ERROR PHY Error Count Threshold Reached LINK_ERROR Link Error Count Threshold Reached BAD_LCW Illegal LCW received (see LNK_CONTROL_WORD for details) continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 474 LGO_U3 Received Interrupt LGO_U2 LGO_U2 Received Interrupt LGO_U1 LGO_U1 Received Interrupt LCRD LCRD Received Interrupt LBAD LBAD Received Interrupt LRTY LRTY Received Interrupt LGOOD LGOOD Received Interrupt LTSSM_STATE_CHG LTSSM State Change Interrupt EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 475: Lnk_Intr_Mask
U2_INACTIVITY_TIMEOUT U2 Inactivity Timeout Interrupt PHY_ERROR PHY Error Count Threshold Reached LINK_ERROR Link Error Count Threshold Reached BAD_LCW Illegal LCW received (see LNK_CONTROL_WORD for details) continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 476 LGO_U3 Received Interrupt LGO_U2 LGO_U2 Received Interrupt LGO_U1 LGO_U1 Received Interrupt LCRD LCRD Received Interrupt LBAD LBAD Received Interrupt LRTY LRTY Received Interrupt LGOOD LGOOD Received Interrupt LTSSM_STATE_CHG LTSSM State Change Interrupt EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 477: Lnk_Error_Conf
Rx Header Buffer Credit Advertisement CREDIT_HP_TIMER Timeout Count Enable CREDIT_HP_TIMER timeout before receipt of LCRD_x Link Command during Rx Header Buffer Credit Advertisement [USB 3.0: §7.3.7, p 7−30…7−31] continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 478 Received Rx Header Sequence Number does not match what is expected. [USB 3.0: §7.3.3.3, p 7−28] HP_TIMEOUT_EN PENDING_HP_TIMER Timeout Count Enable Header Packet acknowledgement has not been received by PENDING_HP_TIMEOUT. [USB 3.0: §7.2.4.1.10, p 7−21] EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 479: Lnk_Error_Status
HDR_ADV_LCRD_EV Indicates this error (see LNK_ERROR_CONF for description) occurred since this bit was last cleared by firmware. continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 480 Indicates this error (see LNK_ERROR_CONF for description) occurred since this bit was last cleared by firmware. HP_TIMEOUT_EV Indicates this error (see LNK_ERROR_CONF for description) occurred since this bit was last cleared by firmware. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 481: Lnk_Error_Count
The Link Error Count keeps track of the number of errors for which the Link Layer Block had to transition to the Recovery State before resuming normal operation. Counting of errors in each class can be enabled through the LINK_ERROR_CONF register. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 482: Lnk_Error_Count_Threshold
Threshold values for asserting Error Count Interrupts. These values are the error count limits after which the respective inter- rupts are generated. Name Description 31:16 PHY_ERROR_THRESHOLD[15:0] PHY Error Count Threshold for Interrupt Generation 15:0 LINK_ERROR_THRESHOLD[15:0] Link Error Count Threshold for Interrupt Generation EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 483: Lnk_Phy_Conf
PHY_MODE[1:0] [PIPE 3.0] Name Description RX_TERMINATION_ENABLE PHY Receiver Termination Enable RX_TERMINATION_OVR_VAL PHY Receiver Termination Override Value Removed Present RX_TERMINATION_OVR PHY Receiver Termination Override PHY_MODE[1:0] PHY Operation Mode USB Super Speed EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 484: Lnk_Phy_Mpll_Status
Spread Spectrum Enable MPLL_MULTIPLIER[6:0] MPLL Frequency Multiplier Control Default values (based on clock crystal frequency): 19.2 MHz  0x02 26 MHz  0x60 38.4 MHz  0x41 52 MHz  0x30 EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 485: Lnk_Phy_Tx_Trim
TX Amplitude (Low Swing Mode) in 10 mv units 20:14 PCS_TX_SWING_FULL[6:0] TX Amplitude (Full Swing Mode) in 10 mv units 12:7 PCS_TX_DEEMPH_6DB[5:0] TX de-emphasis at 6dB PCS_TX_DEEMPH_3P5DB[5:0] TX de-emphasis at 3.5dB EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 486: Lnk_Phy_Error_Conf
PHY_ERROR_EB_UND_EN Enable Counting of Elastic Buffer Underflow (RxStatus == 3'b110) PHY_ERROR_EB_OVR_EN Enable Counting of Elastic Buffer Overflow (RxStatus == 3'b101) PHY_ERROR_DECODE_EN Enable Counting of 8b/10b Decode Errors (RxStatus == 3'b100) EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 487: Lnk_Phy_Error_Status
RX_ERROR_CRC5_EV Indicates this error (see LNK_PHY_ERROR_CONF for description) occurred since this bit was last cleared by firmware. continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 488 Indicates this error (see LNK_PHY_ERROR_CONF for description) occurred since this bit was last cleared by firmware. PHY_ERROR_DECODE_EV Indicates this error (see LNK_PHY_ERROR_CONF for description) occurred since this bit was last cleared by firmware. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 489: Lnk_Device_Power_Control
When host requests transition to U2, automatically accept (send LAU) or rejects (send LXU) depend- ing on pending activity. The interrupt RX_U2 is still raised for firmware to monitor, take additional power saving actions. continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 490 LCW is transmitted. TX_U1 Transmit LGO_U1 - Request to go to U1 Power State (send LGO_U1). This bit is cleared by hard- ware when the LCW is transmitted. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 491: Lnk_Ltssm_State
Link Training Status State Machine (LTSSM) State Register LTSSM_STATE[5:0] USB 3.0 interface link layer state control and status Name Description LTSSM_STATE[5:0] LTSSM State. See USBLNK_LTSSM Tab in USB-RegMap.xls for more details. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 492: Lnk_Lfps_Observe
LFPS Sequence detected since last cleared by CPU RESET_DET LFPS Sequence detected since last cleared by CPU PING_DET LFPS Sequence detected since last cleared by CPU POLLING_DET LFPS Sequence detected since last cleared by CPU EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 493: Lnk_Compliance_Pattern_0
0. Name Description TXONESZEROS Enable TXONESZEROS (PIPE PHY Transmit Signal) LFPS LFPS On/Off DEEMPHASIS De-emphasis On/Off SCRAMBLED Scramble On/Off Symbol Type Data (D) Symbol (K) CP[7:0] Compliance Pattern EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 494: Lnk_Compliance_Pattern_1
USB 3.0 PHY configuration values for compliance pattern 1. Name Description TXONESZEROS Enable TXONESZEROS (PIPE PHY Transmit Signal) LFPS LFPS On/Off DEEMPHASIS De-emphasis On/Off SCRAMBLED Scramble On/Off Symbol Type Data (D) Symbol (K) CP[7:0] Compliance Pattern EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 495: Lnk_Compliance_Pattern_2
USB 3.0 PHY configuration values for compliance pattern 2. Name Description TXONESZEROS Enable TXONESZEROS (PIPE PHY Transmit Signal) LFPS LFPS On/Off DEEMPHASIS De-emphasis On/Off SCRAMBLED Scramble On/Off Symbol Type Data (D) Symbol (K) CP[7:0] Compliance Pattern EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 496: Lnk_Compliance_Pattern_3
USB 3.0 PHY configuration values for compliance pattern 3. Name Description TXONESZEROS Enable TXONESZEROS (PIPE PHY Transmit Signal) LFPS LFPS On/Off DEEMPHASIS De-emphasis On/Off SCRAMBLED Scramble On/Off Symbol Type Data (D) Symbol (K) CP[7:0] Compliance Pattern EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 497: Lnk_Compliance_Pattern_4
USB 3.0 PHY configuration values for compliance pattern 4. Name Description TXONESZEROS Enable TXONESZEROS (PIPE PHY Transmit Signal) LFPS LFPS On/Off DEEMPHASIS De-emphasis On/Off SCRAMBLED Scramble On/Off Symbol Type Data (D) Symbol (K) CP[7:0] Compliance Pattern EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 498: Lnk_Compliance_Pattern_5
USB 3.0 PHY configuration values for compliance pattern 5. Name Description TXONESZEROS Enable TXONESZEROS (PIPE PHY Transmit Signal) LFPS LFPS On/Off DEEMPHASIS De-emphasis On/Off SCRAMBLED Scramble On/Off Symbol Type Data (D) Symbol (K) CP[7:0] Compliance Pattern EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 499: Lnk_Compliance_Pattern_6
USB 3.0 PHY configuration values for compliance pattern 6. Name Description TXONESZEROS Enable TXONESZEROS (PIPE PHY Transmit Signal) LFPS LFPS On/Off DEEMPHASIS De-emphasis On/Off SCRAMBLED Scramble On/Off Symbol Type Data (D) Symbol (K) CP[7:0] Compliance Pattern EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 500: Lnk_Compliance_Pattern_7
USB 3.0 PHY configuration values for compliance pattern 7. Name Description TXONESZEROS Enable TXONESZEROS (PIPE PHY Transmit Signal) LFPS LFPS On/Off DEEMPHASIS De-emphasis On/Off SCRAMBLED Scramble On/Off Symbol Type Data (D) Symbol (K) CP[7:0] Compliance Pattern EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 501: Lnk_Compliance_Pattern_8
USB 3.0 PHY configuration values for compliance pattern 8. Name Description TXONESZEROS Enable TXONESZEROS (PIPE PHY Transmit Signal) LFPS LFPS On/Off DEEMPHASIS De-emphasis On/Off SCRAMBLED Scramble On/Off Symbol Type Data (D) Symbol (K) CP[7:0] Compliance Pattern EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 502: Usb3 Protocol Layer Registers
Logic is not disabled. Logic is disabled. SEQ_NUM_CONFIG This bit indicates if the seq numbers are EP based or Stream ID (Socket) based EP based Stream ID (Socket) based continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 503 During the USB enumeration process, the host sends a device a unique 7-bit address, which the USB core copies into this register. The USB Core will automatically respond only to its assigned address. During the USB RESET, this register will be cleared to zero. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 504: Prot_Intr
Set whenever a LMP port capability is received but the Link Speed is not ‘1’ or Num HP buf- fer is not ‘4’ or bit zero of the Direction is not ‘1’. STATUS_STAGE Set when host completes Status Stage of a Control Transfer continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 505 LMP was sent back. LMP_RCV_EV A LMP was received and placed in PROT_LMP_PACKET_RX. The LMP may have been recognized and processed as well (leading to other interrupts in this register). EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 506: Prot_Intr_Mask
Report interrupt to CPU LMP_INVALID_PORT_CAP_EN Report interrupt to CPU STATUS_STAGE Report interrupt to CPU HOST_ERR_EN Report interrupt to CPU SUTOK_EN Report interrupt to CPU ITP_EN Report interrupt to CPU continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 507 TIMEOUT_PORT_CFG_EN Report interrupt to CPU TIMEOUT_PORT_CAP_EN Report interrupt to CPU LMP_PORT_CFG_EN Report interrupt to CPU LMP_PORT_CAP_EN Report interrupt to CPU LMP_UNKNOWN_EN Report interrupt to CPU LMP_RCV_EN Report interrupt to CPU EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 508: Prot_Framecnt
The delta value in the last ITP received 13:0 SS_MICROFRAME[13:0] MICROFRAME counter which indicates which of the 8 125-microsecond micro-frames last occurred. This is based on ITPs received from Host EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 509: Prot_Itp_Time
ITP Time Free Running Counter COUNTER24[7:0] This register contains a free running counter running at 125MHz (spread clock) and is used for the PROT_ITP_TIMESTAMP time stamps. Name Description 23:0 COUNTER24[23:0] Current counter value. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 510: Prot_Itp_Timestamp
This register contains a time-stamp of the last ITP received that can be used to calculate BIA messages when needed. Name Description 31:24 MICROFRAME_LSB[7:0] LSBs of MICROFRAME field of ITP when timestamp was taken. 23:0 TIMESTAMP[23:0] Timestamp from a free running counter at 125MHz of the last ITP reception. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 511: Prot_Setup_Dat
Received SETUP Packet Data Register SETUP_INDEX[7:0] PROT_SETUP_DAT Received SETUP Packet Data Register SETUP_VALUE[15:8] PROT_SETUP_DAT Received SETUP Packet Data Register SETUP_VALUE[7:0] PROT_SETUP_DAT Received SETUP Packet Data Register SETUP_REQUEST[15:8] continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 512 8-byte (2-long word) Storage for USB SETUP data received on EP0 Name Description 63:48 SETUP_LENGTH[15:0] Setup data field 47:32 SETUP_INDEX[15:0] Setup data field 31:16 SETUP_VALUE[15:0] Setup data field 15:8 SETUP_REQUEST[7:0] Setup data field SETUP_REQUEST_TYPE[7:0] Setup data field EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 513: Prot_Seq_Num
3. Then software should poll for SEQ_VALID to go 1 to and that will return the End-point’s sequence numbers. To write the sequence number field: 1. Software should poll for SEQ_VALID to be 1 EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 514 Returned as part of a read operation. 12:8 SEQUENCE_NUMBER[4:0] Packet sequence number of next packet to receive/transmit. Set by hardware if COMMAND=0, set by software when COMMAND=1. ENDPOINT[3:0] Endpoint Number EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 515: Prot_Ep_Intr
EPI_CS/EPO_CS registers. Name Description 31:16 EP_OUT[15:0] Bit <16+x> indicates an interrupt from EPO_CS[x] 15:0 EP_IN[15:0] Bit <x> indicates an interrupt from EPI_CS[x] EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 516: Prot_Ep_Intr_Mask
Endpoint Interrupt Mask EP_IN[7:0] Per endpoint masking of interrupt reporting. Name Description 31:16 EP_OUT[15:0] Bit <16+x> masks any interrupt from EPO_CS[x] 15:0 EP_IN[15:0] Bit <x> masks any interrupt from EPI_CS[x] EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 517: Prot_Epi_Cs1
Interrupt mask for FIRST_ACK_NUMP_0 bit STREAM_ERROR_MASK Interrupt mask for STREAM_ERROR bit DBTERM_MASK Interrupt mask for DBTERM bit HBTERM_MASK Interrupt mask for HBTERM bit OOSERR_MASK Interrupt mask for OOSERR bit continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 518 Set VALID=1 to activate an endpoint, and VALID=0 to de-activate it. All USB endpoints default to invalid. An endpoint whose VALID bit is 0 does not respond to any USB traffic. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 519: Prot_Epi_Cs2
Number of packets to be sent per service interval. Maximum can be 48 (Max burst size* Mult field) TYPE[1:0] Endpoint type (EP0 supports CONTROL only) BULK CONTROL (only valid for EP0) EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 520: Prot_Epi_Unmapped_Stream
Disabled Prime Pipe DFR Prime Pipe Idle Start Stream Move Data Error 15:0 STREAM_ID[15:0] The StreamID of the current stream activated (or requested to be activated) by the protocol layer. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 521: Prot_Epi_Mapped_Stream
Stream is unmapped (not in use by the corresponding EP's SPSM). 19:16 EP_NUMBER[3:0] The Endpoint number of the stream connected to the corresponding socket by firmware. 15:0 STREAM_ID[15:0] The StreamID of the stream connected to the corresponding socket by firmware. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 522: Prot_Epo_Cs1
Interrupt mask for DBTERM bit HBTERM_MASK Interrupt mask for HBTERM bit OOSERR_MASK Interrupt mask for OOSERR bit SHORT_MASK Interrupt mask for SHORT bit ZERO_MASK Interrupt mask for ZERO bit continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 523 Set VALID=1 to activate an endpoint, and VALID=0 to de-activate it. All USB endpoints default to invalid. An endpoint whose VALID bit is 0 does not respond to any USB traffic. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 524: Prot_Epo_Cs2
Number of packets to be sent per service interval. Maximum can be 48 (Max burst size* Mult field) TYPE[1:0] Endpoint type (EP0 supports CONTROL only) BULK CONTROL (only valid for EP0) EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 525: Prot_Epo_Unmapped_Stream
Disabled Prime Pipe DFR Prime Pipe Idle Start Stream Move Data Error 15:0 STREAM_ID[15:0] The StreamID of the current stream activated (or requested to be activated) by the protocol layer. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 526: Prot_Epo_Mapped_Stream
Stream is unmapped (not in use by the corresponding EP's SPSM). 19:16 EP_NUMBER[3:0] The Endpoint number of the stream connected to the corresponding socket by firmware. 15:0 STREAM_ID[15:0] The StreamID of the stream connected to the corresponding socket by firmware. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 527: Usb Port - Superspeed Ingress Socket Registers
Name Description 31:16 BLOCK_VERSION[15:0] Version number for the IP 15:8 BLOCK_ID[15:0] A unique number identifying the IP in the memory space EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 528: Uibin_Power
In other words, reading active = 1 indicates block is initialized and ready for operation. This bit is a copy of UIB_POWER.active. Preferably use UIB_POWER register instead. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 529: I2S Registers
Do nothing Clear transmit FIFO (After TX_CLEAR is set, software must wait for TX*_DONE before clearing it) 12:11 MODE[1:0] I2S Mode Left Justified Mode Right Justified Mode. continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 530 A small, integral, but undefined number of samples will be transmitted after this bit is set to 1 (to ensure no hanging samples). When one of the descriptors is modified in socket, no samples from the old descriptor will be output (all FIFO's will be cleared). EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 531: I2S_Status
No data is currently available for output, but socket does not indicate empty. Only relevant when DMA_MODE=1. Non sticky. PAUSED Output is paused (PAUSE has taken effect). Non sticky continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 532 MODE=1 this is defined as socket is EOT and shift register empty. Note that this field will only assert after a transmission was started - it's power up state is 0. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 533: I2S_Intr
Set by hardware when corresponding STATUS asserts, cleared by software. TXL_SPACE Set by hardware when corresponding STATUS asserts, cleared by software. TXL_DONE Set by hardware when corresponding STATUS asserts, cleared by software. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 534: I2S_Intr_Mask
TXR_HALF Report interrupt to CPU TXR_SPACE Report interrupt to CPU TXR_DONE Report interrupt to CPU TXL_HALF Report interrupt to CPU TXL_SPACE Report interrupt to CPU TXL_DONE Report interrupt to CPU EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 535: I2S_Egress_Data_Left
It will result in ERROR if the FIFO is full. The size of the transmit FIFO is configured at design time. Name Description 31:0 DATA[31:0] Sample to be written to the peripheral in registered mode. Number of bits taken depends on sample size (see I2S_CONFIG), other bits are ignored. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 536: I2S_Egress_Data_Right
It will result in ERROR if the FIFO is full. The size of the transmit FIFO is configured at design time. Name Description 31:0 DATA[31:0] Sample to be written to the peripheral in registered mode. Number of bits taken depends on sample size (see I2S_CONFIG), other bits are ignored. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 537: I2S_Counter
Counter increments by one for every sample written on output. Counts L+R as one sample in stereo mode. This counter is more reliable to implement a software PLL because of more periodic behavior. This counter will be reset to 0 when I2S_CONFIG.ENABLE=0. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 538: I2S_Socket
Indicates sockets used for DMA based operation. Left and right socket must be different for stereo operation. Name Description 15:8 RIGHT_SOCKET[7:0] Socket number for right data samples Supported 8-.. Reserved LEFT_SOCKET[7:0] Socket number for left data samples Supported 8-.. Reserved EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 539: I2S_Id
Name Description 31:16 BLOCK_VERSION[15:0] Version number for the IP 15:0 BLOCK_ID[15:0] A unique number identifying the IP in the memory space EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 540: I2S_Power
For blocks that must perform initialization after reset before becoming operational, this signal will remain deasserted until initialization is complete. In other words reading active=1 indicates block is initialized and ready for operation. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 541: I2C Registers
(After TX_CLEAR is set, software must wait for TX_DONE before clearing it) RX_CLEAR Use only when ENABLE=0; behavior undefined when ENABLE=1 Do nothing Clear receive FIFO (Software must wait for RX_DATA=0 before clearing this bit again) continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 542 Continue transmission even if NAK is received. It is strongly advised to use this bit for debugging purposes only. This bit is overridden in preamble repeat feature. DMA_MODE Register-based transfers DMA-based transfers EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 543: I2C_Status
Indicates the block is busy transmitting data. This field may remain asserted after the block is sus- pended and must be polled before changing any configuration values. continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 544 Indicates data is available in the RX FIFO (only relevant when DMA_MODE=0). This bit is updated immediately after reads from INGRESS_DATA register. Non sticky RX_DONE Indicates receive operation completed. Non sticky, Does not need software intervention to clear it. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 545: I2C_Intr
Set by hardware when corresponding STATUS asserts, cleared by software. RX_DATA Set by hardware when corresponding STATUS asserts, cleared by software. RX_DONE Set by hardware when corresponding STATUS asserts, cleared by software. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 546: I2C_Intr_Mask
TX_HALF Report interrupt to CPU TX_SPACE Report interrupt to CPU TX_DONE Report interrupt to CPU RX_HALF Report interrupt to CPU RX_DATA Report interrupt to CPU RX_DONE Report interrupt to CPU EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 547: I2C_Timeout
Bus timeout interval. 0xFFFF_FFFFF means no timeout, otherwise, count the number of core clock cycles. Name Description 31:0 TIMEOUT[31:0] Number of core clocks SCK can be held low by the slave byte transmission before triggering a time- out error. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 548: I2C_Dma_Timeout
Bus timeout interval for DMA. 0xFFFF means no timeout, otherwise, count the number of core clock cycles of DMA not being ready before raising error. Name Description 15:0 TIMEOUT16[15:0] Number of core clocks DMA has to be not ready before the condition is reported as error condition. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 549: I2C_Preamble_Ctrl
If bit <x> is 1, issue a stop after byte <x> of the preamble (if both START and STOP are set, STOP will take priority). START[7:0] If bit <x> is 1, issue a start after byte <x> of the preamble. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 550: I2C_Preamble_Data
C Preamble Data Register DATA[47:40] I2C_PREAMBLE_DATA C Preamble Data Register DATA[39:32] I2C_PREAMBLE_DATA C Preamble Data Register DATA[31:24] I2C_PREAMBLE_DATA C Preamble Data Register DATA[23:16] I2C_PREAMBLE_DATA C Preamble Data Register DATA[15:8] continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 551 Contains the bytes that precede the data phase of the I2C command. This includes the slave address, R/W command, possi- ble internal address and repeated start command. The number of bytes used is indicated in I2C_COMMAND. Name Description 63:0 DATA[63:0] Command and initial data bytes. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 552: I2C_Preamble_Rpt
The only exception is if timeout is enabled and happens during byte transmission, in which case preamble will stop at the end of the current byte. Data phase is not entered if preamble repeat feature is enabled. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 553: I2C_Command
After command, the hardware will idle if no valid preamble exists, will play preamble if it does exist. Valid preamble is indicated by preamble valid bit. Data phase is not entered if preamble repeat fea- ture is enabled. continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 554 PREAMBLE_LEN[3:0] Number of bytes in preamble. For preamble length = 1, set this to 1 etc. From 1 through 8. 0 and val- ues > 8 are not supported. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 555: I2C_Egress_Data
ERROR if the FIFO is full. The size of the transmit FIFO is configured at design time. Name Description DATA[7:0] Data byte to be written to the peripheral in registered mode. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 556: I2C_Ingress_Data
It will result in ERROR if the FIFO is empty. The size of the receive FIFO is configured at design time. Name Description DATA[7:0] Data byte read from the peripheral when DMA_MODE=0 EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 557: I2C_Clock_Low_Count
This register is for hardware’s internal use for clock synchronization in F/S mode. It appears here in the MMIO space for debug purposes. Name Description 31:0 CLOCK_LOW_COUNT[31:0] Indicates the low period of the last clock pulse on the I C bus, measured using the I C core clock. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 558: I2C_Byte_Count
Number of bytes in the data phase of the transfer. Perform transfers in terms of fixed byte count and perform dummy transactions at the end if required to complete the byte count. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 559: I2C_Bytes_Transferred
5. If timeout happens while transmitting the 1 st bit of the 11th byte, this value will be 11 and so on. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 560: I2C_Socket
C Socket Register EGRESS_SOCKET[7:0] Indicates sockets used for DMA based operation. Name Description 15:8 INGRESS_SOCKET[7:0] Socket number for ingress data Supported 8-.. Reserved EGRESS_SOCKET[7:0] Socket number for egress data Supported 8-.. Reserved EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 561: I2C_Id
Name Description 31:16 BLOCK_VERSION[15:0] Version number for the IP 15:0 BLOCK_ID[15:0] A unique number identifying the IP in the memory space EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 562: I2C_Power
For blocks that must perform initialization after reset before becoming operational, this signal will remain deasserted until initialization is complete. In other words reading active=1 indicates block is initialized and ready for operation. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 563: Uart Registers
(After TX_CLEAR is set, software must wait for TX_DONE before clearing it) RX_CLEAR Do nothing Clear receive FIFO (Software must wait for RX_DATA=0 before clearing this bit again) continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 564 Connect the value being transmitted to the receive buffer. Disable external transmit and receive. TX_ENABLE Transmitter disable, do not transmit data Transmitter enabled RX_ENABLE Receiver disabled, ignore incoming data Receive enabled EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 565: Uart_Status
A protocol error has occurred with cause ERROR_CODE. Must be cleared by software. Sticky BREAK Break condition is detected. Non sticky. CTS_TOGGLE Set when CTS toggles. continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 566 Indicates receive operation completed. Only relevant when DMA_MODE=1). Receive operation is complete when transfer size bytes in socket have been received. Non sticky. Does not need software intervention to clear it. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 567: Uart_Intr
Set by hardware when corresponding STATUS asserts, cleared by software. RX_DATA Set by hardware when corresponding STATUS asserts, cleared by software. RX_DONE Set by hardware when corresponding STATUS asserts, cleared by software. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 568: Uart_Intr_Mask
TX_HALF Report interrupt to CPU TX_SPACE Report interrupt to CPU TX_DONE Report interrupt to CPU RX_HALF Report interrupt to CPU RX_DATA Report interrupt to CPU RX_DONE Report interrupt to CPU EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 569: Uart_Egress_Data
ERROR if the FIFO is full. The size of the transmit FIFO is configured at design time. Name Description DATA[7:0] Data byte to be written to the peripheral in registered mode. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 570: Uart_Ingress_Data
It will result in ERROR if the FIFO is empty. The size of the receive FIFO is configured at design time. Name Description DATA[7:0] Data byte read from the peripheral when DMA_MODE=0 EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 571: Uart_Socket
UART Socket Register EGRESS_SOCKET[7:0] Indicates sockets used for DMA based operation. Name Description 15:8 INGRESS_SOCKET[7:0] Socket number for ingress data Supported 8-.. Reserved EGRESS_SOCKET[7:0] Socket number for egress data Supported 8-.. Reserved EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 572: Uart_Rx_Byte_Count
BYTE_COUNT. BYTE_COUNT will stay 0 in this case (not decrement). Name Description 31:0 BYTE_COUNT[31:0] Number of bytes left to receive 0xFFFFFFFF indicates infinite (counter will not decrement) EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 573: Uart_Tx_Byte_Count
On transmit a command will complete (TX_DONE) when BYTE_COUNT=0. No more bytes will be sent until BYTE_COUNT is modified again. Any EOP signalling from the DMA adapter will be ignored. Name Description 31:0 BYTE_COUNT[31:0] Number of bytes left to transmit 0xFFFFFFFF indicates infinite (counter will not decrement) EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 574: Uart_Id
Name Description 31:16 BLOCK_VERSION[15:0] Version number for the IP 15:0 BLOCK_ID[15:0] A unique number identifying the IP in the memory space EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 575: Uart_Power
For blocks that must perform initialization after reset before becoming operational, this signal will remain deasserted until initialization is complete. In other words reading active=1 indicates block is initialized and ready for operation. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 576: Spi Registers
(After TX_CLEAR is set, software must wait for TX_DONE before clearing it) RX_CLEAR Use only when ENABLE=0; behavior undefined when ENABLE=1 Do nothing Clear receive FIFO (Software must wait for RX_DATA=0 before clearing this bit again) continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 577 Modify only when ENABLE=0. ENDIAN MSB First LSB First DMA_MODE Register-based transfers DMA-based transfers TX_ENABLE Transmitter disable, do not transmit data Transmitter enabled RX_ENABLE Receiver disabled, ignore incoming data Receive enabled EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 578: Spi_Status
This bit is updated immediately after writes to EGRESS_DATA register. Non sticky. TX_SPACE Indicates space is available in the TX FIFO. This bit is updated immediately after writes to EGRESS_- DATA register. Non sticky. continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 579 Indicates receive operation completed. Only relevant when DMA_MODE=1). Receive operation is complete when transfer size bytes in socket have been received. Non sticky. Does not need software intervention to clear it. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 580: Spi_Intr
Set by hardware when corresponding STATUS asserts, cleared by software. RX_DATA Set by hardware when corresponding STATUS asserts, cleared by software. RX_DONE Set by hardware when corresponding STATUS asserts, cleared by software. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 581: Spi_Intr_Mask
TX_HALF Report interrupt to CPU TX_SPACE Report interrupt to CPU TX_DONE Report interrupt to CPU RX_HALF Report interrupt to CPU RX_DATA Report interrupt to CPU RX_DONE Report interrupt to CPU EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 582: Spi_Egress_Data
It will result in ERROR if the FIFO is full. The size of the transmit FIFO is configured at design time. Name Description 31:0 DATA32[31:0] Data word to be written to the peripheral in registered mode. Only the least significant SPI_CONF.WL bits are used. Other bits are ignored. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 583: Spi_Ingress_Data
FIFO has data available. It will result in ERROR if the FIFO is empty. The size of the receive FIFO is configured at design time. Name Description 31:0 DATA32[31:0] Data word read from the peripheral when DMA_MODE=0. Only the least significant SPI_CONF.WL bits are provided. Other bits are set to 0. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 584: Spi_Socket
SPI Socket Register EGRESS_SOCKET[7:0] Indicates sockets used for DMA based operation. Name Description 15:8 INGRESS_SOCKET[7:0] Socket number for ingress data Supported 8-.. Reserved EGRESS_SOCKET[7:0] Socket number for egress data Supported 8-.. Reserved EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 585: Spi_Rx_Byte_Count
BYTE_COUNT. BYTE_COUNT will stay 0 in this case (not decrement). Words can consist of 4-32 bits. Name Description 31:0 WORD_COUNT[31:0] Number of words left to read or write 0xFFFFFFFF indicates infinite (counter will not decrement) EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 586: Spi_Tx_Byte_Count
Any EOP signalling from the DMA adapter will be ignored. Words can consist of 4-32 bits. Name Description 31:0 WORD_COUNT[31:0] Number of words left to read or write 0xFFFFFFFF indicates infinite (counter will not decrement) EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 587: Spi_Id
Name Description 31:16 BLOCK_VERSION[15:0] Version number for the IP 15:0 BLOCK_ID[15:0] A unique number identifying the IP in the memory space EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 588: Spi_Power
For blocks that must perform initialization after reset before becoming operational, this signal will remain deasserted until initialization is complete. In other words reading active=1 indicates block is initialized and ready for operation. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 589: General Purpose Io Block Registers
Registers edge triggered interrupt condition. Only relevant when INTRMODE=1,2,3,6,7. When INTR- MODE=4,5 pin status is fed directly to interrupt controller; condition can be observed through IN_VALUE in this case. continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 590 Output driver is tristated Output driver is active (weak/strong is determined in IO Matrix) IN_VALUE Present input measurement High OUT_VALUE Output value used for output drive (if DRIVE_EN=1) Driven Low Driven High EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 591: Gpio_Invalue0
GPIO_INVALUE0 GPIO Input Value Vector INVALUE0[7:0] One bit for each GPIO pin indicating interrupt status Name Description 31:0 INVALUE0[31:0] If bit <x> is set, IN_VALUE is active for GPIO <x>. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 592: Gpio_Invalue1
GPIO_INVALUE1 GPIO Input Value Vector INVALUE1[7:0] One bit for each GPIO pin indicating interrupt status Name Description 28:0 INVALUE1[28:0] If bit <x> is set, IN_VALUE is active for GPIO <x+32>. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 593: Gpio_Intr0
INTR0[15:8] GPIO_INTR0 GPIO Interrupt Vector INTR0[7:0] One bit for each GPIO pin indicating interrupt status Name Description 31:0 INTR0[31:0] If bit <x> is set, INTR is active for GPIO <x>. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 594: Gpio_Intr1
INTR1[15:8] GPIO_INTR1 GPIO Interrupt Vector INTR1[7:0] One bit for each GPIO pin indicating interrupt status Name Description 28:0 INTR1[28:0] If bit <x> is set, INTR is active for GPIO <x+32>. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 595: Gpio_Intr
Set by hardware when corresponding STATUS asserts, cleared by software. INTR1 Set by hardware when corresponding STATUS asserts, cleared by software. INTR0 Set by hardware when corresponding STATUS asserts, cleared by software. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 596: Gpio_Id
Name Description 31:16 BLOCK_VERSION[15:0] Version number for the IP 15:0 BLOCK_ID[15:0] A unique number identifying the IP in the memory space EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 597: Gpio_Power
For blocks that must perform initialization after reset before becoming operational, this signal will remain deasserted until initialization is complete. In other words reading active=1 indicates block is initialized and ready for operation. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 598: General Purpose Io Registers (One Pin)
Registers edge triggered interrupt condition. Only relevant when INTRMODE=1,2,3,6,7. When INTR- MODE=4,5 pin status is fed directly to interrupt controller; condition can be observed through IN_VALUE in this case. continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 599 Output driver is tristated Output driver is active (weak/strong is determined in IO Matrix) IN_VALUE Present input measurement High OUT_VALUE Output value used for output drive (if DRIVE_EN=1) Driven Low Driven High EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 600: Pin_Timer
Note that each GPIO has its own independent timer/counter Name Description 31:0 TIMER[31:0] 32-bit timer-counter value. Use MODE=SAMPLE_NOW (in PIN_STATUS register) to sample the timer into PIN_THRESHOLD. When TIMER reaches GPIO_PERIOD it resets to 0. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 601: Pin_Period
Note that each GPIO has its own independent timer/counter. Note: In FX3 PIN_PERIOD must be 1 or greater. Name Description 31:0 PERIOD[31:0] 32-bit period for GPIO_TIMER (counter resets to 0 when PERIOD=TIMER) EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 602: Pin_Threshold
A 32-bit threshold or measurement. Usage depends on MODE field in PIN_STATUS register. Note that each GPIO has its own independent timer/counter. Name Description 31:0 THRESHOLD[31:0] 32-bit threshold or measurement for counter. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 603: Low Performance Peripherals Registers
Name Description 31:16 BLOCK_VERSION[15:0] Version number for the IP 15:0 BLOCK_ID[15:0] A unique number identifying the IP in the memory space EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 604: Lpp_Power
For blocks that must perform initialization after reset before becoming operational, this signal will remain deasserted until initialization is complete. In other words reading active=1 indicates block is initialized and ready for operation. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 605: Dma Socket And Descriptor Registers
0xE0038000 + 2 (DMA #2) * 80 + 0x0C = 0xE0038000 + 0x100 + 0x0C = 0xE003810C 10.25.1 SCK_DSCR Descriptor Chain Pointer Register SCK_DSCR Descriptor Chain Pointer 0x00 DSCR_LOW[7:0] SCK_DSCR Descriptor Chain Pointer DSCR_COUNT[7:0] SCK_DSCR Descriptor Chain Pointer DSCR_NUMBER[15:8] SCK_DSCR Descriptor Chain Pointer DSCR_NUMBER[7:0] EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 606 Descriptor number of currently active descriptor. A value of 0xFFFF designates no (more) active descriptors available. When activating a socket CPU will write number of first descriptor in here. Only modify this field when go_suspend=1 or go_enable=0 EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 607: Sck_Size
Valid data bytes remaining in the last buffer beyond the transfer size will be read by socket and passed on to the core. Firmware must ensure that no additional bytes beyond the transfer size are present in the last buffer. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 608: Sck_Count
This count is updated only when a descriptor is completed and the socket proceeds to the next one. Exception: When socket suspends with PARTIAL_BUF=1, this value is (incorrectly) incremented by 1 (UNIT=1) or DSCR_SIZE.BYTE_COUNT (UNIT=0). Firmware must correct this before resuming the socket. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 609: Sck_Status
4. If so, make corrections as necessary (complicated) 5. Clear any pending suspend interrupts (SCK_INTR[9:5]) 6. GO_SUSPEND=0 Note that the socket resumes only when SCK_INTR[9:5]=0 and GO_SUSPEND=0. continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 610 A socket can only be resumed by changing go_suspend from 1 to 0. If the socket is suspended while go_suspend=0, it must first be set and then again cleared. ZLP_RCVD Indicates the socket received a ZLP continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 611 This value is used to create a signal to the IP Cores that indicates at least one buffer is available beyond the current one (sck_more_buf_avl). EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 612: Sck_Intr
When asserting EOP to the adapter on ingress, the trans_count is not updated unless the socket actually suspends (see SUSP_TRANS). Note that the socket resumes only when SCK_INTR[9:5]=0 and GO_SUSPEND=0. continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 613 CONSUME_EVENT Indicates that a consume event is received or transmitted since last cleared. PRODUCE_EVENT Indicates that a produce event is received or transmitted since last cleared. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 614: Sck_Intr_Mask
1: Report interrupt to CPU SUSPEND 1: Report interrupt to CPU STALL 1: Report interrupt to CPU DSCR_NOT_AVL 1: Report interrupt to CPU DSCR_IS_LOW 1: Report interrupt to CPU continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 615 SCK_INTR_MASK 0x14 10.25.6 SCK_INTR_MASK (continued) CONSUME_EVENT 1: Report interrupt to CPU PRODUCE_EVENT 1: Report interrupt to CPU EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 616: Dscr_Buffer
This register is only modified by the adapter when being read from memory. This register is not intended to be modified by software directly. Name Description 31:0 BUFFER_ADDR[31:0] The base address of the buffer where data is written. This address is not necessarily word-aligned to allow for header/trailer/length modification. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 617: Dscr_Sync
The socket number of the producing socket to which the consume event will be sent. If prod_ip and prod_sck matches the socket's IP and socket number then the matching socket becomes consuming socket. continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 618 The socket number of the consuming socket to which the produce event will be sent. If cons_ip and cons_sck matches the socket's IP and socket number then the matching socket becomes consuming socket. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 619: Dscr_Chain
Descriptor number of the next task for producer. A value of 0xFFFF signals end of this list. 15:0 RD_NEXT_DSCR[15:0] Descriptor number of the next task for consumer. A value of 0xFFFF signals end of this list. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 620: Dscr_Size
A producer will interpret this as: Buffer is ready to be filled Buffer is occupied, wait until empty BUFFER_ERROR Indicates the buffer data is valid (0) or in error (1). continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 621 A marker that is provided by software and can be observed by the IP. Its meaning is defined by the IP that uses it. This bit has no effect on the other DMA mechanisms. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 622: Event
Type of event Consume event descriptor is marked empty - BUFFER_OCCUPIED=0) Produce event descriptor is marked full = BUFFER_OCCUPIED=1) 15:0 ACTIVE_DSCR[15:0] The active descriptor number for which the event is sent. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 623: Dma Adapter Global Registers
Socket Interrupt Request Register b239 b238 b237 b236 b235 b234 b233 b232 SCKINTR[239:232] SCK_INTR Socket Interrupt Request Register b231 b230 b229 b228 b227 b226 b225 b224 SCKINTR[231:224] continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 624 Socket Interrupt Request Register b183 b182 b181 b180 b179 b178 b177 b176 SCKINTR[183:176] SCK_INTR Socket Interrupt Request Register b175 b174 b173 b172 b171 b170 b169 b168 SCKINTR[175:168] continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 625 Socket Interrupt Request Register b127 b126 b125 b124 b123 b122 b121 b120 SCKINTR[127:120] SCK_INTR Socket Interrupt Request Register b119 b118 b117 b116 b115 b114 b113 b112 SCKINTR[119:112] continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 626 Socket Interrupt Request Register SCKINTR[95:88] SCK_INTR Socket Interrupt Request Register SCKINTR[87:80] SCK_INTR Socket Interrupt Request Register SCKINTR[79:72] SCK_INTR Socket Interrupt Request Register SCKINTR[71:64] SCK_INTR Socket Interrupt Request Register SCKINTR[63:56] continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 627 Socket Interrupt Request Register SCKINTR[39:32] SCK_INTR Socket Interrupt Request Register SCKINTR[31:24] SCK_INTR Socket Interrupt Request Register SCKINTR[23:16] SCK_INTR Socket Interrupt Request Register SCKINTR[15:8] SCK_INTR Socket Interrupt Request Register SCKINTR[7:0] continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 628 Socket <x> asserts interrupt when bit <x> is set in this vector. Multiple bits may be set to 1 simultaneously. This register is only as wide as the number of sockets in the adapter; 256 is just the maximum width. All other bits always return 0. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 629: Adapter_Status
0..IG_ONLY-1: Sockets capable of both in and egress IG_ONLY..TTL_SOCKETS-1: Ingress sockets only TTL_SOCKETS[7:0] Total number of sockets in this adapter. This number is different for each instance of the adapter and varies with the core IP needs. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 630: Sib_Id
0xE0027F00 BLOCK_VERSION[15:8] BLOCK_VERSION[7:0] BLOCK_ID[15:8] BLOCK_ID[7:0] Name Description 16:31 BLOCK_VERSION Version number for the SIB block IP. Set to 0x0001. 0:15 BLOCK_ID Block ID for the SIB IP. Set to 0x0002. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 631: Sib_Power
Active LOW reset signal for all logic in the block. After setting this bit to 1, firmware will poll and wait for the 'active' bit to assert. ACTIVE Indicates whether the block is powered up and active. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 632: Sdmmc_Cmd_Idx
There are two copies of this register corresponding to the two storage ports. The address of each register is calculated as 0xe0020000 + (port * 0x0400). SDMMC_CMD_IDX SDMMC Command Index 0xE0020000 CMD[5:0] Name Description 6-bit command index. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 633: Sdmmc_Cmd_Arg0
The address of each register is calculated as 0xe0020004 + (port * 0x0400). SDMMC_CMD_ARG0 SDMMC Command Argument 0 0xE0020004 ARG[31:24] ARG[23:16] ARG[15:8] ARG[7:0] Name Description 31:0 Lower 32 bits of the command argument. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 634: Sdmmc_Cmd_Arg1
32 bits. There are two copies of this register corresponding to the two storage ports. The address of each register is calculated as 0xe0020008 + (port * 0x0400). SDMMC_CMD_ARG1 SDMMC Command Argument 1 0xE0020008 ARG[63:56] ARG[55:48] ARG[47:40] ARG[39:32] Name Description 31:0 Upper 32 bits of the command argument. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 635: Sdmmc_Resp_Idx
0xe002000C + (port * 0x0400). SDMMC_RESP_IDX SDMMC Response Index 0xE002000C ST_BIT TR_BIT CMD[5:0] Name Description ST_BIT Start-bit: As received in response. TR_BIT Transmission bit: As received in response. Command index. As received in response EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 636: Sdmmc_Resp_Reg0
0xe0020010 + (port * 0x0400). SDMMC_RESP_REG0 SDMMC Command Response 0 0xE0020010 RESP[31:24] RESP[23:16] RESP[15:8] RESP[7:0] Name Description 31:0 RESP Bits 8 to 39 of the command response from MSB to LSB. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 637: Sdmmc_Resp_Reg1
0xe0020014 + (port * 0x0400). SDMMC_RESP_REG1 SDMMC Command Response 1 0xE0020014 RESP[31:24] RESP[23:16] RESP[15:8] RESP[7:0] Name Description 31:0 RESP Bits 40 to 71 of the command response from MSB to LSB. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 638: Sdmmc_Resp_Reg2
0xe0020018 + (port * 0x0400). SDMMC_RESP_REG2 SDMMC Command Response 2 0xE0020018 RESP[31:24] RESP[23:16] RESP[15:8] RESP[7:0] Name Description 31:0 RESP Bits 72 to 103 of the command response from MSB to LSB. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 639: Sdmmc_Resp_Reg3
0xe002001C + (port * 0x0400). SDMMC_RESP_REG3 SDMMC Command Response 3 0xE002001C RESP[31:24] RESP[23:16] RESP[15:8] RESP[7:0] Name Description 31:0 RESP Bits 104 to 135 of the command response from MSB to LSB. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 640: Sdmmc_Resp_Reg4
0xe0020020 + (port * 0x0400). SDMMC_RESP_REG4 SDMMC Command Response 4 0xE0020020 RESP[31:24] RESP[23:16] RESP[15:8] RESP[7:0] Name Description 31:0 RESP Bits 136 to 167 of the command response from MSB to LSB. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 641: Sdmmc_Cmd_Resp_Fmt
Non-zero values indicate the size in bits CMDFRMT Command length minus 1, in bits, that includes command index bits and argument bits. This length does not include start, transmit, CRC7 and end bits. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 642: Sdmmc_Block_Count
There are two copies of this register corresponding to the two storage ports. The address of each register is calculated as 0xe0020028 + (port * 0x0400). SDMMC_BLOCK_COUNT SDMMC Block Count 0xE0020028 NOBD[31:24] NOBD[23:16] NOBD[15:8] NOBD[7:0] Name Description 31:0 NOBD Number of data blocks to be transferred. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 643: Sdmmc_Block_Len
SDMMC Block Length 0xE002002C DATABLKS[31:24] DATABLKS[23:16] DATABLKS[15:8] DATABLKS[7:0] Name Description 31:0 DATABLKS Data block size in bytes. LSB is ignored for DDR mode of operation, because block length needs to be even. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 644: Sdmmc_Mode_Cfg
1: SDMMC interface clock can be stopped only at the end of data block transfer. Clock is not stopped in the middle of a block data transfer. It is recommended that this bit should be set to 1. continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 645 Setting this bit causes the SIB internal clock to be driven out on the pad bypassing the DLL. It is rec- ommended that this bit should always be set to 1. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 646: Sdmmc_Data_Cfg
1: Enable the SIB state machine to wait for busy before sending first block of data. 0: SIB state machine pushes 1st block of data without checking busy status. RD_CRC_EN 1: Check CRC16 on incoming blocks of data. 0: Ignore CRC16 checking on incoming data. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 647: Sdmmc_Cs
FW writes ‘1’ to clear the RDDCARD bit so that the next command can be issued. This bit is cleared by HW when RDDCARD is cleared. continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 648 FW writes ‘1’ to initiate sending of command. HW writes ‘0’ when command is sent and the response, if any, is received. FW may clear this bit on response timeout by writing 1 to CLR_SNDCMD bit. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 649: Sdmmc_Status
COMMAND_SM_BUSY 1: Command state machine is busy. 0: Command state machine is idle. 26:24 CRCFC 3-bit CRC response received from the card following a data write. continued in next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 650 This bit is cleared when the FW writes ‘1’ to SDMMC_CS.SNDCMD again. CMDSENT HW sets this bit to ‘1’ when a command is sent. This bit is cleared when the FW writes ‘1’ to SDMMC_CS.SNDCMD again. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 651: Sdmmc_Intr
FW writes 1 to clear the interrupt. BOOT_ACK HW writes 1 to indicate that a BOOT acknowledgement is received. FW writes 1 to clear the interrupt. continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 652 HW writes 1 to indicate that a command response is received. FW writes 1 to clear the interrupt. CMDSENT HW writes 1 to indicate that a command is sent to the target device. FW writes 1 to clear the interrupt. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 653: Sdmmc_Intr_Mask
1: Enable interrupt due to DLL lock loss. 0: Disable interrupt due to DLL lock loss. BOOT_ACK 1: Enable interrupt due to BOOT acknowledgement. 0: Disable interrupt due to BOOT acknowledgement. continued on next page EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 654 RCVDRES 1: Enable interrupt due to response reception. 0: Disable interrupt due to response reception. CMDSENT 1: Enable interrupt due to command transmission. 0: Disable interrupt due to command transmission. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 655: Sdmmc_Ncr
NCR_MAX Specifies the timeout period for which the SIB will wait to receive a response, in terms of number of cycles from end bit of command. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 656: Sdmmc_Ncc_Nwr
NWR_MIN Specifies the minimum number of clock cycles between end bit of response and start bit of write data. NCC_MIN Specifies the minimum number of clock cycles between consecutive commands. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 657: Sdmmc_Nac
The address of each register is calculated as 0xe0020050 + (port * 0x0400). SDMMC_NAC SDMMC Read Timeout Register 0xE0020050 RDTMOUT[29:22] RDTMOUT[21:14] RDTMOUT[13:6] RDTMOUT[5:0] Name Description 31:2 RDTMOUT Specifies the timeout duration in clock cycles to be applied to data read operations. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 658: Sdmmc_Hw_Ctrl
FW writes ‘1’ to assert the eMMC4.4 card HW reset using the SxMMCRST pin. FW writes ‘0’ to de-assert reset after tRSTW (1 usec) and waits for tRSCA (200 usec) before issuing commands. EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 659 0: Use when clock frequency is less than 70 MHz. 1: Use when clock frequency is greater than 70 MHz. ENABLE 1: Enable the SIB DLL 0: Disable the SIB DLL EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...
Page 660 Added hyperlinks to application notes Updated Figure 6-1 6569868 05/09/2019 SHEA Removed reference to EZ-Detect and Charger Detect Removed reference to the Battery Charging Specification Deleted the CRC Configuration Register EZ-USB FX3 Technical Reference Manual, Document Number: 001-76074 Rev. *F...

Cypress EZ-USB FX3 Technical Reference Manual

1 Introduction to EZ-USB FX3

2 FX3 CPU Subsystem

3 Memory and System Interconnect

4 Global Controller (GCTL)

5 FX3 DMA Subsystem

6 Universal Serial Bus (USB)

7 General Programmable Interface II (GPIF II)

8 Low Performance Peripherals (LPP)

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