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NXR-901
IC2 (PLL IC) compares the phase difference of the VCO
signal and the 20.0MHz reference signal from the TX unit.
The phase error signal from IC2 is fi ltered by the Q2 and Q3
active low pass fi lter.
The VCO frequency tuning voltage is adjusted by the
IC805 pin 3 DAC signal, the IC3 DC amplifi er and the low
pass fi lter. The LPF is confi gured with R32, C46 and D5. The
VCO frequency tuning voltage is monitored by the IC1 DC
buffer and IC811 pin 16 ADC.
The 2nd-PLL circuit consists of the VCO (Q604), the Buf-
fer amplifi er (Q609), the RF amplifi er (Q602), the RF doubler
(Q608) and the PLL-IC (IC603).
IC603
PLL IC
16
CIRCUIT DESCRIPTION
CV1
IC1
IC3
Active
LPF
Q2,Q3
Q5
Q9
IC2
823~829MHz
PLL IC
20.0MHz
CV2
ADC
IC601
IC811
LPF
Q604
Q609
Frequency
doubler
145.2MHz
x2
Q608
20.0MHz
Q602
Fig. 18 Receiver PLL circuits
The 72.6MHz 2nd local oscillator signal generated by
Q604 is doubled to 145.20MHz by Q608 and is passed to
the LC band-pass fi lter to attenuate the spurious signals. The
145.2MHz signal is fed to IC603 (pin 5) as the Fin signal.
The 20.0MHz reference clock distributed by the Transmitter
unit (X56-315) is input as the REFin signal to IC603 (pin 8)
via Q602.
Two signals, Fin and REFin, are phase-compared by
each frequency divider as the comparison frequency of
200kHz. Therefore the VCO output frequency is half of the
PLL's Fin frequency.
The 2nd VCO control voltage (CV2) is input to IC811
(ADC) pin 10 via IC601.
ADC
Frequency
IC811
doubler
823~829MHz
DAC
x2
IC805
Q11
Q10
3dB
411.5~414.5MHz
divider
Frequency
doubler
x2
Q8
Ref signal
20MHz
Q1
72.6MHz
3dB
divider
Q603
Ref signal
20MHz
1st mixer
ATT
IC207
3dB
divider
IC501
Q501
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