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4-4. Demodulator circuits
The desired signal that passed through the 1st IF circuit
passes through a 3dB divider consisting of LC parts and is
fed to the IF system IC, IC207, and IC501.
Analog_Narrow FM signal is mixed with the second local
oscillator signal by the mixer in IC207. The 450kHz signal is
produced as the 2nd Intermediate Frequency (IF2).
The analog narrow FM signal is fi ltered by the ceramic
filters of CF201 and CF203. The baseband signal is FM-
detected by the quadrature detection circuit consisting of
L286, and is an amplifi ed Narrow FM signal to be fi ltered by
ceramic fi lters CF201 and CF203 for narrow FM.
1st IF signal
4-5. Squelch circuit
The desired noise of the noise component output from
the IF system IC_IC207 (pin 9) is extracted by the BPF
IC207 (pin 7, 8).
After passing through Q214, it is DC-detected as the
squelch voltage by D214, D215 and input to ADC_IC811 (pin
11).
The MPU mounted in the Control unit (X53-413) com-
pares it with a predetermined reference voltage and turns
the Audio signal on and off. The strength of the receiver sig-
nal input from CN5 is output as the RSSI voltage from the IF
system IC_IC207 (pin 12), and is input to_IC811 (ADC) pin
12 via IC812 A/2.
CIRCUIT DESCRIPTION
CF201
IC208
CF203
Narrow FM
IC207
Quadrature
Q214
3dB
divider
2nd Lo
IC218 A/2
72.60MHz
IC501
CF501
Fig. 17 Demodulator circuits
Narrow FM signal to be fi ltered by ceramic fi lters CF201,
CF203 for narrow FM. The baseband signal FM-detected by
the quadrature detection circuit is amplifi ed to a signal level
of approximately 100mVrms by IC210 and is then transmit-
ted to the Control unit (X53-413) from CN42 (pin 12).
Digital_Narrow or Digital_Very-Narrow signal is mixed
with the second local oscillator signal by the mixer in IC501.
450kHz signal is produced as the 2nd Intermediate Frequen-
cy (IF2). Here, irrespective of modulation modes, it passes
through the CF501 and CF502 path. It is transmitted as the
baseband signal via IC502 to the CN43 Control unit, X53-
414.
IC210
CN42 #12
DET
D214,D215
CN43 #24 AD_CLK
IC811
CN43 #28 AD_CS
CN43 #22 AD_DAT_READ
CF502
IC502
CN43
4-6. Receiver PLL circuits
The Receiver unit (X55-312) has the 1st-PLL circuit for
controlling the VCO that generates the signal to the fi rst lo-
cal oscillator, and the 2nd-PLL circuit for controlling the VCO
that generates the signal to the second local oscillator.
The 1st-PLL circuit consists of the VCO (Q5), the Buffer
amplifi er (Q9), the RF amplifi ers (Q8), the PLL-IC (IC2), the
Active loop fi lters (Q2 and Q3) and the CV adjustment buf-
fer/LPF (IC3 and D5).
The receiver's 1st mixer requires a 823~829MHz lo-
cal oscillator signal. The 1st-PLL's VCO oscillates at half of
it, 411.5~414.5MHz. Frequency doubler Q8 doubles to a
823~829MHz signal and passes it to IC2 pin 2 through the
band-pass fi lter to attenuate the spurious signals. The PLL is
locked to the 823~829MHz frequency range. As described in
section 4.2, the VCO signal is doubled for the 1st mixer.
NXR-901
15
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