Timer 3 Irq Clear (T3Ic, 0X632); Timer 4 Irq Clear (T4Ic, 0X633); Cpld Gpio Lpc Interface Access Port And General; Configuration Registers - GE OpenVPX VPXcel6 SBC622 Hardware Reference Manual

3.2.28 Timer 3 IRQ Clear (T3IC, 0x632)

The Timer 3 IRQ Clear (T3IC) register is used to clear an interrupt caused by
Timer 3. Writing to this register, located at offset 0x32 from base I/O address
0x600, causes the interrupt from Timer 3 to be cleared. This can also be done by
writing a ʺ0ʹ to TCSR3[7]. The T3IC register is write only and the data written is
irrelevant.

3.2.29 Timer 4 IRQ Clear (T4IC, 0x633)

The Timer 4 IRQ Clear (T4IC) register is used to clear an interrupt caused by
Timer 4. Writing to this register, located at offset 0x33 from base I/O address
0x600, causes the interrupt from Timer 4 to be cleared. This can also be done by
writing a ʺ0ʺ to TCSR4[7]. The T4IC register is write only and the data written is
irrelevant.

3.2.30 CPLD GPIO LPC Interface Access Port and General

Configuration Registers

The SBC622 provides eight lines of General Purpose I/O through the P4/P6
connector. The lines are able to tolerate 5V input voltages and the signals are
isolated whenever the SBC622 is powered down.

Figure 3-2 CPLD GPIO Interface Access

Max 5 V
4K7
Onboard
Logic
Isolator VPX
(CPLD)
Connector
PWROK
The GPIO signals are sourced from the CPLD and any reset clears all output pins
to inputs. To prevent GPIO output pins glitching during board reset, the GPIO
Out Register (offset 0x640) is only reset on power‐up. Always write this register
before enabling GPIO output pins.
Under software control, each GPIO signal can be used to generate an interrupt to
the CPU on either level, either edge or both edges (see the GPIO Registers). All
GPIO interrupts are connected to the PCH via the SERIRQ (Serial Interrupt
Request) signal and appear to the Interrupt Handler as IRQ5. When using level
interrupts, the PCH interrupt (IRQ5) also needs to be set to level sensitive.
The GPIO interrupt using the SERIRQ signal means that the maximum update of
the GPIO interrupt to the Interrupt Handler is around 2.25 μS. If the time that the
ISR takes to write to the GPIO Interrupt Status Register (0x640) to clear the
interrupt and return from the interrupt routine is very short (<2.25 μS), then it is
possible to receive spurious GPIO interrupts.
CPLD Control and Status Registers 59