Harman Kardon AVR 151/230C Service Manual page 73

Harman Kardon
ADI Confidential
Pin No. Mnemonic
56 TX2−
57 TX2+
58 TXGND
59 CEC
60 DGND
61 DVDD
62 ALSB
63 CS
64 EP_SCK
65 EP_CS
66 EP_MOSI
67 EP_MISO
68 MCLK_IN
69 SCLK_IN
70 AP5_IN
71 AP4_IN
72 DGNDIO
73 DVDDIO
74 AP3_IN
75 AP2_IN
76 AP1_IN
77 AP0_IN
78 SDATA
79 SCL
80 DGND
81 DVDD
82 INT1
(AMUTE1)
83 INT2
(AMUTE2) TE2)
84 INT_TX T_TX X
85 DGNDIO NDIO DIO
86 DVDDIO
87 AP0_OUT
88 AP1_OUT
89 AP2_OUT
90 AP3_OUT
91 AP4_OUT
92 DGND
93 DVDD
94 AP5_OUT
95 SCLK_OUT
96 MCLK_OUT
97 RESET
98 PWRDN
Type Description
HDMI output Differential Output Channel 2 Complement. Differential output of the red data at 10×
the pixel clock rate; supports TMDS logic level.
HDMI output Differential Output Channel 2 True. Differential output of the red data at 10× the pixel
clock rate; supports TMDS logic level.
Ground TXAVDD Ground.
Digital I/O Consumer Electronics Control Channel (5 V Tolerant).
Ground DVDD Ground.
Power Digital Supply Voltage (1.8 V).
Digital input This pin is used to set the I
Digital input Chip Select Pin. This pin must be set low or left floating for the chip to process I
that are destined for the ADV7623. The ADV7623 ignores I
this pin is high.
Digital output SPI Clock Interface for the EDID/OSD.
Digital output SPI Chip Selected Interface for the EDID/OSD.
Digital output SPI Master Out/Slave In for the EDID/OSD.
Digital input SPI Master In/Slave Out for the EDID/OSD.
Digital input
Audio Reference Clock. 128 × N × f
256 × f , 384 × f
S
2
Digital input I S Aud S Audio Clock. It supports CMOS logic levels from 1.8 V to 3.3 V. ud
Digital input Audio Input Audio Input Port 5. It supports CMOS logic levels from 1.8 V to 3.3 V. o Input
Digital input Audio Input Po Audio Input Port 4. It supports CMOS logic levels from 1.8 V to 3.3 V. o Input Po
Ground DVDDIO Grou DVDDIO Ground. DVDDIO G
Power Digital I/O Supply Voltage (3.3 V). Digital I/O S Digital I/O
Digital input t t Audio Input Port 3. It supports CMOS logic levels from 1.8 V to 3.3 V. Audio Inp Audio Inp
Digital input put ut Audio I Audio Input Port 2. It supports CMOS logic levels from 1.8 V to 3.3 V. Audio
Digital input nput nput Audi Audio Audio Input Port 1. It supports CMOS logic levels from 1.8 V to 3.3 V.
Digital input l input l input Aud Aud Audio Input Port 0. It supports CMOS logic levels from 1.8 V to 3.3 V.
2 2 2
Digital I/O tal I/O tal I/O I I I C Port Serial Data Input/Output Pin. SDATA is the data line for the control port. C
2
Digital input gital input tal input I C Port Serial Clock Input. SCL is the clock line for the control port.
Ground Ground DVDD Ground. round. ound.
Power Power Digital Supply Voltage (1.8 V). Supply Voltage
Digital o Digital output Digital output Interrupt Pin. This pin can be active low or active high. When status bits change, this pin is rupt Pin. This pi pt Pin. This
triggered. The events that trigger an interrupt are under user control. This pin can also output ggered. The even ed. The e
an audio mute signal. n audio mute sig udio mute
Digital ou Digital o Digital output Interrupt Pin. T Interrupt Pin. This pin can be active low or active high. When status bits change, this pin is errupt P
triggered. The triggered. The events that trigger an interrupt are under user control. This pin can also output riggered. T
an audio an audio mu an audio mute signal.
Digi Digi Digital output Interrupt; Open Drain. A 2 kΩ pull-up resistor to the microcontroller I/O supply is recommended. Interrup Interrupt; O
Ground Gr Gr DVDDIO DVD DVDDIO Ground.
Power P Digita Di Digital I/O Supply Voltage (3.3 V).
Digital output t t Audio Output Port 0. Aud A
Digital output Audio Output Port 1. Au
Digital output Audio Output Port 2. utput Port 2. utput P
Digital output Audio Output Port 3. Output Port 3. utput Port 3
Digital output Audio Output Port 4. o Output Port 4. Output Port 4.
Ground DVDD Ground. Ground. Ground.
Power Digital Supply Voltage (1.8 V).
Digital output Audio Output Port 5.
Digital output Audio Serial Clock Output.
Digital output Audio Master Clock Output.
Digital input System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required to reset
the ADV7623 circuitry.
Digital input Active Low Power-Down Pin. If used, this pin should be pulled high to power up the
ADV7623. This pin can also be used as an in system power detect where internal EDID can
be powered from a 5 V signal of the HDMI port when it is connected to active equipment.
2 C address of the Rx IO and the Tx main map.
with N = 1, 2, 3, or 4. Set to 128 × sampling frequency (f
S
, or 512 × f . It supports CMOS logic levels from 1.8 V to 3.3 V.
S S
tage (3.3 age
t supports CM t supports CM
2. It supports CM t supports
t 1. It supports C 1. It suppor
ort 0. It support 0. It supp ogic levels fro ogic levels fro
al Data Input/Ou n. SDAT . SDATA is the data
rial Clock Input. Clo he clock line for th clock line for th
pply Volt
active low or acti ve low or acti
trigger an interrup r an interru
an be active low o e active low
that trigger an inte rigger an in
al.
ain. A 2 kΩ pull ain. A 2 kΩ pull-up r up
.
ply Voltage (3.3 V) y Voltage (3.3 V)
ut Port 0. 0.
put Port 1.
y Vo y Volta
Rev. Sp0 | Page 11 of 16
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AVR 151 Service Manual
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