Analog Devices LTC2941 Datasheet page 11

APPLICATIONS INFORMATION
To use as much of the range of the accumulated charge
registers C and D as possible the prescaler factor M
should be chosen for a given battery capacity Q
sense resistor R as:
SENSE
Q
BAT
M ≥ 128 •
16
2 • 0.085mAh
M can be set to 1, 2, 4, 8, ...128 by programming
B[5:3] of the control register as M = 2
+ B[3])
. The default value after power up is M = 128 = 2
(B[5:3] = 111).
In the above example of a 100mAh battery and a R
of 50mΩ, the prescaler should be programmed to M = 4.
The q then becomes 2.656µAh and the battery capacity
LSB
corresponds to roughly 37650 q
Note that the internal digital resolution of the coulomb
counter is higher than indicated by q
charge q is M • 8 smaller than q
INTERNAL
typically 299µAs for a 50mΩ sense resistor.
V Alert B[7:6]
BAT
The V alert function allows the LTC2941 to monitor
BAT
–
the voltage at SENSE . If enabled, a drop of the voltage
–
at the SENSE pin below a preset threshold is detected
and bit A[1] in the status register is set. If the alert mode
is enabled by setting B[2] to one, an alert is generated at
the AL/CC pin. The threshold for the V
is selectable according to Table 3.
Accumulated Charge Registers (C, D)
The coulomb counter of the LTC2941 integrates current
through the sense resistor. The 16-bit result of this charge
integration is stored in the accumulated charge registers C
and D. As the LTC2941 does not know the actual battery
status after initial power-up, the accumulated charge is
set to mid-scale (7FFFh). If the host knows the status of
the battery, the accumulated charge registers C[7:0] and
and a
BAT
R
SENSE
•
50mΩ
(4 • B[5] + 2 • B[4]
SENSE
s.
LSB
. The digitized
LSB
. q is
LSB INTERNAL
alert function
BAT
For more information
D[7:0] can be either programmed to the correct value
2
via I C or it can be set after charging to FFFFh (full) by
pulling the AL/CC pin high (if charge complete mode is
enabled via bits B[2:1]). Before writing the accumulated
charge registers, the analog section should be shut down
by setting B[0] to 1. In order to avoid a change in the
accumulated charge registers between reading MSBs
C[7:0] and LSBs D[7:0], it is recommended to read them
sequentially, as shown in Figure 8.
7
Threshold Registers (E, F), (G, H)
For battery charge, the LTC2941 features a high and a
low threshold register. At power-up the high threshold
is set to FFFFh while the low threshold is set to 0000h.
Both thresholds can be programmed to a desired value via
2
I C. As soon as the accumulated charge exceeds the high
threshold or falls below the low threshold, the LTC2941
sets the corresponding flag in the status register and pulls
the AL/CC pin low if alert mode is enabled.
2
I C Protocol
The LTC2941 uses an I
drain interface supporting multiple devices and masters
on a single bus. The connected devices can only pull the
bus wires LOW and they never drive the bus HIGH. The
bus wires should be externally connected to a positive
supply voltage via a current source or pull-up resistor.
When the bus is idle, both SDA and SCL are HIGH. Data on
2
the I C-bus can be transferred at rates of up to 100kbit/s
in standard mode and up to 400kbit/s in fast mode.
Each device on the I
address stored in that device and can operate as either a
transmitter or receiver, depending on the function of the
device. In addition to transmitters and receivers, devices
can also be classified as masters or slaves when perform-
ing data transfers. A master is the device which initiates
a data transfer on the bus and generates the clock sig-
nals to permit that transfer. At the same time any device
addressed is considered a slave. The LTC2941 always
acts as a slave. Figure 4 shows an overview of the data
transmission on the I
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LTC2941
2
C/SMBus compatible 2-wire open-
2
C/SMBus is recognized by a unique
2
C bus.
Rev. C
11