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5
QQ
3 7 63 1515 0
Pin Function
No.
Pin Name
1
VCC
2
DE
3
VREF
4
HSYNC
5
VSYNC
6
CTL3
7
NC
8
NC
9
HTPLG
10
PD#
11
MSEN
12
VCC
13
ISEL/RST#
14
SDAS
15
SCLS
16
GND
17
PGND1
18
PVCC1
19
EXT_SWING
20
AGND
21
TXC-
TE
L 13942296513
22
TXC+
23
AVCC
24
TX0-
25
TX0+
26
AGND
27
TX1-
28
TX1+
29
AVCC
30
TX2-
31
TX2+
32
AGND
33
VCC
34
RESERVED
35
GND
36
D23
37
D22
38
D21
39
D20
40
D19
41
D18
www
42
D17
43
D16
44
D15
.
45
D14
5
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6
I/O
−
Digital power supply (3.3V)
I
Data enable
I
3.3V fixed
I
Horizontal sync. control signal input
I
Vertical sync. control signal input
I
External CTL3 input
−
No connection
−
No connection
I
Monitor chrage input
I
Power down input (Active low)
O
Monitor sense output (open-collector output)
−
Digital power supply (3.3V)
I
I2C interface selecting input
I/O
DDC I2C data input/output
I
DDC I2C clock input
−
Digital ground
−
PLL analog ground
−
Analog power supply for PLL of primary side (3.3V)
I
Voltage regulation adjustment
−
Analog ground
O
Differential signal clock output of TMDS Low voltage
O
Differential signal clock output of TMDS Low voltage
−
Analog power supply (3.3V)
O
Differential signal clock output of TMDS Low voltage
O
Differential signal clock output of TMDS Low voltage
−
Analog ground
O
Differential signal clock output of TMDS Low voltage
O
Differential signal clock output of TMDS Low voltage
−
Analog power supply (3.3V)
O
Differential signal clock output of TMDS Low voltage
O
Differential signal clock output of TMDS Low voltage
−
Analog ground
−
Digital power supply (3.3V)
I
Reserved pin for Silicon Image Normally, fixed to low.
−
Digital ground
I
24-bit pixel bus input
I
24-bit pixel bus input
I
24-bit pixel bus input
I
24-bit pixel bus input
I
24-bit pixel bus input
I
24-bit pixel bus input
I
24-bit pixel bus input
I
24-bit pixel bus input
x
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y
I
24-bit pixel bus input
i
I
24-bit pixel bus input
6
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7
2 9
8
Pin Function
High: I2C interface is active
Q Q
3
6 7
1 3
1 5
co
.
PDP-R05U
7
8
9 4
2 8
0 5
8
2 9
9 4
2 8
m
9 9
A
B
C
9 9
D
E
F
209
8
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