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Dialog Semiconductor DA1468 Series Application Note

Application hardware design guidelines
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Company confidential
Application note
DA1468x Application hardware
design guidelines
AN-B-061

Abstract

Minimal reference schematic, circuit explanation and design guidelines for BLE applications based
on the DA14680-01, DA14681-01, DA14682-00 and the DA14683-00 SoCs.

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Summary of Contents for Dialog Semiconductor DA1468 Series

  • Page 1: Abstract

    Company confidential Application note DA1468x Application hardware design guidelines AN-B-061 Abstract Minimal reference schematic, circuit explanation and design guidelines for BLE applications based on the DA14680-01, DA14681-01, DA14682-00 and the DA14683-00 SoCs.

  • Page 2: Table Of Contents

    Appendix: AQFN60 assembly and soldering guidelines ............... 40 PCB ............................. 40 Stencil Design ........................41 Component Placement......................42 Reflow Profile ........................43 Revision history ..........................44 Application note Revision 1.9 28-Mar-2019 CFR0014 Rev 3 2 of 45 © 2019 Dialog Semiconductor...

  • Page 3: Figures

    Table 9: 32 MHz crystal examples and characteristics ............... 22 Table 10: 32.768 KHz crystal examples and characteristics ............... 23 Table 11: Default UART pins ....................... 25 Table 12: JTAG pins ..........................25 Application note Revision 1.9 28-Mar-2019 CFR0014 Rev 3 3 of 45 © 2019 Dialog Semiconductor...

  • Page 4: Terms And Definitions

    Wafer Level Chip Scale Package References DA14680-01, DA14681-01, DA14682-00, DA14683-00 Datasheet, Dialog Semiconductor. DA1468x Pro-Development Kit, Dialog Semiconductor. AN-B-056 - DA14680_681 Recovery from System Level ESD Events, Dialog Semiconductor. AN-B-45 - DA1468x Booting from serial interfaces, Dialog Semiconductor. Application note Revision 1.9...

  • Page 5: Introduction

    DA1468x. Based on this, system designers can build a BLE application on the top of it. Recommended schematic, chip interfaces and surrounding components as well as PCB layout guidelines of the DA1468x SoC family are provided. Application note Revision 1.9 28-Mar-2019 CFR0014 Rev 3 5 of 45 © 2019 Dialog Semiconductor...

  • Page 6: Device Revision Numbering And Marking

    Version format: xx = commercial chip revision: ‘00’ or ‘01’. Date code format: yy = Year, ww = Week, nnnn = Dialog internal number Application note Revision 1.9 28-Mar-2019 CFR0014 Rev 3 6 of 45 © 2019 Dialog Semiconductor...

  • Page 7: Minimal Design For The Da1468X Soc

    JTAG DA1468x GPIOs matching QSPI Flash* 16/32 MHz 32.768 KHz (optional) * Not needed for DA14680/682 Figure 1: Block diagram of the DA1468x minimal design Application note Revision 1.9 28-Mar-2019 CFR0014 Rev 3 7 of 45 © 2019 Dialog Semiconductor...

  • Page 8: Figure 2: Minimal Design For Da14681-01 Wlcsp53 Package

    AN-B-061 DA1468x Application hardware design guidelines Company confidential Figure 2: Minimal design for DA14681-01 WLCSP53 package Application note Revision 1.9 28-Mar-2019 CFR0014 Rev 3 8 of 45 © 2019 Dialog Semiconductor...

  • Page 9: Figure 3: Minimal Design For Da14681-01 Aqfn60 Package

    Company confidential Figure 3: Minimal design for DA14681-01 AQFN60 package Note: for the DA14680-01 (embedded flash), U2, R3, C12 are not present. And P0_0~P0_5 are N.C. Application note Revision 1.9 28-Mar-2019 CFR0014 Rev 3 9 of 45 © 2019 Dialog Semiconductor...

  • Page 10: Figure 4: Minimal Design For Da14683-00 Wlcsp53 Package

    AN-B-061 DA1468x Application hardware design guidelines Company confidential Figure 4: Minimal design for DA14683-00 WLCSP53 package Application note Revision 1.9 28-Mar-2019 CFR0014 Rev 3 10 of 45 © 2019 Dialog Semiconductor...

  • Page 11: Figure 5: Minimal Design For Da14683-00 Aqfn60 Package

    Company confidential Figure 5: Minimal design for DA14683-00 AQFN60 package Note: for the DA14682-01 (embedded flash), U2, R3, C12 are not present. And P0_0~P0_5 are N.C. Application note Revision 1.9 28-Mar-2019 CFR0014 Rev 3 11 of 45 © 2019 Dialog Semiconductor...

  • Page 12: Power Section Of Da1468X

    The V18P (VDD1V8P) rail is assigned to be used for supplying external devices like sensors or a RF power amplifier. The V18P supply rail is also used to supply the GPIOs when these are set to use the Application note Revision 1.9 28-Mar-2019 CFR0014 Rev 3 12 of 45 © 2019 Dialog Semiconductor...

  • Page 13: Table 5: Suggested Decoupling Capacitors For The Power Section

    2.0 x 1.2 x 1.0 2.0 x 1.25 x 1.0 2.0 x 1.2 x 0.6 1.6 x 0.8 x 0.8 L x W x H Application note Revision 1.9 28-Mar-2019 CFR0014 Rev 3 13 of 45 © 2019 Dialog Semiconductor...

  • Page 14: Supplying External Loads

    The GPIOs supply-rail can be configured to 1.8V or 3.3V. When set to 1.8V, the GPIO is supplied from V18P, VDD1V8P. Whereas for 3.3V it is supplied from the 3.3V LDO, V33. Refer to Figure Application note Revision 1.9 28-Mar-2019 CFR0014 Rev 3 14 of 45 © 2019 Dialog Semiconductor...

  • Page 15: Figure 8: Da1468X Power Management Unit Block Diagram

    V18 / V18P active 75 mA 75 mA V18 / V18P sleep 3 mA 10 mA V33 active 100 mA 100 mA V33 sleep 3 mA 10 mA Application note Revision 1.9 28-Mar-2019 CFR0014 Rev 3 15 of 45 © 2019 Dialog Semiconductor...

  • Page 16: Supply Rails Discharging

    ‘Rails Discharging’ section of the ‘Reset and BOD’ chapter in the DA14682 and the DA14683 datasheet. Figure 9: V14, V18, V18P rails discharging by HW Reset Figure 10: Discharging rails FSM timing Application note Revision 1.9 28-Mar-2019 CFR0014 Rev 3 16 of 45 © 2019 Dialog Semiconductor...

  • Page 17: Simo Buck Dc/Dc Characteristics

    The converter tries to charge each output every 2 µsec, and since there are four outputs there’s one pulse every 0.5 µsec, leading to a typical switching frequency of 2 MHz. Figure 11: SIMO BUCK DC/DC Block Diagram Application note Revision 1.9 28-Mar-2019 CFR0014 Rev 3 17 of 45 © 2019 Dialog Semiconductor...
  • Page 18 In general the buck DC/DC inductor value (470 nH) is pretty optimal for the DA1468x design, and increasing the output capacitor values will reduce the voltage ripple and the magnitude of the load transients. Application note Revision 1.9 28-Mar-2019 CFR0014 Rev 3 18 of 45 © 2019 Dialog Semiconductor...

  • Page 19: I/O Pins

    It is recommended to toggle these pins at a low rate only and not at all while the radio is active or the PLL96M is used. Application note Revision 1.9 28-Mar-2019 CFR0014 Rev 3 19 of 45 © 2019 Dialog Semiconductor...

  • Page 20: Crystals And Clocks

    The crystal or the external clock must meet the 16 MHz or 32 MHz crystal oscillator recommended operating conditions as listed below in below tables. Application note Revision 1.9 28-Mar-2019 CFR0014 Rev 3 20 of 45 © 2019 Dialog Semiconductor...

  • Page 21: Figure 13: 16 Mhz Or 32 Mhz Crystal Oscillator, Recommended Operating Conditions

    Table 8 and in Table 9 below there are examples of some 16 MHz and 32 MHz crystals that meet the specification described above in Figure Application note Revision 1.9 28-Mar-2019 CFR0014 Rev 3 21 of 45 © 2019 Dialog Semiconductor...

  • Page 22: 32.768 Khz Clock

    MOhm resistor from the XTAL32Kp pin to ground, the DA14682 and DA14683 do not need this. The external crystal must meet the recommended operating conditions as indicated below: Application note Revision 1.9 28-Mar-2019 CFR0014 Rev 3 22 of 45 © 2019 Dialog Semiconductor...

  • Page 23: Figure 15: 32.768 Khz Crystal Oscillator, Recommended Operating Conditions

    (e.g. MCU) to the P2_0 pin of the DA1468x, the following procedure needs to be applied: • XTAL32K oscillator must be disabled by applying: CLK_32K_REG [XTAL32K_ENABLE] = 0x0 • CLK32K_SOURCE must be set to select external clock signal: Application note Revision 1.9 28-Mar-2019 CFR0014 Rev 3 23 of 45 © 2019 Dialog Semiconductor...

  • Page 24: Generating A Clock Output From The Da1468X

    GPIO_CLK_SEL: FUNC_CLOCK_SEL set to 0x3 for the 16MHz Xtal clock. Please find below the tables showing the P1_0 register settings: P10_MODE_REG (0x5000302E), and GPIO Clock Selection: FUNC_CLOCK_SEL (0x500030D0). Application note Revision 1.9 28-Mar-2019 CFR0014 Rev 3 24 of 45 © 2019 Dialog Semiconductor...

  • Page 25: Uart

    P0_6 and P2_4 can be used as GPIOs when they will not be used as SWD (serial wire debugging) interface. Table 12: JTAG pins AQFN60 WLCSP Function name JTAG data (SWDIO) P0_6 JTAG JTAG clock (SWCLK) P2_4 Application note Revision 1.9 28-Mar-2019 CFR0014 Rev 3 25 of 45 © 2019 Dialog Semiconductor...

  • Page 26: Qspi Flash Memory

    The in Figure 3 and in Figure 4 indicated 10K pull-up resistor at the QSPI Flash CS pin is not mandatory, the DA14681/683 QSPI_CS port will also pull the CS line high. Application note Revision 1.9 28-Mar-2019 CFR0014 Rev 3 26 of 45 © 2019 Dialog Semiconductor...

  • Page 27: Usb And Vbus

    Please make sure to have a short and solid ground connection, having a low impedance, to the ground terminal of the ESD protection device. Please read also section 5.9 for layout related ESD topics. Application note Revision 1.9 28-Mar-2019 CFR0014 Rev 3 27 of 45 © 2019 Dialog Semiconductor...

  • Page 28: Vbus Circuitry

    60 cm cable connection, whereas, when the length of the cable is increased to 150 cm, the damping reduces leading to larger voltage overshoots. Figure 20: used USB circuit for testing Application note Revision 1.9 28-Mar-2019 CFR0014 Rev 3 28 of 45 © 2019 Dialog Semiconductor...

  • Page 29: Figure 21: Step Response With 60 Cm (Left) And 150 Cm (Right) Cable (Non Usb-Cable). A Damping Network Of 0.39 Ω And 10 Μf Capacitor On Vbus Is Used

    0.47 Ω and a 6.8 µF can be used. These R-C combinations will result in the same damping value. Preferably the capacitors should be at least 10 V types. Application note Revision 1.9 28-Mar-2019 CFR0014 Rev 3 29 of 45 © 2019 Dialog Semiconductor...

  • Page 30: Hibernation Mode And Wakeup

    GPIO or configure the GPIO as input pull-down (adding the internal 25 kΩ resistor Application note Revision 1.9 28-Mar-2019 CFR0014 Rev 3 30 of 45 © 2019 Dialog Semiconductor...

  • Page 31: Figure 24: Wakeup From Hibernation By Vbus Voltage Using Gpio Trigger

    These SoCs are clockless when in ‘shipping’ or hibernation mode and need the Wake-Up Controller to wake up from this clockless mode (using the ~2V LDO_Ret Low Power Clamp). Application note Revision 1.9 28-Mar-2019 CFR0014 Rev 3 31 of 45 © 2019 Dialog Semiconductor...

  • Page 32: Rfio Port

    The cost of producing a PCB with microvias is higher in comparison to a PCB with PTH vias. For copper filled vias, cost and production time are significantly higher. Application note Revision 1.9 28-Mar-2019 CFR0014 Rev 3 32 of 45 © 2019 Dialog Semiconductor...

  • Page 33: Pcb Layout For Wlcsp53 Package

    Layer 3 is the reference GND plane (normal ground vias connect to this layer directly; 50 ohms microstrip line uses this layer as a ground reference). Application note Revision 1.9 28-Mar-2019 CFR0014 Rev 3 33 of 45 © 2019 Dialog Semiconductor...

  • Page 34: Figure 28: Wlcsp53 Pcb Layout, Top Side

    ‘hot’ pads of the 16 MHz or 32 MHz crystal. Please refer to Figure Figure 28: WLCSP53 PCB layout, top side Application note Revision 1.9 28-Mar-2019 CFR0014 Rev 3 34 of 45 © 2019 Dialog Semiconductor...

  • Page 35: Figure 29: Wlcsp53 Pcb Layout, Layer 2

    AN-B-061 DA1468x Application hardware design guidelines Company confidential Figure 29: WLCSP53 PCB layout, layer 2 Figure 30: WLCSP53 PCB layout, layer 3, reference GND Application note Revision 1.9 28-Mar-2019 CFR0014 Rev 3 35 of 45 © 2019 Dialog Semiconductor...

  • Page 36: Figure 31: Ground Connectivity Top (Left) And Layer 2 (Right)

    A decoupling cap should be placed very close to GND_BUCK and VBAT1, as is presented on Figure Figure 31: Ground connectivity Top (left) and layer 2 (right) Application note Revision 1.9 28-Mar-2019 CFR0014 Rev 3 36 of 45 © 2019 Dialog Semiconductor...

  • Page 37: Pcb Layout For Aqfn60 Package

    For the same reason, please provide openings in the nearest ground layer under the ‘hot’ pads of the 16 MHz or 32 MHz crystal. Please refer to Figure Application note Revision 1.9 28-Mar-2019 CFR0014 Rev 3 37 of 45 © 2019 Dialog Semiconductor...

  • Page 38: Figure 33: Aqfn60 Pcb Layout, Top Layer

    Figure 33 This Buck DCDC_Ground is located between the VBAT2, VBAT1 and VBUS pins: between pins B6 and B7. Figure 33: AQFN60 PCB layout, top layer Application note Revision 1.9 28-Mar-2019 CFR0014 Rev 3 38 of 45 © 2019 Dialog Semiconductor...

  • Page 39: 5.11 Aqfn60 - Package Outline (Pod) Information

    5.12 WLCSP53 - Package Outline (POD) Information Please refer to Section 39 of the DA14680-01, DA14681-01 and DA14682-00, DA14683-00 datasheets for information on the WLCSP53 package outline. [1] Application note Revision 1.9 28-Mar-2019 CFR0014 Rev 3 39 of 45 © 2019 Dialog Semiconductor...

  • Page 40: Appendix: Aqfn60 Assembly And Soldering Guidelines

    SMT assembly, the pad size used on the Dialog boards as showing below: Terminal pad: 0.25 x 0.25 mm ; Terminal solder mask: 0.4 x 0.4 mm Figure 35: PCB footprint data Application note Revision 1.9 28-Mar-2019 CFR0014 Rev 3 40 of 45 © 2019 Dialog Semiconductor...

  • Page 41: Stencil Design

    For the thermal paddle stencil opening, using array of 2x2 opening and 20% opening of PCB thermal paddle area is recommended to avoid void resident inside thermal paddle and can get better solderability. Application note Revision 1.9 28-Mar-2019 CFR0014 Rev 3 41 of 45 © 2019 Dialog Semiconductor...

  • Page 42: Component Placement

    • It is preferred to use a machine with fine-pitch placement for better accuracy. Application note Revision 1.9 28-Mar-2019 CFR0014 Rev 3 42 of 45 © 2019 Dialog Semiconductor...

  • Page 43: Reflow Profile

    DA1468x Application hardware design guidelines Company confidential Reflow Profile Below reflow-profile, based on using solder paste SAC305 Figure 37: Reflow profile for solder paste SAC305 Application note Revision 1.9 28-Mar-2019 CFR0014 Rev 3 43 of 45 © 2019 Dialog Semiconductor...

  • Page 44: Revision History

    This application note is to be used with the DA14680-01/681-01 and DA14682-00/683-00 SoCs. ● Added a table with 32 MHz crystal examples (DA14682/683 support 32 MHz crystal operation) Application note Revision 1.9 28-Mar-2019 CFR0014 Rev 3 44 of 45 © 2019 Dialog Semiconductor...
  • Page 45 Dialog Semiconductor excludes all liability in this respect. Customer notes that nothing in this document may be construed as a license for customer to use the Dialog Semiconductor products, software and applications referred to in this document. Such license must be separately sought by customer with Dialog Semiconductor.

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