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Dialog Semiconductor SLG46824 Programming Manual

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In-System Programming Guide
SLG46824/6
ISPG-SLG46824/6

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Summary of Contents for Dialog Semiconductor SLG46824

  • Page 1 In-System Programming Guide SLG46824/6 ISPG-SLG46824/6...

  • Page 2: Table Of Contents

    3.2 Addressing ................................8 4 Memory Spaces ..................................9 4.1 Memory Map ................................9 4.2 Special Pages ..............................10 5 Programming Algorithm for the Emulated EEPROM Space ..................11 6 Protection for Emulated EEPROM ............................13 Revision 1.1 4-Mar-2019 2 of 15 © 2019 Dialog Semiconductor...

  • Page 3: Hardware Requirements

    ISPG-SLG46824/6 SLG46824/6 Introduction This document describes the in-system programming procedures for SLG46824 and SLG46826. Hardware Requirements 1.1 PINOUT AND SIGNALS Four pins are required to program the SLG46824/6: V , GND, SCL and SDA. The V pin requires a voltage ranging from 2.5 V to 5.5 V for Programming (Write) operations, and 2.3 V to 5.5 V for Verification (Read) operations.
  • Page 4 = 2.3 V to 5.5 V Inputs Fall Time = 2.3 V to 5.5 V Stop Set-up Time = 2.3 V to 5.5 V SU_STD Data Out Hold Time = 2.3 V to 5.5 V Revision 1.1 4-Mar-2019 4 of 15 © 2019 Dialog Semiconductor...

  • Page 5: Programming Algorithm For Nvm Configuration Register Space

    SLG46824/6 Programming Algorithm for NVM Configuration Register Space The SLG46824 and SLG46826 programming algorithm for the NVM Configuration space consists of a series of I C Sequential Write commands, each of which will program one 16 byte page of NVM memory (Note Data “1”...
  • Page 6 Not Acknowledged Seq. Read for Word Address = Verify Word Address + Acknowledged Data Fail Correct Word Address = E0H? Done Figure 4: Flowchart for Programming NVM with Acknowledge Polling Revision 1.1 4-Mar-2019 6 of 15 © 2019 Dialog Semiconductor...

  • Page 7: I2C Signal Specifications

    Write access to the NVM is possible by setting A3 A2 A1 A0 to "0000", which allows serial write data for a single page only. Upon receipt of the proper Control Byte and Word Address bytes, the SLG46824/6 will send an ACK. The device will then be ready to receive page data, which is 16 sequential writes of 8-bit data words.

  • Page 8: Addressing

    ERSEB1 ERSEB0 Upon receipt of the proper Device Address and Erase Register Address, the SLG46824/6 will send an ACK. The device will then be ready to receive Erase Register data. The SLG46824/6 will respond with a non-compliant I C ACK after the Erase Register data word is received.

  • Page 9: Memory Spaces

    2 Kbits EEPROM (Note 2) emulated EEPROM (Note 2) A10 = 1 A9 = X A8 = X Not Used Highest I Address = 7FFh Figure 8: I C Block Addressing Revision 1.1 4-Mar-2019 9 of 15 © 2019 Dialog Semiconductor...

  • Page 10: Special

    The information on this page can be Read but not Written by the user. As this page cannot be altered by the user, the programming algorithm does not need to address this page. Revision 1.1 4-Mar-2019 10 of 15 © 2019 Dialog Semiconductor...

  • Page 11: Programming Algorithm For The Emulated Eeprom Space

    ISPG-SLG46824/6 SLG46824/6 Programming Algorithm for the Emulated EEPROM Space The SLG46824 and SLG46826 programming algorithm for the emulated EEPROM (Note 2) space consists of a series of I Sequential Write commands, each of which will program one 16 byte page of NVM memory.
  • Page 12 Not Acknowledged Seq. Read for Word Address = Verify Word Address + Acknowledged Data Fail Correct Word Address = E0H? Done Figure 11: Flowchart for Programming Emulated EEPROM with Acknowledge Polling Revision 1.1 4-Mar-2019 12 of 15 © 2019 Dialog Semiconductor...

  • Page 13: Protection For Emulated Eeprom

    ISPG-SLG46824/6 SLG46824/6 Protection for Emulated EEPROM The SLG46824/6 utilizes a software scheme that allows a portion or the entire emulated EEPROM (Note 2) to be inhibited from being written/ erased to by modifying the contents of the Write Protection Register (WPR). If desired, the WPR can be set so that it may no longer be modified/erased, thereby making the current protection scheme permanent.
  • Page 14 Non-Volatile Memory Read/Write/Erase Protection Non-Volatile Memory Protect Lock Bit Read/Write Register Register Read/Write Protection C Clock Input C Data Input/Output Write Protect Block Bits Write Protection Register WPRE Write Protect Register Enable Revision 1.1 4-Mar-2019 14 of 15 © 2019 Dialog Semiconductor...

  • Page 15: Revision History

    Standard Terms and Conditions of Sale, available on the company website (www.dialog-semiconductor.com) unless otherwise stated. Dialog and the Dialog logo are trademarks of Dialog Semiconductor plc or its subsidiaries. All other product or service names are the property of their respective owners.

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Slg46826

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