Ziatech Corporation ZT 8906 Manuals

Manuals and User Guides for Ziatech Corporation ZT 8906. We have 1 Ziatech Corporation ZT 8906 manual available for free PDF download: Hardware Manual

Ziatech Corporation ZT 8906 Hardware Manual

Ziatech Corporation ZT 8906 Hardware Manual (166 pages)

Single Board Computer with Pentium Processor

Brand: Ziatech Corporation | Category: Motherboard | Size: 0.92 MB

Table of Contents
8
Chapter 1. Introduction

18
- Product Definition
  18
  - Stand Alone
    18
  - STD 32 Single Master
    19
  - STD 32 Multiple Master (STAR SYSTEM)
    19
- Features of the Zt 8905
  19
- Development Considerations
  20
- Functional Blocks
  21
  - Functional Block Diagram
    21
  - Pentium Processor Comparison
    22
  - Pentium Processors
    22
  - STD 32 Bus Interface
    22
  - Memory and I/O Addressing
    23
  - PCI Local Bus
    23
  - Serial I/O
    23
  - Counter/Timers
    24
  - Dma
    24
  - Interrupts
    24
  - Watchdog Timer
    24
  - IEEE® 1284 Parallel Port/Printer Interface
    25
  - J5 Multi-I/O Connector
    25
  - Keyboard Controller
    25
  - Real-Time Clock
    25
  - Optional IDE Interface
    26
  - Speaker Interface
    26
Chapter 2. Getting Started

28
- Unpacking
  28
- What's in the Box
  28
- System Requirements
  28
- Memory Configuration
  29
- Typical DRAM Configurations
  29
- I/O Configuration
  30
- Memory Address Map
  30
- I/O Address Map
  31
- Connector Configuration
  32
- Connector Assignments
  32
- Connector Locations
  32
- Jumper Descriptions
  33
- Zt 8905 Setup
  33
Chapter 3. Std 32 Bus Interface

38
- Std 32 Background
  38
- Std-80 Peripheral Support
  38
  - Address Multiplexing
    38
  - Interrupts
    39
  - I/O Expansion
    39
  - DMA Slave Support
    39
- Std 32 Bus Compatibility
  39
  - Standard Architecture
    39
  - Extended Architecture
    40
  - Multiprocessing
    40
  - STD 32 Compliance Levels
    40
- Std Bus Interrupts
  41
- Reset
  43
- Multiple Master and Intelligent I/O
  43
  - Non-Maskable Interrupt Structure
    43
  - Intelligent I/O
    44
  - Multiple Master
    44
  - Multiple Master Architecture
    44
  - Intelligent I/O Architecture
    45
  - Multiple Master System Requirements
    45
  - Multiple Master Vs. Intelligent I/O
    45
  - Socket T6C Location
    46
  - Multiple Master Reset
    47
Chapter 4. Interrupt Controller

48
- Interrupt Architecture
  49
- Interrupt Sources
  50
- Programmable Registers
  50
  - Interrupt Controller Register Addressing
    50
  - Initialization Registers (ICW1-ICW4)
    51
    
    Interrupt Initialization Programming
    51
    
    Initialization Register ICW1
    52
    
    Initialization Register ICW2
    52
    
    Initialization Register ICW3
    52
    
    Master Initialization Register ICW3
    52
    
    Register a
    52
    
    Slave Initialization Register ICW3
    52
    
    Initialization Register ICW4
    53
  - Operational Registers (OCW1-OCW3)
    53
    
    Operational Register OCW1
    53
    
    Operational Register OCW2
    54
    
    Operational Register OCW3
    55
  - Status Registers (IRR, ISR, IPR)
    55
    
    Status Register IRR
    55
    
    Status Register ISR
    56
    
    Status Register IPR
    56
  - Extended Mode Register
    57
- Additional Information
  57
Chapter 5. Counter/Timers

58
- Counter/Timer Architecture
  58
- Programmable Registers
  59
  - Count Registers and Count Latch
    59
  - Counter/Timer Operating Modes
    59
  - Counter/Timer Register Addressing
    59
  - General Control Register
    59
  - Status Register
    60
  - Count Register High Byte
    60
  - Count Register Low Byte
    60
  - Control Register
    61
    
    General Control Register
    61
    
    Count Latch Control Register
    61
    
    Multiple Latch Control Register
    62
- Additional Information
  62
Chapter 6. Dma Controller

64
- Zt 8905 Specifics
  64
- Programmable Registers
  65
  - DMA Architecture
    65
  - DMA Extended
    66
  - DMA Extended Page (A24-31) I/O Port Addressing
    66
  - DMA Page I/O Port Addressing
    66
  - Slave DMA I/O Port Addressing
    66
  - Address Register
    67
  - Address Register (16-Bit I/O)
    67
  - Address Register (8-Bit I/O)
    67
  - Count Register
    67
  - Register C
    67
  - Command Register
    68
  - Status Register
    68
  - Write Request Register
    69
  - Write Single Mask Register
    69
  - DMA Extended Mode Register
    70
  - Write Mode Register
    70
  - Clear Byte Register
    71
  - Clear Mask Register
    71
  - Clear Master Register
    71
  - Write Mask Register
    71
  - DMA Extended Page Register
    72
  - DMA Page Register
    72
- Additional Information
  72
Chapter 7. Real-Time Clock

74
- Programmable Registers
  74
  - Real-Time Clock Register Addressing
    74
  - Register a
    75
  - Register B
    75
  - Register C
    76
  - Register D
    76
- Additional Information
  76
Chapter 8. Serial Controller

78
- Zt 8905 Specifics
  78
  - Address Mapping
    78
  - Interrupt Selection
    79
  - Handshake Signals
    79
  - Serial Channel Interface
    79
- Programmable Registers
  79
  - Serial Controller Register Addressing
    79
  - Baud Rate Divisors
    80
  - Baud Rate Divisors Table
    80
  - Divisor Latch LSB
    81
  - Divisor Latch LSB and MSB
    81
  - Divisor Latch MSB
    81
  - Interrupt Control Register
    81
  - Interrupt Status Register
    82
  - Line Control Register
    82
  - Line Status Register
    83
  - Modem Control Register
    83
  - Modem Status Register
    84
- Additional Information
  84
Chapter 9. Ieee-1284 Parallel Port Interface

86
- Parallel Port Configuration Options
  86
- Address Mapping
  87
- Interrupt Selection
  87
- Dma Selection
  87
- Programmable Registers
  87
- Additional Information
  89
Chapter 10. Optional Ide Interface

90
Chapter 11. System Registers

92
- Programmable Registers
  92
  - System Register 0
    92
  - System Register 1
    93
Chapter 12. Watchdog Timer

94
- Watchdog Timer Operation
  94
- Additional Information
  94
- System Register 1
  94
- Watchdog Timer Architecture
  94
Chapter 13. Pci Mezzanine Local Bus

96
- Pci Operation Frequency
  96
- Additional Information
  96
Chapter 14. Programmable Led

98
Appendix A. Board Configuration

100
- Bios Setup Overview
  100
  - ZT 8905-Specific SETUP Options
    102
- Jumper Options and Locations
  102
- DOS Factory Default Jumper Configuration
  103
- Customer Jumper Configuration
  103
- Jumper Cross-Reference Table
  104
- Jumper Descriptions
  104
  - W1A, W1B (CMOS RAM Erase)
    104
  - W1C (Boot from On-Board Flash Device)
    104
  - W1D (Reserved)
    105
  - W1E (Reserved)
    105
  - W1F (Temporary Master to ZT 8911)
    105
  - W2, W3 (Reserved)
    105
- Cuttable Trace Options and Locations
  105
  - CT1, CT2 (Frontplane DMA)
    106
  - Cuttable Trace Locations
    106
Appendix B. Specifications

108
- Electrical and Environmental
  108
  - Absolute Maximum Ratings
    108
  - ZT 8905 Key Parts
    108
  - Pentium Processors Maximum Ambient Temperatures
    109
  - Ambient Temperature Vs. Pentium Processor Case Temperature
    109
  - DC Operating Characteristics
    110
  - Battery Backup Characteristics
    110
  - STD Bus Loading Characteristics
    111
  - STD Bus Loading, P Connector
    111
  - STD Bus Loading, E Connector
    112
- Mechanical
  113
  - Card Dimensions and Weight
    113
  - Board Dimensions
    113
  - Connectors
    114
    
    P/E (STD-80/STD 32 Bus)
    115
    
    J1 (L2 Cache Module)
    116
    
    J2 (Fan Connector)
    116
    
    J2 Fan Connector Pinout
    116
    
    J3 (PCI Local Bus Interface)
    117
    
    J3 PCI Local Bus Connector Pinout
    117
    
    J4 (VGA Transition Connector)
    118
    
    J5 (Multi-I/O Connector)
    118
    
    J4 VGA Transition Connector Pinout
    118
    
    J5 Multi-I/O Connector Pinout
    119
    
    J6 (Floppy Disk Controller Interface)
    120
    
    J7 (IDE Hard Disk Interface)
    120
    
    J7 IDE Hard Disk Connector Pinout
    120
  - Cable
    121
  - ZT 90205 Rev. 0 Multi-I/O Cable
    121
Appendix C. Customer Support

122
- Technical/Sales Assistance
  122
- Revision History
  122
- Reliability
  123
- Returning for Service
  124
- Ziatech 5+5 Warranty
  124
  - Five-Year Limited Warranty
    124
  - Special Extended Warranty Option
    125
  - Life Support Policy
    125
Appendix D. Pci Configuration Space Map

126

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Ziatech Corporation ZT 8906 Manuals

Ziatech Corporation ZT 8906 Hardware Manual (166 pages)

Table of Contents

Chapter 1. Introduction

Chapter 2. Getting Started

Chapter 3. Std 32 Bus Interface

Chapter 4. Interrupt Controller

Chapter 5. Counter/Timers

Chapter 6. Dma Controller

Chapter 7. Real-Time Clock

Chapter 8. Serial Controller

Chapter 9. Ieee-1284 Parallel Port Interface

Chapter 10. Optional Ide Interface

Chapter 11. System Registers

Chapter 12. Watchdog Timer

Chapter 13. Pci Mezzanine Local Bus

Chapter 14. Programmable Led

Appendix A. Board Configuration

Appendix B. Specifications

Appendix C. Customer Support

Appendix D. Pci Configuration Space Map

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