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Seiko Epson S1C17 Series Manual

Cmos 16-bit single chip microcomputer.s1c17 core
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CMOS 16 - BIT SINGLE CHIP MICROCOMPUTER
S1C17 Family
S1C17 Core Manual

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  • Page 1 CMOS 16 - BIT SINGLE CHIP MICROCOMPUTER S1C17 Family S1C17 Core Manual...
  • Page 2 No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not...
  • Page 3 Configuration of product number Devices 17xxx 00E1 Packing specifications 00 : Besides tape & reel 0A : TCP BL 2 directions 0B : Tape & reel BACK 0C : TCP BR 2 directions 0D : TCP BT 2 directions 0E : TCP BD 2 directions 0F : Tape &...

  • Page 5: Table Of Contents

    CONTENTS – Contents – 1 Summary ........................1-1 1.1 Features ...........................1-1 2 Registers ........................2-1 2.1 General-Purpose Registers (R0–R7) ................2-1 2.2 Program Counter (PC) .....................2-1 2.3 Processor Status Register (PSR)..................2-2 2.4 Stack Pointer (SP)......................2-4 2.4.1 About the Stack Area ..................2-4 2.4.2 SP Operation at Subroutine Call/Return............2-4 2.4.3 SP Operation when an Interrupt Occurs............2-5 2.4.4 Saving/Restoring Register Data Using a Load Instruction ........2-6 2.5 Register Notation and Register Numbers ................2-7...
  • Page 6 CONTENTS 5.3 Addressing Modes with ext.....................5-8 5.3.1 Extension of Immediate Addressing ..............5-8 5.3.2 Extension of Register Direct Addressing ............5-9 5.3.3 Extension of Register Indirect Addressing ............5-10 5.3.4 Extension of Register Indirect Addressing with Displacement......5-11 5.3.5 Extension of Signed PC Relative Addressing ...........5-11 5.3.6 Extension of PC Absolute Addressing ..............5-12 5.4 Data Transfer Instructions ....................5-13 5.5 Logical Operation Instructions..................5-14...
  • Page 7 CONTENTS add.a/c %rd, %rs ..........................7-6 add.a/nc %rd, %rs ..........................7-6 add.a %rd, imm7 .......................... 7-7 add.a %sp, %rs ..........................7-8 add.a %sp, imm7 ......................... 7-9 %rd, %rs ..........................7-10 and/c %rd, %rs ..........................7-10 and/nc %rd, %rs ..........................7-10 %rd, sign7 .........................
  • Page 8 CONTENTS jrlt.d sign7..........................7-42 jrne sign7..........................7-43 jrne.d sign7..........................7-43 jruge sign7..........................7-44 jruge.d sign7..........................7-44 jrugt sign7..........................7-45 jrugt.d sign7..........................7-45 jrule sign7..........................7-46 jrule.d sign7..........................7-46 jrult sign7..........................7-47 jrult.d sign7..........................7-47 %rd, %rs ..........................7-48 %rd, [%rb] ......................... 7-49 %rd, [%rb]+ ........................
  • Page 9 CONTENTS ld.b [%rb]+, %rs ........................7-81 ld.b [%rb]-, %rs ........................7-81 ld.b -[%rb], %rs ........................7-81 ld.b [%sp + imm7], %rs ......................7-83 ld.b [imm7], %rs ........................7-84 ld.ca %rd, %rs ..........................7-85 ld.ca %rd, imm7 ......................... 7-86 ld.cf %rd, %rs ..........................7-87 ld.cf %rd, imm7 .........................
  • Page 10 CONTENTS Appendix List of S1C17 Core Instructions..............Ap-1 EPSON S1C17 FAMILY S1C17 CORE MANUAL...

  • Page 11: Features

    The S1C17 Core incorporates a coprocessor interface allowing implementation of additional computing features. Furthermore, Seiko Epson provides a software development environment similar to the S1C33 Family that includes an IDE work bench, a C compiler, a serial ICE and a debugger, for supporting the developer to develop application software.
  • Page 12 1 SUMMARY THIS PAGE IS BLANK. EPSON S1C17 FAMILY S1C17 CORE MANUAL...

  • Page 13: Registers

    2 REGISTERS 2 Registers The S1C17 Core contains eight general-purpose registers and three special registers. Special registers General-purpose registers bit 23 bit 0 bit 23 bit 0 IL[2:0] Figure 2.1 Registers 2.1 General-Purpose Registers (R0–R7) Symbol Register name Size Initial value R0–R7 General-Purpose Register 24 bits...

  • Page 14: Processor Status Register (Psr)

    2 REGISTERS 2.3 Processor Status Register (PSR) Symbol Register name Size Initial value Processor Status Register 8 bits 0x00 The Processor Status Register (hereinafter referred to as the “PSR”) is an 8-bit register for storing the internal status of the processor. The PSR stores the internal status of the processor when the status has been changed by instruction execution.
  • Page 15 2 REGISTERS The V flag is set under the following conditions: (1) When negative integers are added together, the operation produced a 0 (positive) in the sign bit (most sig- nificant bit of the result) (2) When positive integers are added together, the operation resulted in a 1 (negative) in the sign bit (most sig- nificant bit of the result) (3) When a negative integer is subtracted from a positive integer, the operation resulted in producing a 1 (nega- tive) in the sign bit (most significant bit of the result)

  • Page 16: Stack Pointer (Sp)

    2 REGISTERS 2.4 Stack Pointer (SP) Symbol Register name Size Initial value Stack Pointer 24 bits 0x000000 The Stack Pointer (hereinafter referred to as the “SP”) is a 24-bit register for holding the start address of the stack. The stack is an area locatable at any place in the system RAM, the start address of which is set in the SP during the initialization process.

  • Page 17: Sp Operation When An Interrupt Occurs

    2 REGISTERS SP operation by the ret instruction (1) [SP] → PC (2) SP = SP + 4 0xffffff 0xffffff SP = SP + 4 0x00 0x00 PC[23:16] PC[23:16] PC[15:8] PC[15:8] PC[7:0] PC[7:0] 0x000000 0x000000 Figure 2.4.2.2 SP and Stack (2) 2.4.3 SP Operation when an Interrupt Occurs If an interrupt or a software interrupt resulting from the int/intl instruction occurs, the processor enters an inter- rupt handling process.

  • Page 18: Saving/Restoring Register Data Using A Load Instruction

    2 REGISTERS 2.4.4 Saving/Restoring Register Data Using a Load Instruction The S1C17 Core provides load instructions to save and restore register data to/from the stack instead of push/pop instructions. Saving register data into the stack Example: ld.a -[%sp],%r0 (1) SP = SP - 4 (2) R0 →...

  • Page 19: Register Notation And Register Numbers

    2 REGISTERS 2.5 Register Notation and Register Numbers The following describes the register notation and register numbers in the S1C17 Core instruction set. 2.5.1 General-Purpose Registers In the instruction code, a general-purpose register is specified using a 3-bit field, with the register number entered in that field.
  • Page 20 2 REGISTERS THIS PAGE IS BLANK. EPSON S1C17 FAMILY S1C17 CORE MANUAL...

  • Page 21: Data Formats

    3 DATA FORMATS 3 Data Formats 3.1 Data Formats Handled in Operations Between Registers The S1C17 Core can handle 8-, 16-, and 24-bit data in register operations. In this manual, data sizes are expressed as follows: Byte, B, or b 8-bit data Word, W, or w 16-bit data...

  • Page 22: 16-Bit Transfer (Register → Register)

    3 DATA FORMATS 3.1.3 16-Bit Transfer (Register → Register) Example: ld %rd,%rs 16 15 16-bit data 16 15 16-bit data Figure 3.1.3.1 16-Bit Transfer (Register → Register) Bits 23–16 in the destination register are set to 0x00. 3.1.4 24-Bit Transfer (Register → Register) Example: ld.a %rd,%rs 24-bit data...

  • Page 23: Unsigned 8-Bit Transfer (Memory → Register)

    3 DATA FORMATS 3.2.1 Unsigned 8-Bit Transfer (Memory → Register) Example: ld.ub %rd,[%rb] Byte [%rb] 16 15 Byte Figure 3.2.1.1 Unsigned 8-Bit Transfer (Memory → Register) Bits 23–8 in the destination register are set to 0x0000. 3.2.2 Signed 8-Bit Transfer (Memory → Register) Example: ld.b %rd,[%rb] Byte...

  • Page 24: 16-Bit Transfer (Register → Memory)

    3 DATA FORMATS 3.2.5 16-Bit Transfer (Register → Memory) Example: ld [%rb],%rs Byte 1 Byte 0 0b∗∗∗∗∗∗∗1 Byte 1 [%rb] 0b∗∗∗∗∗∗∗0 Byte 0 Figure 3.2.5.1 16-Bit Transfer (Register → Memory) 3.2.6 32-Bit Transfer (Memory → Register) Example: ld.a %rd,[%rb] 0b∗∗∗∗∗∗11 Byte 3 Ignored after read 0b∗∗∗∗∗∗10...

  • Page 25: Address Map

    0xff fdff 0x00 0000 Figure 4.1.1 Address Space of the S1C17 Core The boot address and debug RAM address depend on the specifications of each the S1C17 Series models. Refer to the Technical Manual of each model. EPSON S1C17 FAMILY S1C17 CORE MANUAL...

  • Page 26: Processor Information In The Core I/O Area

    4 ADDRESS MAP 4.2 Processor Information in the Core I/O Area The reserved core I/O area contains the processor information described below. 4.2.1 Trap Table Base Register (TTBR, 0xffff80) Register name Address Name Function Setting Init. R/W Remarks Trap table FFFF80 D31–24 –...

  • Page 27: Instruction Set

    5 INSTRUCTION SET 5 Instruction Set The S1C17 Core instruction codes are all fixed to 16 bits in length which, combined with pipelined processing, al- lows most important instructions to be executed in one cycle. For details, refer to the description of each instruction in the latter sections of this manual.
  • Page 28 5 INSTRUCTION SET Classification Mnemonic Function General-purpose register (32 bits, zero-extended) → stack * Data transfer ld.a [%sp],%rs Stack pointer post-increment, post-decrement, and pre-decrement functions can [%sp]+,%rs be used. [%sp]-,%rs -[%sp],%rs General-purpose register (24 bits) → SP %sp,%rs Immediate → SP %sp,imm7 Integer arithmetic 16-bit addition between general-purpose registers...
  • Page 29 5 INSTRUCTION SET Classification Mnemonic Function Shift and swap Logical shift to the right with the number of bits specified by the register %rd,%rs Logical shift to the right with the number of bits specified by immediate %rd,imm7 Arithmetic shift to the right with the number of bits specified by the register %rd,%rs Arithmetic shift to the right with the number of bits specified by immediate %rd,imm7...
  • Page 30 5 INSTRUCTION SET The symbols in the above table each have the meanings specified below. Table 5.1.2 Symbol Meanings Symbol Description General-purpose register, source General-purpose register, destination Memory addressed by general-purpose register [%rb] Memory addressed by general-purpose register with address post-incremented [%rb]+ Memory addressed by general-purpose register with address post-decremented [%rb]-...

  • Page 31: Addressing Modes (Without Ext Extension)

    5 INSTRUCTION SET 5.2 Addressing Modes (without ext extension) The instruction set of the S1C17 Core has seven discrete addressing modes, as described below. The processor de- termines the addressing mode according to the operand in each instruction before it accesses data. (1) Immediate addressing (2) Register direct addressing (3) Register indirect addressing...

  • Page 32: Register Indirect Addressing

    5 INSTRUCTION SET 5.2.3 Register Indirect Addressing In this mode, memory is accessed indirectly by specifying a general-purpose register or the stack pointer that holds the address needed. This addressing mode is used only for load instructions that have [%rb] or [%sp] as the op- erand.

  • Page 33: Register Indirect Addressing With Displacement

    5 INSTRUCTION SET 5.2.5 Register Indirect Addressing with Displacement In this mode, memory is accessed beginning with the address that is derived by adding a specified immediate (dis- placement) to the register content. Unless ext instructions are used, this addressing mode can only be used for load instructions that have [%sp+imm7] as the operand.

  • Page 34: Addressing Modes With Ext

    5 INSTRUCTION SET 5.3 Addressing Modes with ext The immediate specifiable in 16-bit, fixed-length instruction code is specified in a bit field of a 7- or 10-bit length, depending on the instruction used. The ext instructions are used to extend the size of this immediate. The ext instructions are used in combination with data transfer, arithmetic/logic, or branch instructions, and is placed directly before the instruction whose immediate needs to be extended.

  • Page 35: Extension Of Register Direct Addressing

    5 INSTRUCTION SET Extension of sign7 The sign7 immediate is extended to a 16-bit immediate. Extending to a 16-bit immediate To extend the immediate to 16-bit quantity, enter one ext instruction directly before the target instruction. Example: ext imm13 %rd,sign7 Extended immediate imm13 sign7...

  • Page 36: Extension Of Register Indirect Addressing

    5 INSTRUCTION SET operation instructions) Extending to rs + imm24 (24-bit To extend to rs + imm24, enter two ext instructions directly before the target instruction. Example: ext imm13 imm13 add.a %rd,%rs If not extended, rd = rd + rs When extended by two ext instructions, rd = rs + imm24 Data 13 12...

  • Page 37: Extension Of Register Indirect Addressing With Displacement

    5 INSTRUCTION SET 5.3.4 Extension of Register Indirect Addressing with Displacement Extending [%sp+imm7] displacement The immediate (imm7) in displacement-added register indirect addressing instructions is extended. The extended data and the SP are added to comprise the source or destination address of transfer. Extending to a 20-bit immediate To extend the immediate to 20-bit quantity, enter one ext instruction directly before the target instruction.

  • Page 38: Extension Of Pc Absolute Addressing

    5 INSTRUCTION SET Extending to a 24-bit immediate To extend the sign7 immediate to a 24-bit immediate, enter two ext instructions directly before the target in- struction. Example: ext imm13 imm13 jrgt sign7 ; = jrgt sign24 21 20 Immediate S (1) imm13 (2) sign7...

  • Page 39: Data Transfer Instructions

    5 INSTRUCTION SET 5.4 Data Transfer Instructions The transfer instructions in the S1C17 Core support data transfer between one register and another, as well as be- tween a register and memory. A transfer data size and data extension format can be specified in the instruction code. In mnemonics, this specification is classified as follows: Signed byte data transfer ld.b...

  • Page 40: Logical Operation Instructions

    5 INSTRUCTION SET 5.5 Logical Operation Instructions Four discrete logical operation instructions are available for use with the S1C17 Core. Logical AND Logical OR Exclusive-OR Logical NOT All logical operations are performed in a specified general-purpose register (R0–R7). The source is one of two, ei- ther 16-bit data in a specified general-purpose register or immediate data (7, 13, or 16 bits).

  • Page 41: Arithmetic Operation Instructions

    5 INSTRUCTION SET 5.6 Arithmetic Operation Instructions The instruction set of the S1C17 Core supports add/subtract, and compare instructions for arithmetic operations. 16-bit addition 24-bit addition add.a 16-bit addition with carry 16-bit subtraction 24-bit subtraction sub.a 16-bit subtraction with borrow 16-bit comparison 24-bit comparison cmp.a...

  • Page 42: Shift And Swap Instructions

    5 INSTRUCTION SET 5.7 Shift and Swap Instructions The S1C17 Core supports instructions to shift or swap the register data. Logical shift right Logical shift left (= Arithmetic shift left) Arithmetic shift right Swap upper and lower bytes swap The shift operation is effective for bits 15 to 0 in the specified register and bits 23 to 16 are set to 0. The number of bits to be shifted can be specified to 0–3 bits, 4 bits, or 8 bits using the operand imm5 or the rs reg- ister.

  • Page 43: Branch And Delayed Branch Instructions

    5 INSTRUCTION SET 5.8 Branch and Delayed Branch Instructions 5.8.1 Types of Branch Instructions (1) PC relative jump instructions PC relative jump instructions include the following: sign7 sign10 PC relative jump instructions are provided for relocatable programming, so that the program branches to the ad- dress calculated as PC + 2 (the next address of the branch instruction) + signed displacement (specified by the operand).
  • Page 44 5 INSTRUCTION SET When extended by one ext instruction imm13 Functions as “jr* sign21” (sign21 = {imm13, sign7, 0}) sign7 The imm13 specified by the ext instruction is extended as the 13 high-order bits of sign21. sign21 S S S imm13 sign7 Current address...
  • Page 45 5 INSTRUCTION SET For jpr %rb A signed 24-bit relative value is specified for rb. The jump address is configured as follows: {rb(23:1), 0} D(23:1) Current address Branch destination address The least significant bit in the rb register is always handled as 0. The range of addresses to which jumped is (PC - 8,388,606) to (PC + 8,388,608).
  • Page 46 5 INSTRUCTION SET jpa imm7 20 19 imm7 with no ext 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 imm7 imm7 with one ext imm13 imm7 imm7 with two ext imm13 imm13' imm7 (3:0) Branch destination address (3) PC relative call instructions...

  • Page 47: Delayed Branch Instructions

    5 INSTRUCTION SET 5.8.2 Delayed Branch Instructions The S1C17 Core uses pipelined instruction processing, in which instructions are executed while other instructions are being fetched. In a branch instruction, because the instruction that follows it has already been fetched when it is executed, the execution cycles of the branch instruction can be reduced by one cycle by executing the prefetched in- struction before the program branches.

  • Page 48: System Control Instructions

    5 INSTRUCTION SET 5.9 System Control Instructions The following five instructions are used to control the system. Only increments the PC, with no other operations performed Places the processor in HALT mode halt Places the processor in SLEEP mode Enables interrupts Disables interrupts For details on HALT and SLEEP modes, refer to Section 6.4, “Power-Down Mode,”...

  • Page 49: Conversion Instructions

    5 INSTRUCTION SET 5.10 Conversion Instructions The 8/16/24/32 data conversion instructions listed below are provided for supporting C compiler. cv.ab %rd,%rs Converts Byte data (8 bits) into 24-bit data with sign extended. Byte 8 bits cv.as %rd,%rs Converts 16-bit data into 24-bit data with sign extended. 16 15 Word 16 15...

  • Page 50: Coprocessor Instructions

    5 INSTRUCTION SET 5.11 Coprocessor Instructions The S1C17 Core incorporates a coprocessor interface and provides the dedicated coprocessor instructions listed be- low. Transfer data to the coprocessor ld.cw Transfer data and input the results and flag status to/from the coprocessor ld.ca Input flag status from the coprocessor ld.cf...

  • Page 51: Functions

    6 FUNCTIONS 6 Functions This chapter describes the processing status of the S1C17 Core and outlines the operation. 6.1 Transition of the Processor Status The diagram below shows the transition of the operating status in the S1C17 Core. Reset state Interrupt instruction Interrupt...

  • Page 52: Program Execution

    6 FUNCTIONS 6.2 Program Execution Following initial reset, the processor loads the reset vector (address of the reset handler routine) into the PC and starts executing instructions beginning with the address. As the instructions in the S1C17 Core are fixed to 16 bits in length, the PC is incremented by 2 each time an instruction is fetched from the address indicated by the PC.

  • Page 53: Execution Cycles And Flags

    6 FUNCTIONS 6.2.2 Execution Cycles and Flags The following shows the number of cycles required for executing each instruction in a 1-cycle accessible memory connected to the Harvard bus and the flag change status. Depending on the model, clock cycles spent by the external bus arbiter and wait cycles inherent in the external devices may be added.
  • Page 54 6 FUNCTIONS Flag Classification Mnemonic Cycle Remark ∗1 ∗1: 1 cycle when ext is not Data transfer 1–2 – – – – – – ld.a [%sp],%rs used – – – – – – [%sp]+,%rs – – – – – – 2 cycles when ext is [%sp]-,%rs used...
  • Page 55 6 FUNCTIONS Flag Classification Mnemonic Cycle Remark ↔ ↔ ↔ Shift and swap – – – %rd,%rs ↔ ↔ ↔ – – – %rd,imm7 ↔ ↔ ↔ – – – %rd,%rs ↔ ↔ ↔ – – – %rd,imm7 ↔ ↔ ↔...

  • Page 56: Interrupts

    6 FUNCTIONS 6.3 Interrupts When an interrupt occurs during program execution, the processor enters an interrupt handling state. The interrupt handling state is a process by which the processor branches to the corresponding user’s service routine for the interrupt that occurred. The processor returns after branching and starts executing the program from where it left off.

  • Page 57: Vector Table

    6 FUNCTIONS 6.3.2 Vector Table Vector table in the S1C17 Core The table below lists the interrupts for which the vector table is referenced during interrupt handling. Table 6.3.2.1 Vector List Vector No. Interrupt Vector address Software interrupt No. 0 (0x00) Reset TTBR + 0x00 1 (0x01)

  • Page 58: Address Misaligned Interrupt

    6 FUNCTIONS 6.3.5 Address Misaligned Interrupt The load instructions that access memory or I/O areas are characteristic in that the data size to be transferred is predetermined for each instruction used, and that the accessed addresses must be aligned with the respective data- size boundaries.

  • Page 59: Software Interrupts

    6 FUNCTIONS 6.3.8 Software Interrupts The S1C17 Core provides the int imm5 and intl imm5,imm3 instructions allowing the software to generate any interrupts. The operand imm5 specifies a vector number (0–31) in the vector table. In addition to this, the intl instruction has the operand imm3 to specify an interrupt level (0–7) to be set to the IL field in the PSR.

  • Page 60: Power-Down Mode

    6 FUNCTIONS 6.4 Power-Down Mode The S1C17 Core supports two power-down modes: HALT and SLEEP modes. HALT mode Program execution is halted at the same time that the S1C17 Core executes the halt instruction, and the processor enters HALT mode. HALT mode commonly turns off only the S1C17 Core operation, note, however that modules to be turned off depend on the implementation of the clock control circuit outside the core.

  • Page 61: Debug Circuit

    6 FUNCTIONS 6.5 Debug Circuit The S1C17 Core has a debug circuit to assist in software development by the user. 6.5.1 Debugging Functions The debug circuit provides the following functions: • Instruction break A debug interrupt is generated before the set instruction address is executed. An instruction break can be set at two addresses.

  • Page 62: Registers For Debugging

    6 FUNCTIONS 6.5.3 Registers for Debugging The reserved core I/O area contains the debug registers described below. 0xFFFF90: Debug RAM Base Register (DBRAM) Register name Address Name Function Setting Init. R/W Remarks Debug RAM FFFF90 D31–24 – Unused (fixed at 0) ∗...
  • Page 63 6 FUNCTIONS 0xFFFFB0: Instruction Break Address Register 0 (IBAR0) Register name Address Name Function Setting Init. R/W Remarks Instruction FFFFB0 – D31–24 Unused (fixed at 0) break address IBAR023 Instruction break address #0 0x0–0xFFFDE register 0 IBAR00 is fixed at 0. IBAR00 D[23:0] IBAR0[23:0]: Instruction Break Address #0...
  • Page 64 6 FUNCTIONS THIS PAGE IS BLANK. EPSON 6-14 S1C17 FAMILY S1C17 CORE MANUAL...

  • Page 65: Details Of Instructions

    7 DETAILS OF INSTRUCTIONS 7 Details of Instructions This section explains all the instructions in alphabetical order. Symbols in the instruction reference %rd, rd General-purpose registers (R0–R7) or their contents used as the destination %rs, rs General-purpose registers (R0–R7) or their contents used as the source %rb, rb General-purpose registers (R0–R7) or their contents that hold the base address to be accessed in register indirect addressing...

  • Page 66: Adc %Rd, %Rs

    7 DETAILS OF INSTRUCTIONS %rd, %rs adc/c %rd, %rs adc/nc %rd, %rs Function 16-bit addition with carry rd(15:0) ← rd(15:0) + rs(15:0) + C, rd(23:16) ← 0 Standard) Extension 1) rd(15:0) ← rs(15:0) + imm13(zero extended) + C, rd(23:16) ← 0 Extension 2) rd(15:0) ←...

  • Page 67: Adc %Rd, Imm7

    7 DETAILS OF INSTRUCTIONS adc %rd, imm7 Function 16-bit addition with carry rd(15:0) ← rd(15:0) + imm7(zero extended) + C, rd(23:16) ← 0 Standard) Extension 1) rd(15:0) ← rd(15:0) + imm16 + C, rd(23:16) ← 0 Extension 2) Unusable 15 14 13 12 11 10 Code imm7 Flag...

  • Page 68: Add %Rd, %Rs

    7 DETAILS OF INSTRUCTIONS %rd, %rs add/c %rd, %rs add/nc %rd, %rs Function 16-bit addition rd(15:0) ← rd(15:0) + rs(15:0), rd(23:16) ← 0 Standard) Extension 1) rd(15:0) ← rs(15:0) + imm13(zero extended), rd(23:16) ← 0 Extension 2) rd(15:0) ← rs(15:0) + imm16, rd(23:16) ← 0 15 14 13 12 11 10 Code add/c...

  • Page 69: Add %Rd, Imm7

    7 DETAILS OF INSTRUCTIONS add %rd, imm7 Function 16-bit addition rd(15:0) ← rd(15:0) + imm7(zero extended), rd(23:16) ← 0 Standard) Extension 1) rd(15:0) ← rd(15:0) + imm16, rd(23:16) ← 0 Extension 2) Unusable 15 14 13 12 11 10 Code imm7 Flag –...

  • Page 70: Add.a %Rd, %Rs

    7 DETAILS OF INSTRUCTIONS add.a %rd, %rs add.a/c %rd, %rs add.a/nc %rd, %rs Function 24-bit addition rd(23:0) ← rd(23:0) + rs(23:0) Standard) Extension 1) rd(23:0) ← rs(23:0) + imm13(zero extended) Extension 2) rd(23:0) ← rs(23:0) + imm24 15 14 13 12 11 10 Code add.a add.a/c...

  • Page 71: Add.a %Rd, Imm7

    7 DETAILS OF INSTRUCTIONS add.a %rd, imm7 Function 24-bit addition rd(23:0) ← rd(23:0) + imm7(zero extended) Standard) Extension 1) rd(23:0) ← rd(23:0) + imm20(zero extended) Extension 2) rd(23:0) ← rd(23:0) + imm24 15 14 13 12 11 10 Code imm7 Flag –...

  • Page 72: Add.a %Sp, %Rs

    7 DETAILS OF INSTRUCTIONS add.a %sp, %rs Function 24-bit addition sp(23:0) ← sp(23:0) + rs(23:0) Standard) Extension 1) sp(23:0) ← rs(23:0) + imm13(zero extended) Extension 2) sp(23:0) ← rs(23:0) + imm24 15 14 13 12 11 10 Code Flag – –...

  • Page 73: Add.a %Sp, Imm7

    7 DETAILS OF INSTRUCTIONS add.a %sp, imm7 Function 24-bit addition sp(23:0) ← sp(23:0) + imm7(zero extended) Standard) Extension 1) sp(23:0) ← sp(23:0) + imm20(zero extended) Extension 2) sp(23:0) ← sp(23:0) + imm24 15 14 13 12 11 10 Code imm7 Flag –...

  • Page 74: And %Rd, %Rs

    7 DETAILS OF INSTRUCTIONS %rd, %rs and/c %rd, %rs and/nc %rd, %rs Function 16-bit logical AND rd(15:0) ← rd(15:0) & rs(15:0), rd(23:16) ← 0 Standard) Extension 1) rd(15:0) ← rs(15:0) & imm13(zero extended), rd(23:16) ← 0 Extension 2) rd(15:0) ← rs(15:0) & imm16, rd(23:16) ← 0 15 14 13 12 11 10 Code and/c...

  • Page 75: And %Rd, Sign7

    7 DETAILS OF INSTRUCTIONS and %rd, sign7 Function 16-bit logical AND rd(15:0) ← rd(15:0) & sign7(sign extended), rd(23:16) ← 0 Standard) Extension 1) rd(15:0) ← rd(15:0) & sign16, rd(23:16) ← 0 Extension 2) Unusable 15 14 13 12 11 10 Code sign7 Flag...

  • Page 76: Brk

    7 DETAILS OF INSTRUCTIONS Function Debugging interrupt A[DBRAM ] ← {psr, pc + 2}, A[DBRAM + 0x4] ← r0, pc ← 0xfffc00 Standard) Extension 1) Unusable Extension 2) Unusable 15 14 13 12 11 10 Code Flag – – – –...

  • Page 77: Call %Rb

    7 DETAILS OF INSTRUCTIONS call call.d %rb Function PC relative subroutine call sp ← sp - 4, A[sp] ← pc + 2, pc ← pc + 2 + rb Standard) Extension 1) Unusable Extension 2) Unusable 15 14 13 12 11 10 Code call call.d...

  • Page 78: Call Sign10

    7 DETAILS OF INSTRUCTIONS call sign10 call.d sign10 Function PC relative subroutine call sp ← sp - 4, A[sp] ← pc + 2, pc ← pc + 2 + sign10 × 2 Standard) Extension 1) sp ← sp - 4, A[sp] ← pc + 2, pc ← pc + 2 + sign24 Extension 2) Unusable 15 14 13 12 11 10 Code...

  • Page 79: Calla %Rb

    7 DETAILS OF INSTRUCTIONS calla calla.d %rb Function PC absolute subroutine call sp ← sp - 4, A[sp] ← pc + 2, pc ← rb Standard) Extension 1) Unusable Extension 2) Unusable 15 14 13 12 11 10 Code calla calla.d Flag –...

  • Page 80: Calla Imm7

    7 DETAILS OF INSTRUCTIONS calla imm7 calla.d imm7 Function PC absolute subroutine call sp ← sp - 4, A[sp] ← pc + 2, pc ← imm7 Standard) Extension 1) sp ← sp - 4, A[sp] ← pc + 2, pc ← imm20 Extension 2) sp ←...

  • Page 81: Cmc %Rd, %Rs

    7 DETAILS OF INSTRUCTIONS %rd, %rs cmc/c %rd, %rs cmc/nc %rd, %rs Function 16-bit comparison with carry Standard) rd(15:0) - rs(15:0) - C Extension 1) rs(15:0) - imm13(zero extended) - C Extension 2) rs(15:0) - imm16 - C 15 14 13 12 11 10 Code cmc/c cmc/nc...

  • Page 82: Cmc %Rd, Sign7

    7 DETAILS OF INSTRUCTIONS cmc %rd, sign7 Function 16-bit comparison with carry Standard) rd(15:0) - sign7(sign extended) - C Extension 1) rd(15:0) - sign16 - C Extension 2) Unusable 15 14 13 12 11 10 Code sign7 Flag – ↔ ↔ ↔ ↔ –...

  • Page 83: Cmp %Rd, %Rs

    7 DETAILS OF INSTRUCTIONS %rd, %rs cmp/c %rd, %rs cmp/nc %rd, %rs Function 16-bit comparison Standard) rd(15:0) - rs(15:0) Extension 1) rs(15:0) - imm13(zero extended) Extension 2) rs(15:0) - imm16 15 14 13 12 11 10 Code cmp/c cmp/nc Flag –...

  • Page 84: Cmp %Rd, Sign7

    7 DETAILS OF INSTRUCTIONS cmp %rd, sign7 Function 16-bit comparison Standard) rd(15:0) - sign7(sign extended) Extension 1) rd(15:0) - sign16 Extension 2) Unusable 15 14 13 12 11 10 Code sign7 Flag – ↔ ↔ ↔ ↔ – Mode Src:Immediate data (signed) Dst:Register direct %rd = %r0 to %r7 One cycle Description...

  • Page 85: Cmp.a %Rd, %Rs

    7 DETAILS OF INSTRUCTIONS cmp.a %rd, %rs cmp.a/c %rd, %rs cmp.a/nc %rd, %rs Function 24-bit comparison Standard) rd(23:0) - rs(23:0) Extension 1) rs(23:0) - imm13(zero extended) Extension 2) rs(23:0) - imm24 15 14 13 12 11 10 Code cmp.a cmp.a/c cmp.a/nc Flag –...

  • Page 86: Cmp.a %Rd, Imm7

    7 DETAILS OF INSTRUCTIONS cmp.a %rd, imm7 Function 24-bit comparison Standard) rd(23:0) - imm7(zero extended) Extension 1) rd(23:0) - imm20(zero extended) Extension 2) rd(23:0) - imm24 15 14 13 12 11 10 Code imm7 Flag – ↔ – ↔ – –...

  • Page 87: Cv.ab %Rd, %Rs

    7 DETAILS OF INSTRUCTIONS cv.ab %rd, %rs Function Data conversion from byte to 24 bits rd(23:8) ← rs(7), rd(7:0) ← rs(7:0) Standard) Extension 1) Unusable Extension 2) Unusable 15 14 13 12 11 10 Code Flag – – – – –...

  • Page 88: Cv.al %Rd, %Rs

    7 DETAILS OF INSTRUCTIONS cv.al %rd, %rs Function Data conversion from 32 bits to 24 bits rd(23:16) ← rs(7:0), rd(15:0) ← rd(15:0) Standard) Extension 1) Unusable Extension 2) Unusable 15 14 13 12 11 10 Code Flag – – – –...

  • Page 89: Cv.as %Rd, %Rs

    7 DETAILS OF INSTRUCTIONS cv.as %rd, %rs Function Data conversion from 16 bits to 24 bits rd(23:16) ← rs(15), rd(15:0) ← rs(15:0) Standard) Extension 1) Unusable Extension 2) Unusable 15 14 13 12 11 10 Code Flag – – – –...

  • Page 90: Cv.la %Rd, %Rs

    7 DETAILS OF INSTRUCTIONS cv.la %rd, %rs Function Data conversion from 24 bits to 32 bits rd(23:8) ← 0, rd(7:0) ← rs(23:16) Standard) Extension 1) Unusable Extension 2) Unusable 15 14 13 12 11 10 Code Flag – – – –...

  • Page 91: Cv.ls %Rd, %Rs

    7 DETAILS OF INSTRUCTIONS cv.ls %rd, %rs Function Data conversion from 16 bits to 32 bits rd(23:16) ← 0, rd(15:0) ← rs(15) Standard) Extension 1) Unusable Extension 2) Unusable 15 14 13 12 11 10 Code Flag – – – –...
  • Page 92 7 DETAILS OF INSTRUCTIONS Function Disable interrupts psr(IE) ← 0 Standard) Extension 1) Unusable Extension 2) Unusable 15 14 13 12 11 10 Code Flag – – – – – Mode – One cycle Description (1) Standard Resets the IE bit in the PSR to disable external maskable interrupts. The reset interrupt, address misaligned interrupt, and NMI will be accepted even if the IE bit is set to 0.
  • Page 93 7 DETAILS OF INSTRUCTIONS Function Enable interrupts psr(IE) ← 1 Standard) Extension 1) Unusable Extension 2) Unusable 15 14 13 12 11 10 Code Flag – – – – – Mode – One cycle Description (1) Standard Sets the IE bit in the PSR to enable external maskable interrupts. (2) Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the “d”...

  • Page 94: Ext Imm13

    7 DETAILS OF INSTRUCTIONS ext imm13 Function Immediate extension Standard) Extends the immediate data/operand of the following instruction Extension 1) Unusable Extension 2) Unusable 15 14 13 12 11 10 Code imm13 Flag – – – – – – Mode Immediate data (unsigned) One cycle Description...

  • Page 95: Halt

    7 DETAILS OF INSTRUCTIONS halt Function HALT Standard) Sets the processor to HALT mode Extension 1) Unusable Extension 2) Unusable 15 14 13 12 11 10 Code Flag – – – – – – Mode – Six cycles Description Sets the processor to HALT mode for power saving. Program execution is halted at the same time that the S1C17 Core executes the halt instruction, and the processor enters HALT mode.

  • Page 96: Int Imm5

    7 DETAILS OF INSTRUCTIONS int imm5 Function Software interrupt sp ← sp - 4, A[sp] ← {psr, pc + 2}, pc ← vector (vector No. = imm5) Standard) Extension 1) Unusable Extension 2) Unusable 15 14 13 12 11 10 Code imm5 Flag...

  • Page 97: Intl Imm5, Imm3

    7 DETAILS OF INSTRUCTIONS intl imm5, imm3 Function Software interrupt with interrupt level setting sp ← sp - 4, A[sp] ← {psr, pc + 2}, pc ← vector (vector No. = imm5), Standard) psr(IL) ← imm3 Extension 1) Unusable Extension 2) Unusable 15 14 13 12 11 10 Code imm3...

  • Page 98: Jpa %Rb

    7 DETAILS OF INSTRUCTIONS jpa.d %rb Function Unconditional PC absolute jump pc ← rb Standard) Extension 1) Unusable Extension 2) Unusable 15 14 13 12 11 10 Code jpa.d Flag – – – – – – Mode PC absolute Three cycles Two cycles jpa.d Description...

  • Page 99: Jpa Imm7

    7 DETAILS OF INSTRUCTIONS imm7 jpa.d imm7 Function Unconditional PC absolute jump pc ← imm7 Standard) Extension 1) pc ← imm20 Extension 2) pc ← imm24 15 14 13 12 11 10 Code imm7 imm7 jpa.d Flag – – – –...

  • Page 100: Jpr %Rb

    7 DETAILS OF INSTRUCTIONS jpr.d %rb Function Unconditional PC relative jump pc ← pc + 2 + rb Standard) Extension 1) Unusable Extension 2) Unusable 15 14 13 12 11 10 Code jpr.d Flag – – – – – – Mode Signed PC relative Three cycles...

  • Page 101: Jpr Sign10

    7 DETAILS OF INSTRUCTIONS sign10 jpr.d sign10 Function Unconditional PC relative jump pc ← pc + 2 + sign10 × 2 Standard) Extension 1) pc ← pc + 2 + sign24 Extension 2) Unusable 15 14 13 12 11 10 Code sign10 sign10...

  • Page 102: Jreq Sign7

    7 DETAILS OF INSTRUCTIONS jreq sign7 jreq.d sign7 Function Conditional PC relative jump pc ← pc + 2 + sign7 × 2 if Z is true Standard) Extension 1) pc ← pc + 2 + sign21 if Z is true Extension 2) pc ←...

  • Page 103: Jrge Sign7

    7 DETAILS OF INSTRUCTIONS jrge sign7 jrge.d sign7 Function Conditional PC relative jump (for judgment of signed operation results) pc ← pc + 2 + sign7 × 2 if !(N^V) is true Standard) Extension 1) pc ← pc + 2 + sign21 if !(N^V) is true Extension 2) pc ←...

  • Page 104: Jrgt Sign7

    7 DETAILS OF INSTRUCTIONS jrgt sign7 jrgt.d sign7 Function Conditional PC relative jump (for judgment of signed operation results) pc ← pc + 2 + sign7 × 2 if !Z&!(N^V) is true Standard) Extension 1) pc ← pc + 2 + sign21 if !Z&!(N^V) is true Extension 2) pc ←...

  • Page 105: Jrle Sign7

    7 DETAILS OF INSTRUCTIONS jrle sign7 jrle.d sign7 Function Conditional PC relative jump (for judgment of signed operation results) pc ← pc + 2 + sign7 × 2 if Z | (N^V) is true Standard) Extension 1) pc ← pc + 2 + sign21 if Z | (N^V) is true Extension 2) pc ←...

  • Page 106: Jrlt Sign7

    7 DETAILS OF INSTRUCTIONS jrlt sign7 jrlt.d sign7 Function Conditional PC relative jump (for judgment of signed operation results) pc ← pc + 2 + sign7 × 2 if N^V is true Standard) Extension 1) pc ← pc + 2 + sign21 if N^V is true Extension 2) pc ←...

  • Page 107: Sign7

    7 DETAILS OF INSTRUCTIONS jrne sign7 jrne.d sign7 Function Conditional PC relative jump pc ← pc + 2 + sign7 × 2 if !Z is true Standard) Extension 1) pc ← pc + 2 + sign21 if !Z is true Extension 2) pc ←...

  • Page 108: Jruge Sign7

    7 DETAILS OF INSTRUCTIONS jruge sign7 jruge.d sign7 Function Conditional PC relative jump (for judgment of unsigned operation results) pc ← pc + 2 + sign7 × 2 if !C is true Standard) Extension 1) pc ← pc + 2 + sign21 if !C is true Extension 2) pc ←...

  • Page 109: Jrugt Sign7

    7 DETAILS OF INSTRUCTIONS jrugt sign7 jrugt.d sign7 Function Conditional PC relative jump (for judgment of unsigned operation results) pc ← pc + 2 + sign7 × 2 if !Z&!C is true Standard) Extension 1) pc ← pc + 2 + sign21 if !Z&!C is true Extension 2) pc ←...

  • Page 110: Jrule Sign7

    7 DETAILS OF INSTRUCTIONS jrule sign7 jrule.d sign7 Function Conditional PC relative jump (for judgment of unsigned operation results) pc ← pc + 2 + sign7 × 2 if Z | C is true Standard) Extension 1) pc ← pc + 2 + sign21 if Z | C is true Extension 2) pc ←...

  • Page 111: Jrult Sign7

    7 DETAILS OF INSTRUCTIONS jrult sign7 jrult.d sign7 Function Conditional PC relative jump (for judgment of unsigned operation results) pc ← pc + 2 + sign7 × 2 if C is true Standard) Extension 1) pc ← pc + 2 + sign21 if C is true Extension 2) pc ←...

  • Page 112: Ld %Rd, %Rs

    7 DETAILS OF INSTRUCTIONS ld %rd, %rs Function 16-bit data transfer rd(15:0) ← rs(15:0), rd(23:16) ← 0 Standard) Extension 1) Unusable Extension 2) Unusable 15 14 13 12 11 10 Code Flag – – – – – – Mode Src:Register direct %rs = %r0 to %r7 Dst:Register direct %rd = %r0 to %r7 One cycle Description...

  • Page 113: Ld %Rd, [%Rb]

    7 DETAILS OF INSTRUCTIONS ld %rd, [%rb] ld %rd, [%rb]+ ld %rd, [%rb]- ld %rd, -[%rb] 16-bit data transfer Function ld %rd, [%rb] rd(15:0) ← W[rb], rd(23:16) ← 0 Standard) Extension 1) rd(15:0) ← W[rb + imm13], rd(23:16) ← 0 Extension 2) rd(15:0) ←...
  • Page 114 7 DETAILS OF INSTRUCTIONS (3) Extension 2 imm13 ; imm13(10:0) = imm24(23:13) imm13 ; = imm24(12:0) %rd,[%rb] ; memory address = rb + imm24 The addressing mode changes to register indirect addressing with displacement, so the content of the rb register with the 24-bit immediate imm24 added comprises the memory address, the 16-bit data in which is transferred to the rd register.

  • Page 115: Ld %Rd, [%Sp + Imm7]

    7 DETAILS OF INSTRUCTIONS ld %rd, [%sp + imm7] Function 16-bit data transfer rd(15:0) ← W[sp + imm7], rd(23:16) ← 0 Standard) Extension 1) rd(15:0) ← W[sp + imm20], rd(23:16) ← 0 Extension 2) rd(15:0) ← W[sp + imm24], rd(23:16) ← 0 15 14 13 12 11 10 Code imm7...

  • Page 116: Ld %Rd, [Imm7]

    7 DETAILS OF INSTRUCTIONS ld %rd, [imm7] Function 16-bit data transfer rd(15:0) ← W[imm7], rd(23:16) ← 0 Standard) Extension 1) rd(15:0) ← W[imm20], rd(23:16) ← 0 Extension 2) rd(15:0) ← W[imm24], rd(23:16) ← 0 15 14 13 12 11 10 Code imm7 Flag...

  • Page 117: Ld %Rd, Sign7

    7 DETAILS OF INSTRUCTIONS ld %rd, sign7 Function 16-bit data transfer rd(6:0) ← sign7(6:0), rd(15:7) ← sign7(6), rd(23:16) ← 0 Standard) Extension 1) rd(15:0) ← sign16(15:0), rd(23:16) ← 0 Extension 2) Unusable 15 14 13 12 11 10 Code sign7 Flag –...

  • Page 118: Ld [%Rb], %Rs

    7 DETAILS OF INSTRUCTIONS ld [%rb], %rs ld [%rb]+, %rs ld [%rb]-, %rs ld -[%rb], %rs 16-bit data transfer Function ld [%rb], %rs W[rb] ← rs(15:0) Standard) Extension 1) W[rb + imm13] ← rs(15:0) Extension 2) W[rb + imm24] ← rs(15:0) ld [%rb]+, %rs (with post-increment option) W[rb] ←...
  • Page 119 7 DETAILS OF INSTRUCTIONS (3) Extension 2 imm13 ; imm13(10:0) = imm24(23:13) imm13 ; = imm24(12:0) [%rb],%rs ; memory address = rb + imm24 The addressing mode changes to register indirect addressing with displacement, so the 16 low- order bits of the rs register are transferred to the address indicated by the content of the rb register with the 24-bit immediate imm24 added.

  • Page 120: Ld [%Sp + Imm7], %Rs

    7 DETAILS OF INSTRUCTIONS ld [%sp + imm7], %rs Function 16-bit data transfer W[sp + imm7] ← rs(15:0) Standard) Extension 1) W[sp + imm20] ← rs(15:0) Extension 2) W[sp + imm24] ← rs(15:0) 15 14 13 12 11 10 Code imm7 Flag –...

  • Page 121: Ld [Imm7], %Rs

    7 DETAILS OF INSTRUCTIONS ld [imm7], %rs Function 16-bit data transfer W[imm7] ← rs(15:0) Standard) Extension 1) W[imm20] ← rs(15:0) Extension 2) W[imm24] ← rs(15:0) 15 14 13 12 11 10 Code imm7 Flag – – – – – – Mode Src:Register direct %rs = %r0 to %r7 Dst:Immediate data (unsigned)

  • Page 122: Ld.a %Rd, %Pc

    7 DETAILS OF INSTRUCTIONS ld.a %rd, %pc Function 24-bit data transfer rd(23:0) ← pc(23:0) + 2 Standard) Extension 1) Unusable Extension 2) Unusable 15 14 13 12 11 10 Code Flag – – – – – – Mode Src:Register direct %pc Dst:Register direct %rd = %r0 to %r7 One cycle Description...

  • Page 123: Ld.a %Rd, %Rs

    7 DETAILS OF INSTRUCTIONS ld.a %rd, %rs Function 24-bit data transfer rd(23:0) ← rs(23:0) Standard) Extension 1) Unusable Extension 2) Unusable 15 14 13 12 11 10 Code Flag – – – – – – Mode Src:Register direct %rs = %r0 to %r7 Dst:Register direct %rd = %r0 to %r7 One cycle Description...

  • Page 124: Ld.a %Rd, %Sp

    7 DETAILS OF INSTRUCTIONS ld.a %rd, %sp Function 24-bit data transfer rd(23:2) ← sp(23:2), rd(1:0) ← 0 Standard) Extension 1) Unusable Extension 2) Unusable 15 14 13 12 11 10 Code Flag – – – – – – Mode Src:Register direct %sp Dst:Register direct %rd = %r0 to %r7 One cycle Description...

  • Page 125: Ld.a %Rd, [%Rb]

    7 DETAILS OF INSTRUCTIONS ld.a %rd, [%rb] ld.a %rd, [%rb]+ ld.a %rd, [%rb]- ld.a %rd, -[%rb] 32-bit data transfer Function ld.a %rd, [%rb] rd(23:0) ← A[rb](23:0), ignored ← A[rb](31:24) Standard) Extension 1) rd(23:0) ← A[rb + imm13](23:0), ignored ← A[rb + imm13](31:24) Extension 2) rd(23:0) ←...
  • Page 126 7 DETAILS OF INSTRUCTIONS (2) Extension 1 imm13 ld.a %rd,[%rb] ; memory address = rb + imm13 The e x t instruction changes the addressing mode to register indirect addressing with displacement. As a result, the content of the rb register with the 13-bit immediate imm13 added comprises the memory address, the 32-bit data (the eight high-order bits are ignored) in which is transferred to the rd register.

  • Page 127: Ld.a %Rd, [%Sp]

    7 DETAILS OF INSTRUCTIONS ld.a %rd, [%sp] ld.a %rd, [%sp]+ ld.a %rd, [%sp]- ld.a %rd, -[%sp] 32-bit data transfer Function ld.a %rd, [%sp] rd(23:0) ← A[sp](23:0), ignored ← A[sp](31:24) Standard) Extension 1) rd(23:0) ← A[sp + imm13](23:0), ignored ← A[sp + imm13](31:24) Extension 2) rd(23:0) ←...
  • Page 128 7 DETAILS OF INSTRUCTIONS (2) Extension 1 imm13 ld.a %rd,[%sp] ; memory address = sp + imm13 The e x t instruction changes the addressing mode to register indirect addressing with displacement. As a result, the content of the SP with the 13-bit immediate imm13 added comprises the memory address, the 32-bit data (the eight high-order bits are ignored) in which is transferred to the rd register.

  • Page 129: Ld.a %Rd, [%Sp + Imm7]

    7 DETAILS OF INSTRUCTIONS ld.a %rd, [%sp + imm7] Function 32-bit data transfer rd(23:0) ← A[sp + imm7](23:0), ignored ← A[sp + imm7](31:24) Standard) Extension 1) rd(23:0) ← A[sp + imm20](23:0), ignored ← A[sp + imm20](31:24) Extension 2) rd(23:0) ← A[sp + imm24](23:0), ignored ← A[sp + imm24](31:24) 15 14 13 12 11 10 Code imm7...

  • Page 130: Ld.a %Rd, [Imm7]

    7 DETAILS OF INSTRUCTIONS ld.a %rd, [imm7] Function 32-bit data transfer rd(23:0) ← A[imm7](23:0), ignored ← A[imm7](31:24) Standard) Extension 1) rd(23:0) ← A[imm20](23:0), ignored ← A[imm20](31:24) Extension 2) rd(23:0) ← A[imm24](23:0), ignored ← A[imm24](31:24) 15 14 13 12 11 10 Code imm7 Flag...

  • Page 131: Ld.a %Rd, Imm7

    7 DETAILS OF INSTRUCTIONS ld.a %rd, imm7 Function 24-bit data transfer rd(6:0) ← imm7, rd(23:7) ← 0 Standard) Extension 1) rd(19:0) ← imm20, rd(23:20) ← 0 Extension 2) rd(23:0) ← imm24 15 14 13 12 11 10 Code imm7 Flag –...

  • Page 132: Ld.a %Sp, %Rs

    7 DETAILS OF INSTRUCTIONS ld.a %sp, %rs Function 24-bit data transfer sp(23:2) ← rs(23:2) Standard) Extension 1) Unusable Extension 2) Unusable 15 14 13 12 11 10 Code Flag – – – – – – Mode Src:Register direct %rs = %r0 to %r7 Dst:Register direct %sp One cycle Description...

  • Page 133: Ld.a %Sp, Imm7

    7 DETAILS OF INSTRUCTIONS ld.a %sp, imm7 Function 24-bit data transfer sp(6:2) ← imm7(6:2), sp(23:7) ← 0 Standard) Extension 1) sp(19:2) ← imm20(19:2), sp(23:20) ← 0 Extension 2) sp(23:2) ← imm24(23:2) 15 14 13 12 11 10 Code imm7 Flag –...

  • Page 134: Ld.a [%Rb], %Rs

    7 DETAILS OF INSTRUCTIONS ld.a [%rb], %rs ld.a [%rb]+, %rs ld.a [%rb]-, %rs ld.a -[%rb], %rs 32-bit data transfer Function ld.a [%rb], %rs A[rb](23:0) ← rs(23:0), A[rb](31:24) ← 0 Standard) Extension 1) A[rb + imm13](23:0) ← rs(23:0), A[rb + imm13](31:24) ← 0 Extension 2) A[rb + imm24](23:0) ←...
  • Page 135 7 DETAILS OF INSTRUCTIONS (3) Extension 2 imm13 ; imm13(10:0) = imm24(23:13) imm13 ; = imm24(12:0) ld.a [%rb],%rs ; memory address = rb + imm24 The addressing mode changes to register indirect addressing with displacement, so the content of the rs register is transferred to the address indicated by the content of the rb register with the 24-bit immediate imm24 added.

  • Page 136: Ld.a [%Sp], %Rs

    7 DETAILS OF INSTRUCTIONS ld.a [%sp], %rs ld.a [%sp]+, %rs ld.a [%sp]-, %rs ld.a -[%sp], %rs 32-bit data transfer Function ld.a [%sp], %rs A[sp](23:0) ← rs(23:0), A[sp](31:24) ← 0 Standard) Extension 1) A[sp + imm13](23:0) ← rs(23:0), A[sp + imm13](31:24) ← 0 Extension 2) A[sp + imm24](23:0) ←...
  • Page 137 7 DETAILS OF INSTRUCTIONS (3) Extension 2 imm13 ; imm13(10:0) = imm24(23:13) imm13 ; = imm24(12:0) ld.a [%sp],%rs ; memory address = sp + imm24 The addressing mode changes to register indirect addressing with displacement, so the content of the rs register is transferred to the address indicated by the content of the SP with the 24-bit immediate imm24 added.

  • Page 138: Ld.a [%Sp + Imm7], %Rs

    7 DETAILS OF INSTRUCTIONS ld.a [%sp + imm7], %rs Function 32-bit data transfer A[sp + imm7](23:0) ← rs(23:0), A[sp + imm7](31:24) ← 0 Standard) Extension 1) A[sp + imm20](23:0) ← rs(23:0), A[sp + imm20](31:24) ← 0 Extension 2) A[sp + imm24](23:0) ← rs(23:0), A[sp + imm24](31:24) ← 0 15 14 13 12 11 10 Code imm7...

  • Page 139: Ld.a [Imm7], %Rs

    7 DETAILS OF INSTRUCTIONS ld.a [imm7], %rs Function 32-bit data transfer A[imm7](23:0) ← rs(23:0), A[imm7](31:24) ← 0 Standard) Extension 1) A[imm20](23:0) ← rs(23:0), A[imm20](31:24) ← 0 Extension 2) A[imm24](23:0) ← rs(23:0), A[imm24](31:24) ← 0 15 14 13 12 11 10 Code imm7 Flag...

  • Page 140: Ld.b %Rd, %Rs

    7 DETAILS OF INSTRUCTIONS ld.b %rd, %rs Function Signed byte data transfer rd(7:0) ← rs(7:0), rd(15:8) ← rs(7), rd(23:16) ← 0 Standard) Extension 1) Unusable Extension 2) Unusable 15 14 13 12 11 10 Code Flag – – – – –...

  • Page 141: Ld.b %Rd, [%Rb]

    7 DETAILS OF INSTRUCTIONS ld.b %rd, [%rb] ld.b %rd, [%rb]+ ld.b %rd, [%rb]- ld.b %rd, -[%rb] Signed byte data transfer Function ld.b %rd, [%rb] rd(7:0) ← B[rb], rd(15:8) ← B[rb](7), rd(23:16) ← 0 Standard) Extension 1) rd(7:0) ← B[rb + imm13], rd(15:8) ← B[rb + imm13](7), rd(24:16) ← 0 Extension 2) rd(7:0) ←...

  • Page 142: Ld.b %Rd, [%Rb]

    7 DETAILS OF INSTRUCTIONS (2) Extension 1 imm13 ld.b %rd,[%rb] ; memory address = rb + imm13 The e x t instruction changes the addressing mode to register indirect addressing with displacement. As a result, the content of the rb register with the 13-bit immediate imm13 added comprises the memory address, the byte data in which is transferred to the rd register after being sign-extended to 16 bits.

  • Page 143: Ld.b %Rd, [%Sp + Imm7]

    7 DETAILS OF INSTRUCTIONS ld.b %rd, [%sp + imm7] Function Signed byte data transfer rd(7:0) ← B[sp + imm7], rd(15:8) ← B[sp + imm7](7), rd(23:16) ← 0 Standard) Extension 1) rd(7:0) ← B[sp + imm20], rd(15:8) ← B[sp + imm20](7), rd(23:16) ← 0 Extension 2) rd(7:0) ←...

  • Page 144: Ld.b %Rd, [Imm7]

    7 DETAILS OF INSTRUCTIONS ld.b %rd, [imm7] Function Signed byte data transfer rd(7:0) ← B[imm7], rd(15:8) ← B[imm7](7), rd(23:16) ← 0 Standard) Extension 1) rd(7:0) ← B[imm20], rd(15:8) ← B[imm20](7), rd(23:16) ← 0 Extension 2) rd(7:0) ← B[imm24], rd(15:8) ← B[imm24](7), rd(23:16) ← 0 15 14 13 12 11 10 Code imm7...

  • Page 145: Ld.b [%Rb], %Rs

    7 DETAILS OF INSTRUCTIONS ld.b [%rb], %rs ld.b [%rb]+, %rs ld.b [%rb]-, %rs ld.b -[%rb], %rs Signed byte data transfer Function ld.b [%rb], %rs B[rb] ← rs(7:0) Standard) Extension 1) B[rb + imm13] ← rs(7:0) Extension 2) B[rb + imm24] ← rs(7:0) ld.b [%rb]+, %rs (with post-increment option) B[rb] ←...
  • Page 146 7 DETAILS OF INSTRUCTIONS (3) Extension 2 imm13 ; = imm24(23:13) imm13 ; = imm24(12:0) ld.b [%rb],%rs ; memory address = rb + imm24 The addressing mode changes to register indirect addressing with displacement, so the eight low-order bits of the rs register are transferred to the address indicated by the content of the rb register with the 24-bit immediate imm24 added.

  • Page 147: Ld.b [%Sp + Imm7], %Rs

    7 DETAILS OF INSTRUCTIONS ld.b [%sp + imm7], %rs Function Signed byte data transfer B[sp + imm7] ← rs(7:0) Standard) Extension 1) B[sp + imm20] ← rs(7:0) Extension 2) B[sp + imm24] ← rs(7:0) 15 14 13 12 11 10 Code imm7 Flag...

  • Page 148: Ld.b [Imm7], %Rs

    7 DETAILS OF INSTRUCTIONS ld.b [imm7], %rs Function Signed byte data transfer B[imm7] ← rs(7:0) Standard) Extension 1) B[imm20] ← rs(7:0) Extension 2) B[imm24] ← rs(7:0) 15 14 13 12 11 10 Code imm7 Flag – – – – – –...

  • Page 149: Ld.ca %Rd, %Rs

    7 DETAILS OF INSTRUCTIONS ld.ca %rd, %rs Function Transfer data to the coprocessor and get the results co_dout0 ← rd, co_dout1 ← rs, rd ← co_din, psr(C, V, Z, N) ← co_cvzn Standard) Extension 1) Unusable Extension 2) Unusable 15 14 13 12 11 10 Code Flag –...

  • Page 150: Ld.ca %Rd, Imm7

    7 DETAILS OF INSTRUCTIONS ld.ca %rd, imm7 Function Transfer data to the coprocessor and get the results co_dout0 ← rd, co_dout1 ← imm7, rd ← co_din, psr(C, V, Z, N) ← co_cvzn Standard) Extension 1) co_dout0 ← rd, co_dout1 ← imm20, rd ← co_din, psr(C, V, Z, N) ← co_cvzn Extension 2) co_dout0 ←...

  • Page 151: Ld.cf %Rd, %Rs

    7 DETAILS OF INSTRUCTIONS ld.cf %rd, %rs Function Transfer data to the coprocessor and get the flag status co_dout0 ← rd, co_dout1 ← rs, psr(C, V, Z, N) ← co_cvzn Standard) Extension 1) Unusable Extension 2) Unusable 15 14 13 12 11 10 Code Flag –...

  • Page 152: Ld.cf %Rd, Imm7

    7 DETAILS OF INSTRUCTIONS ld.cf %rd, imm7 Function Transfer data to the coprocessor and get the flag status co_dout0 ← rd, co_dout1 ← imm7, psr(C, V, Z, N) ← co_cvzn Standard) Extension 1) co_dout0 ← rd, co_dout1 ← imm20, psr(C, V, Z, N) ← co_cvzn Extension 2) co_dout0 ←...

  • Page 153: Ld.cw %Rd, %Rs

    7 DETAILS OF INSTRUCTIONS ld.cw %rd, %rs Function Transfer data to the coprocessor co_dout0 ← rd, co_dout1 ← rs Standard) Extension 1) Unusable Extension 2) Unusable 15 14 13 12 11 10 Code Flag – – – – – – Mode Src:Register direct %rs = %r0 to %r7 Dst:Register direct %rd = %r0 to %r7...

  • Page 154: Ld.cw %Rd, Imm7

    7 DETAILS OF INSTRUCTIONS ld.cw %rd, imm7 Function Transfer data to the coprocessor co_dout0 ← rd, co_dout1 ← imm7 Standard) Extension 1) co_dout0 ← rd, co_dout1 ← imm20 Extension 2) co_dout0 ← rd, co_dout1 ← imm24 15 14 13 12 11 10 Code imm7 Flag...

  • Page 155: Ld.ub %Rd, %Rs

    7 DETAILS OF INSTRUCTIONS ld.ub %rd, %rs Function Unsigned byte data transfer rd(7:0) ← rs(7:0), rd(15:8) ← 0, rd(23:16) ← 0 Standard) Extension 1) Unusable Extension 2) Unusable 15 14 13 12 11 10 Code Flag – – – – –...

  • Page 156: Ld.ub %Rd, [%Rb]

    7 DETAILS OF INSTRUCTIONS ld.ub %rd, [%rb] ld.ub %rd, [%rb]+ ld.ub %rd, [%rb]- ld.ub %rd, -[%rb] Unsigned byte data transfer Function ld.ub %rd, [%rb] rd(7:0) ← B[rb], rd(15:8) ← 0, rd(23:16) ← 0 Standard) Extension 1) rd(7:0) ← B[rb + imm13], rd(15:8) ← 0, rd(24:16) ← 0 Extension 2) rd(7:0) ←...
  • Page 157 7 DETAILS OF INSTRUCTIONS (3) Extension 2 imm13 ; imm13(10:0) = imm24(23:13) imm13 ; = imm24(12:0) ld.ub %rd,[%rb] ; memory address = rb + imm24 The addressing mode changes to register indirect addressing with displacement, so the content of the rb register with the 24-bit immediate imm24 added comprises the memory address, the byte data in which is transferred to the rd register after being zero-extended to 16 bits.

  • Page 158: Ld.ub %Rd, [%Sp + Imm7]

    7 DETAILS OF INSTRUCTIONS ld.ub %rd, [%sp + imm7] Function Unsigned byte data transfer rd(7:0) ← B[sp + imm7], rd(15:8) ← 0, rd(23:16) ← 0 Standard) Extension 1) rd(7:0) ← B[sp + imm20], rd(15:8) ← 0, rd(23:16) ← 0 Extension 2) rd(7:0) ← B[sp + imm24], rd(15:8) ← 0, rd(23:16) ← 0 15 14 13 12 11 10 Code imm7...

  • Page 159: Ld.ub %Rd, [Imm7]

    7 DETAILS OF INSTRUCTIONS ld.ub %rd, [imm7] Function Unsigned byte data transfer rd(7:0) ← B[imm7], rd(15:8) ← 0, rd(23:16) ← 0 Standard) Extension 1) rd(7:0) ← B[imm20], rd(15:8) ← 0, rd(23:16) ← 0 Extension 2) rd(7:0) ← B[imm24], rd(15:8) ← 0, rd(23:16) ← 0 15 14 13 12 11 10 Code imm7...

  • Page 160: Nop

    7 DETAILS OF INSTRUCTIONS Function No operation Standard) No operation Extension 1) Unusable Extension 2) Unusable 15 14 13 12 11 10 Code Flag – – – – – – Mode – One cycle Description (1) Standard The nop instruction just takes one cycle and no operation results. The PC is incremented (+2). (2) Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the “d”...

  • Page 161: Not %Rd, %Rs

    7 DETAILS OF INSTRUCTIONS %rd, %rs not/c %rd, %rs not/nc %rd, %rs Function 16-bit logical negation rd(15:0) ← !rs(15:0), rd(23:16) ← 0 Standard) Extension 1) rd(15:0) ← !imm13(zero extended), rd(23:16) ← 0 Extension 2) rd(15:0) ← !imm16, rd(23:16) ← 0 15 14 13 12 11 10 Code not/c...

  • Page 162: Not %Rd, Sign7

    7 DETAILS OF INSTRUCTIONS not %rd, sign7 Function 16-bit logical negation rd(15:0) ← !sign7(sign extended), rd(23:16) ← 0 Standard) Extension 1) rd(15:0) ← !sign16, rd(23:16) ← 0 Extension 2) Unusable 15 14 13 12 11 10 Code sign7 Flag 0 ↔ ↔ –...

  • Page 163: Or %Rd, %Rs

    7 DETAILS OF INSTRUCTIONS %rd, %rs or/c %rd, %rs or/nc %rd, %rs Function 16-bit logical OR rd(15:0) ← rd(15:0) | rs(15:0), rd(23:16) ← 0 Standard) Extension 1) rd(15:0) ← rs(15:0) | imm13(zero extended), rd(23:16) ← 0 Extension 2) rd(15:0) ← rs(15:0) | imm16, rd(23:16) ← 0 15 14 13 12 11 10 Code or/c...

  • Page 164: Or %Rd, Sign7

    7 DETAILS OF INSTRUCTIONS or %rd, sign7 Function 16-bit logical OR rd(15:0) ← rd(15:0) | sign7(sign extended), rd(23:16) ← 0 Standard) Extension 1) rd(15:0) ← rd(15:0) | sign16, rd(23:16) ← 0 Extension 2) Unusable 15 14 13 12 11 10 Code sign7 Flag...

  • Page 165: Ret

    7 DETAILS OF INSTRUCTIONS ret.d Function Return from subroutine pc ← A[sp](23:0), sp ← sp + 4 Standard) Extension 1) Unusable Extension 2) Unusable 15 14 13 12 11 10 Code ret.d Flag – – – – – Mode – Three cycles Two cycles ret.d...

  • Page 166: Retd

    7 DETAILS OF INSTRUCTIONS retd Function Return from a debug-interrupt handler routine r0 ← A[DBRAM + 0x4](23:0), {psr, pc} ← A[DBRAM + 0x0] Standard) Extension 1) Unusable Extension 2) Unusable 15 14 13 12 11 10 Code Flag ↔ ↔ ↔ ↔ ↔ ↔ Mode –...

  • Page 167: Reti

    7 DETAILS OF INSTRUCTIONS reti reti.d Function Return from trap handler routine {psr, pc} ← A[sp], sp ← sp + 4 Standard) Extension 1) Unusable Extension 2) Unusable 15 14 13 12 11 10 Code reti reti.d Flag ↔ ↔ ↔ ↔ ↔ ↔ Mode –...

  • Page 168: Sa %Rd, %Rs

    7 DETAILS OF INSTRUCTIONS sa %rd, %rs Function Arithmetic shift to the right Standard) Shift the content of rd to right as many bits as specified by rs (0–3, 4, or 8 bits), MSB ← MSB (sign bit) Extension 1) Unusable Extension 2) Unusable 15 14 13 12 11 10 Code...

  • Page 169: Sa %Rd, Imm7

    7 DETAILS OF INSTRUCTIONS sa %rd, imm7 Function Arithmetic shift to the right Standard) Shift the content of rd to right as many bits as specified by imm7 (0–3, 4, or 8 bits), MSB ← MSB (sign bit) Extension 1) imm7 is extended to imm20 Extension 2) imm7 is extended to imm24 15 14 13 12 11 10 Code...

  • Page 170: Sbc %Rd, %Rs

    7 DETAILS OF INSTRUCTIONS %rd, %rs sbc/c %rd, %rs sbc/nc %rd, %rs Function 16-bit subtraction with borrow rd(15:0) ← rd(15:0) - rs(15:0) - C, rd(23:16) ← 0 Standard) Extension 1) rd(15:0) ← rs(15:0) - imm13(zero extended) - C, rd(23:16) ← 0 Extension 2) rd(15:0) ←...

  • Page 171: Sbc %Rd, Imm7

    7 DETAILS OF INSTRUCTIONS sbc %rd, imm7 Function 16-bit subtraction with borrow rd(15:0) ← rd(15:0) - imm7(zero extended) - C, rd(23:16) ← 0 Standard) Extension 1) rd(15:0) ← rd(15:0) - imm16 - C, rd(23:16) ← 0 Extension 2) Unusable 15 14 13 12 11 10 Code imm7 Flag...

  • Page 172: Sl %Rd, %Rs

    7 DETAILS OF INSTRUCTIONS sl %rd, %rs Function Logical shift to the left Standard) Shift the content of rd to left as many bits as specified by rs (0–3, 4, or 8 bits), LSB ← 0 Extension 1) Unusable Extension 2) Unusable 15 14 13 12 11 10 Code Flag...

  • Page 173: Sl %Rd, Imm7

    7 DETAILS OF INSTRUCTIONS sl %rd, imm7 Function Logical shift to the left Standard) Shift the content of rd to left as many bits as specified by imm7 (0–3, 4, or 8 bits), LSB ← 0 Extension 1) imm7 is extended to imm20 Extension 2) imm7 is extended to imm24 15 14 13 12 11 10 Code...

  • Page 174: Slp

    7 DETAILS OF INSTRUCTIONS Function SLEEP Standard) Place the processor in SLEEP mode Extension 1) Unusable Extension 2) Unusable 15 14 13 12 11 10 Code Flag – – – – – – Mode – Six cycles Description Places the processor in SLEEP mode for power saving. Program execution is halted at the same time that the S1C17 Core executes the slp instruction, and the processor enters SLEEP mode.

  • Page 175: Sr %Rd, %Rs

    7 DETAILS OF INSTRUCTIONS sr %rd, %rs Function Logical shift to the right Standard) Shift the content of rd to right as many bits as specified by rs (0–3, 4, or 8 bits), MSB ← 0 Extension 1) Unusable Extension 2) Unusable 15 14 13 12 11 10 Code Flag...

  • Page 176: Sr %Rd, Imm7

    7 DETAILS OF INSTRUCTIONS sr %rd, imm7 Function Logical shift to the right Standard) Shift the content of rd to right as many bits as specified by imm7 (0–3, 4, or 8 bits), MSB ← 0 Extension 1) imm7 is extended to imm20 Extension 2) imm7 is extended to imm24 15 14 13 12 11 10 Code...

  • Page 177: Sub %Rd, %Rs

    7 DETAILS OF INSTRUCTIONS %rd, %rs sub/c %rd, %rs sub/nc %rd, %rs Function 16-bit subtraction rd(15:0) ← rd(15:0) - rs(15:0), rd(23:16) ← 0 Standard) Extension 1) rd(15:0) ← rs(15:0) - imm13(zero extended), rd(23:16) ← 0 Extension 2) rd(15:0) ← rs(15:0) - imm16, rd(23:16) ← 0 15 14 13 12 11 10 Code sub/c...

  • Page 178: Sub %Rd, Imm7

    7 DETAILS OF INSTRUCTIONS sub %rd, imm7 Function 16-bit subtraction rd(15:0) ← rd(15:0) - imm7(zero extended), rd(23:16) ← 0 Standard) Extension 1) rd(15:0) ← rd(15:0) - imm16, rd(23:16) ← 0 Extension 2) Unusable 15 14 13 12 11 10 Code imm7 Flag –...

  • Page 179: Sub.a %Rd, %Rs

    7 DETAILS OF INSTRUCTIONS sub.a %rd, %rs sub.a/c %rd, %rs sub.a/nc %rd, %rs Function 24-bit subtraction rd(23:0) ← rd(23:0) - rs(23:0) Standard) Extension 1) rd(23:0) ← rs(23:0) - imm13(zero extended) Extension 2) rd(23:0) ← rs(23:0) - imm24 15 14 13 12 11 10 Code sub.a sub.a/c...

  • Page 180: Sub.a %Rd, Imm7

    7 DETAILS OF INSTRUCTIONS sub.a %rd, imm7 Function 24-bit subtraction rd(23:0) ← rd(23:0) - imm7(zero extended) Standard) Extension 1) rd(23:0) ← rd(23:0) - imm20(zero extended) Extension 2) rd(23:0) ← rd(23:0) - imm24 15 14 13 12 11 10 Code imm7 Flag –...

  • Page 181: Sub.a %Sp, %Rs

    7 DETAILS OF INSTRUCTIONS sub.a %sp, %rs Function 24-bit subtraction sp(23:0) ← sp(23:0) - rs(23:0) Standard) Extension 1) sp(23:0) ← rs(23:0) - imm13(zero extended) Extension 2) sp(23:0) ← rs(23:0) - imm24 15 14 13 12 11 10 Code Flag – –...

  • Page 182: Sub.a %Sp, Imm7

    7 DETAILS OF INSTRUCTIONS sub.a %sp, imm7 Function 24-bit subtraction sp(23:0) ← sp(23:0) - imm7(zero extended) Standard) Extension 1) sp(23:0) ← sp(23:0) - imm20(zero extended) Extension 2) sp(23:0) ← sp(23:0) - imm24 15 14 13 12 11 10 Code imm7 Flag –...

  • Page 183: Swap %Rd, %Rs

    7 DETAILS OF INSTRUCTIONS swap %rd, %rs Function Swap rd(15:8) ← rs(7:0), rd(7:0) ← rs(15:8), rd(23:16) ← 0 Standard) Extension 1) Unusable Extension 2) Unusable 15 14 13 12 11 10 Code Flag – – – – – – Mode Src:Register direct %rs = %r0 to %r7 Dst:Register direct %rd = %r0 to %r7 One cycle...

  • Page 184: Xor %Rd, %Rs

    7 DETAILS OF INSTRUCTIONS %rd, %rs xor/c %rd, %rs xor/nc %rd, %rs Function 16-bit exclusive OR rd(15:0) ← rd(15:0) ^ rs(15:0), rd(23:16) ← 0 Standard) Extension 1) rd(15:0) ← rs(15:0) ^ imm13(zero extended), rd(23:16) ← 0 Extension 2) rd(15:0) ← rs(15:0) ^ imm16, rd(23:16) ← 0 15 14 13 12 11 10 Code xor/c...

  • Page 185: Xor %Rd, Sign7

    7 DETAILS OF INSTRUCTIONS xor %rd, sign7 Function 16-bit exclusive OR rd(15:0) ← rd(15:0) ^ sign7(sign extended), rd(23:16) ← 0 Standard) Extension 1) rd(15:0) ← rd(15:0) ^ sign16, rd(23:16) ← 0 Extension 2) Unusable 15 14 13 12 11 10 Code sign7 Flag...
  • Page 186 7 DETAILS OF INSTRUCTIONS THIS PAGE IS BLANK. EPSON 7-122 S1C17 FAMILY S1C17 CORE MANUAL...
  • Page 187 Appendix List of S1C17 Core Instructions Symbols in the Instruction List S1C17 Core Instruction Set Registers/Register Data Flags %rd, rd: A general-purpose register (R0–R7) used as the destination register or its contents Interrupt level %rs, rs: A general-purpose register (R0–R7) used as the source register or its contents Interrupt enable flag %rb, rb: A general-purpose register (R0–R7) that has stored a base address to be accessed in...
  • Page 188 Data Transfer Instructions (1) S1C17 Core Instruction Set Mnemonic Flags Code Function Cycle Opcode Operand ld.b %rd, %rs rd(7:0)←rs(7:0), rd(15:8)←rs(7), rd(23:16)←0 – – – – – – – ∗7 ∗1 %rd, [%rb] rd(7:0)←B[rb], rd(15:8)←B[rb](7), rd(23:16)←0 1, 2 – – – –...
  • Page 189 Data Transfer Instructions (2) S1C17 Core Instruction Set Mnemonic Flags Code Function Cycle Opcode Operand ∗5 [%sp+imm7], %rs imm7 W[sp+imm7]←rs(15:0) – – – – – – ∗4 [imm7], %rs imm7 W[imm7]←rs(15:0) – – – – – – ld.a %rd, %rs rd(23:0)←rs(23:0) –...
  • Page 190 Integer Arithmetic Operation Instructions (1) S1C17 Core Instruction Set Mnemonic Flags Code Function Cycle Opcode Operand %rd, %rs rd(15:0)←rd(15:0)+rs(15:0), rd(23:16)←0 – – ↔ ↔ ↔ ↔ ∗1 ↔ ↔ ↔ ∗1 add/c %rd, %rs rd(15:0)←rd(15:0)+rs(15:0), rd(23:16)←0 if C = 1 (nop if C = 0) –...
  • Page 191 Integer Arithmetic Operation Instructions (2) S1C17 Core Instruction Set Mnemonic Flags Code Function Cycle Opcode Operand ↔ ↔ ∗2 cmp.a %rd, %rs rd(23:0)-rs(23:0) – – – – ↔ ∗2 cmp.a/c %rd, %rs rd(23:0)-rs(23:0) if C = 1 (nop if C = 0) –...
  • Page 192 Branch Instructions S1C17 Core Instruction Set Mnemonic Flags Code Function Cycle Opcode Operand jpr / jpr.d sign10 sign10 pc←pc+2+sign11; sign11={sign10,0} (∗3) – – – – – – ∗4 – pc←pc+2+rb (∗3) 2(.d) – – – – – – – – ∗2 jpa / jpa.d imm7...
  • Page 193 Shift and Swap Instructions S1C17 Core Instruction Set Mnemonic Flags Code Function Cycle Opcode Operand ↔ ↔ ↔ %rd, %rs Logical shift to right; rd(15:0)←rd(15:0)>>rs(15:0), rd(23:16)←0, zero enters to MSB (∗1) – – – – ↔ ↔ ↔ ∗2 %rd, imm7 imm7 Logical shift to right;...
  • Page 194 Coprocessor Interface Instructions S1C17 Core Instruction Set Mnemonic Flags Code Function Cycle Opcode Operand ld.cw %rd, %rs co_dout0←rd, co_dout1←rs – – – – – – – ∗1 %rd, imm7 imm7 co_dout0←rd, co_dout1←imm7 – – – – – – ↔ ↔ ↔...
  • Page 195 Z.A. de Courtaboeuf 2, F-91976 Les Ulis Cedex, FRANCE Phone: +65-6586-5500 Fax: +65-6271-3182 Phone: +33-1-64862350 Fax: +33-1-64862355 SEIKO EPSON CORPORATION UK & IRELAND BRANCH OFFICE KOREA OFFICE 8 The Square, Stockley Park, Uxbridge Middx UB11 1FW, UNITED KINGDOM 50F, KLI 63 Bldg., 60 Yoido-dong...
  • Page 196 S1C17 Family S1C17 Core Manual SEMICONDUCTOR OPERATIONS DIVISION EPSON Electronic Devices Website http://www.epson.jp/device/semicon_e Document code: 410905900 Issue April, 2007 Printed in Japan...

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