Pioneer PD-30-K Service Manual page 23

5
• Pin Function
Symbol Type
CLK Input
CKE Input
BA0, BA1 Input
A0 - A11 Input
CS# Input
RAS# Input
CAS# Input
WE# Input
LDQM, UDQM Input
DQ0 - DQ15 Input/
Output
NC/RFU –
V Supply
DDQ
V Supply
SSQ
V Supply
DD
V Supply
SS
5
6
Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of
CLK. CLK also increments the internal burst counter and controls the output registers.
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. If CKE goes low
synchronously with clock (set-up and hold time same as other inputs), the internal clock is suspended
from the next clock cycle and the state of output and burst address is frozen as long as the CKE remains
low. When all banks are in the idle state, deactivating the clock controls the entry to the Power Down and
Self Refresh modes. CKE is synchronous except after the device enters Power Down and Self Refresh
modes, where CKE becomes asynchronous until exiting the same mode. The input buffers, including CLK,
are disabled during Power Down and Self Refresh modes, providing low standby power.
Bank Activate: BA0, BA1 input select the bank for operation.
BA1
0
0
1
1
Address Inputs: A0-A11 are sampled during the BankActivate command (row address A0-A11) and
Read/Write command (column address A0-A7 with A10 defining Auto Precharge) to select one location
out of the 2M available in the respective bank. During a Precharge command, A10 is sampled to
determine if all banks are to be precharged (A10 = HIGH). The address inputs also provide the op-code
during a Mode Register Set command.
Chip Select: CS# enables (sampled LOW) and disables (sampled HIGH) the command decoder. All
commands are masked when CS# is sampled HIGH. CS# provides for external bank selection on
systems with multiple banks. It is considered part of the command code.
Row Address Strobe: The RAS# signal defines the operation commands in conjunction with the CAS#
and WE# signals and is latched at the positive edges of CLK. When RAS# and CS# are asserted "LOW"
and CAS# is asserted "HIGH," either the BankActivate command or the Precharge command is selected
by the WE# signal. When the WE# is asserted "HIGH," the BankActivate command is selected and the
bank designated by BA is turned on to the active state. When the WE# is asserted "LOW," the Precharge
command is selected and the bank designated by BA is switched to the idle state after the precharge
operation.
Column Address Strobe: The CAS# signal defines the operation commands in conjunction with the
RAS# and WE# signals and is latched at the positive edges of CLK. When RAS# is held "HIGH" and CS#
is asserted "LOW," the column access is started by asserting CAS# "LOW." Then, the Read or Write
command is selected by asserting WE# "LOW" or "HIGH."
Write Enable: The WE# signal defines the operation commands in conjunction with the RAS# and CAS#
signals and is latched at the positive edges of CLK. The WE# input is used to select the BankActivate or
Precharge command and Read or Write command.
Data Input/Output Mask: Controls output buffers in read mode and masks Input data in write mode.
Data I/O: The DQ0-15 input and output data are synchronized with the positive edges of CLK. The I/Os
are maskable during Reads and Writes.
No Connect: These pins should be left unconnected.
DQ Power: Provide isolated power to DQs for improved noise immunity. (3.3 V ± 0.3 V)
DQ Ground: Provide isolated ground to DQs for improved noise immunity. (0 V)
Power Supply: +3.3 V ± 0.3 V
Ground
PD-30-K
6
7
Description
BA0 Select Bank
0 BANK #A
1 BANK #B
0 BANK #C
1 BANK #D
7
8
A
B
C
D
E
F
23
8