Winbond Spiflash W25Q80BV Manual
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Winbond Spiflash W25Q80BV Manual

8m-bit serial flash memory with dual and quad spi
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W25Q80BV
8M-BIT
SERIAL FLASH MEMORY WITH
DUAL AND QUAD SPI
Publication Release Date: Augest 01, 2012
- 1 -
Revision G

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Summary of Contents for Winbond Spiflash W25Q80BV

  • Page 1 W25Q80BV 8M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI Publication Release Date: Augest 01, 2012 - 1 - Revision G...

  • Page 2: Table Of Contents

    W25Q80BV Table of Contents GENERAL DESCRIPTION ....................... 5 FEATURES ............................5 PACKAGE TYPES AND PIN CONFIGURATIONS ................6 Pin Configuration SOIC / VSOP 150 / 208-mil ..............6 Pad Configuration WSON 6x5-mm / USON 2x3-mm ............6 Pin Configuration PDIP 300-mil .................... 7 Pin Description SOIC, VSOP, WSON, USON &...
  • Page 3 W25Q80BV 7.1.12 Status Register Memory Protection (CMP = 1) ..............17 INSTRUCTIONS ......................... 18 7.2.1 Manufacturer and Device Identification ................. 18 7.2.2 Instruction Set Table 1 (Erase, Program Instructions) ............19 7.2.3 Instruction Set Table 2 (Read Instructions) ................20 7.2.4 Instruction Set Table 3 (ID, Security Instructions) ..............
  • Page 4 W25Q80BV Absolute Maximum Ratings ....................60 Operating Ranges ......................60 Power-up Timing and Write Inhibit Threshold ..............61 DC Electrical Characteristics ....................62 AC Measurement Conditions ..................... 63 AC Electrical Characteristics ....................64 AC Electrical Characteristics (cont’d) ................. 65 Serial Output Timing ......................66 Serial Input Timing ......................

  • Page 5: General Description

    – Outperforms X16 Parallel Flash – 24-ball TFBGA 8x6-mm (6x4/5x5 ball array)  Low Power, Wide Temperature Range – Contact Winbond for KGD and other options – Single 2.7 to 3.6V supply – 4mA active current, <1µA Power-down current Note 1. More than 100,000 Block Erase/Program cycles for Industrial and Automotive temperature; more than 10,000 full chip Erase/Program cycles tested in compliance with AEC-Q100.

  • Page 6: Package Types And Pin Configurations

    W25Q80BV 2. Some package types are special orders, please contact Winbond for ordering information. 3. PACKAGE TYPES AND PIN CONFIGURATIONS W25Q80BV is offered in an 8-pin SOIC 150-mil or 208-mil (package code SN & SS), an 8-pin VSOP 150- mil or 208-mil (package code SV & ST), an 8-pad WSON 6x5-mm (package code ZP), an 8-pad USON 2x3-mm (package code UX), an 8-pin PDIP 300-mil (package code DA) and a 24-ball 8x6-mm TFBGA (5x5 ball array - package code TB, 6x4 ball array –...

  • Page 7: Pin Configuration Pdip 300-Mil

    W25Q80BV Pin Configuration PDIP 300-mil Top View DO (IO /HOLD (IO /WP (IO DI (IO Figure 1c. W25Q80BV Pin Assignments, 8-pin PDIP (Package Code DA) Pin Description SOIC, VSOP, WSON, USON & PDIP 300-mil PIN NO. PIN NAME FUNCTION Chip Select Input DO (IO1) Data Output (Data Input Output 1)* /WP (IO2)

  • Page 8: Ball Configuration Tfbga 8X6-Mm

    W25Q80BV Ball Configuration TFBGA 8x6-mm Top View Top View /WP (IO /WP (IO DO(IO DI(IO /HOLD(IO DO(IO DI(IO /HOLD(IO Package Code TB Package Code TC Figure 1d. W25Q80BV Ball Assignments, 24-ball TFBGA 8x6-mm (Package Code TB or TC) Ball Description TFBGA 8x6-mm BALL NO.

  • Page 9: Pin Descriptions

    W25Q80BV 4. PIN DESCRIPTIONS 4.1 Chip Select (/CS) The SPI Chip Select (/CS) pin enables and disables device operation. When /CS is high the device is deselected and the Serial Data Output (DO, or IO0, IO1, IO2, IO3) pins are at high impedance. When deselected, the devices power consumption will be at standby levels unless an internal erase, program or write status register cycle is in progress.

  • Page 10: Block Diagram

    W25Q80BV 5. BLOCK DIAGRAM SFDP Register SFDP Register Security Register 1 - 3 Security Register 1 - 3 000000h 000000h 0000FFh 0000FFh 003000h 003000h 0030FFh 0030FFh 002000h 002000h 0020FFh 0020FFh 001000h 001000h 0010FFh 0010FFh Block Segmentation Block Segmentation 0FFF00h 0FFF00h 0FFFFFh 0FFFFFh xxFF00h...

  • Page 11: Functional Description

    W25Q80BV 6. FUNCTIONAL DESCRIPTION 6.1 SPI OPERATIONS 6.1.1 Standard SPI Instructions The W25Q80BV is accessed through an SPI compatible bus consisting of four signals: Serial Clock (CLK), Chip Select (/CS), Serial Data Input (DI) and Serial Data Output (DO). Standard SPI instructions use the DI input pin to serially write instructions, addresses or data to the device on the rising edge of CLK.

  • Page 12: Write Protection

     One Time Program (OTP) write protection * Note: This feature is available upon special order. Please contact Winbond for details. Upon power-up or at power-down, the W25Q80BV will maintain a reset condition while VCC is below the threshold value of V , (See Power-up Timing and Voltage Levels and Figure 38).

  • Page 13: Control And Status Registers

    W25Q80BV CONTROL AND STATUS REGISTERS The Read Status Register-1 and Status Register-2 instructions can be used to provide status on the availability of the Flash memory array, if the device is write enabled or disabled, the state of write protection, Quad SPI setting, Security Register lock status and Erase/Program Suspend status. The Write Status Register instruction can be used to configure the device write protection features, Quad SPI setting and Security Register OTP lock.

  • Page 14: Complement Protect (Cmp)

    Notes: 1. When SRP1, SRP0 = (1, 0), a power-down, power-up cycle will change SRP1, SRP0 to (0, 0) state. 2. This feature is available upon special order. Please contact Winbond for details. 7.1.8 Erase/Program Suspend Status (SUS) The Suspend Status bit is a read only bit in the status register (S15) that is set to 1 after executing a Erase/Program Suspend (75h) instruction.

  • Page 15: Quad Enable (Qe)

    W25Q80BV 7.1.10 Quad Enable (QE) The Quad Enable (QE) bit is a non-volatile read/write bit in the status register (S9) that allows Quad SPI operation. When the QE bit is set to a 0 state (factory default), the /WP pin and /HOLD are enabled. When the QE bit is set to a 1, the Quad IO2 and IO3 pins are enabled, and /WP and /HOLD functions are disabled.

  • Page 16: Status Register Memory Protection (Cmp = 0)

    W25Q80BV 7.1.11 Status Register Memory Protection (CMP = 0) STATUS REGISTER W25Q80BV (8M-BIT) MEMORY PROTECTION BLOCK(S) ADDRESSES DENSITY PORTION NONE NONE NONE NONE 0F0000h – 0FFFFFh 64KB Upper 1/16 0E0000h – 0FFFFFh 14 and 15 128KB Upper 1/8 0C0000h – 0FFFFFh 12 thru 15 256KB Upper 1/4...

  • Page 17: Status Register Memory Protection (Cmp = 1)

    W25Q80BV 7.1.12 Status Register Memory Protection (CMP = 1) STATUS REGISTER W25Q80BV (8M-BIT) MEMORY PROTECTION BLOCK(S) ADDRESSES DENSITY PORTION 000000h – 0FFFFFh 0 thru 15 000000h – 0EFFFFh 0 thru 14 960KB Lower 15/16 000000h – 0DFFFFh 0 thru 13 896KB Lower 7/8 000000h –...

  • Page 18: Instructions

    Read Status Register will be ignored until the program or erase cycle has completed. 7.2.1 Manufacturer and Device Identification MANUFACTURER ID (MF7-MF0) Winbond Serial Flash Device ID (ID7-ID0) (ID15-ID0) Instruction ABh, 90h, 92h, 94h...

  • Page 19: Instruction Set Table 1 (Erase, Program Instructions)

    W25Q80BV 7.2.2 Instruction Set Table 1 (Erase, Program Instructions) BYTE 1 INSTRUCTION NAME BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 (CODE) Write Enable Write Enable for Volatile Status Register Write Disable Read Status Register-1 (S7–S0) Read Status Register-2 (S15–S8) Write Status Register S7–S0...

  • Page 20: Instruction Set Table 2 (Read Instructions)

    W25Q80BV 7.2.3 Instruction Set Table 2 (Read Instructions) BYTE 1 INSTRUCTION NAME BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 (CODE) Read Data A23-A16 A15-A8 A7-A0 (D7-D0) Fast Read A23-A16 A15-A8 A7-A0 dummy (D7-D0) (D7-D0, …) Fast Read Dual Output A23-A16 A15-A8 A7-A0...

  • Page 21: Instruction Set Table 3 (Id, Security Instructions)

    W25Q80BV 7.2.4 Instruction Set Table 3 (ID, Security Instructions) INSTRUCTION BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 NAME (CODE) Release Power down/ dummy dummy dummy (ID7-ID0) Device ID Manufacturer/ dummy dummy (MF7-MF0) (ID7-ID0) Device ID Manufacturer/Device ID A23-A8 A7-A0, M[7:0]...

  • Page 22: Write Enable (06H)

    W25Q80BV 7.2.5 Write Enable (06h) The Write Enable instruction (Figure 4) sets the Write Enable Latch (WEL) bit in the Status Register to a 1. The WEL bit must be set prior to every Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register and Erase/Program Security Registers instruction.

  • Page 23: Write Disable (04H)

    W25Q80BV 7.2.7 Write Disable (04h) The Write Disable instruction (Figure 6) resets the Write Enable Latch (WEL) bit in the Status Register to a 0. The Write Disable instruction is entered by driving /CS low, shifting the instruction code “04h” into the DI pin and then driving /CS high.

  • Page 24: Read Status Register-1 (05H) And Read Status Register-2 (35H)

    W25Q80BV 7.2.8 Read Status Register-1 (05h) and Read Status Register-2 (35h) The Read Status Register instructions allow the 8-bit Status Registers to be read. The instruction is entered by driving /CS low and shifting the instruction code “05h” for Status Register-1 or “35h” for Status Register-2 into the DI pin on the rising edge of CLK.
  • Page 25 W25Q80BV To complete the Write Status Register instruction, the /CS pin must be driven high after the eighth or sixteenth bit of data that is clocked in. If this is not done the Write Status Register instruction will not be executed.

  • Page 26: Read Data (03H)

    W25Q80BV 7.2.10 Read Data (03h) The Read Data instruction allows one or more data bytes to be sequentially read from the memory. The instruction is initiated by driving the /CS pin low and then shifting the instruction code “03h” followed by a 24-bit address (A23-A0) into the DI pin.

  • Page 27: Fast Read (0Bh)

    W25Q80BV 7.2.11 Fast Read (0Bh) The Fast Read instruction is similar to the Read Data instruction except that it can operate at the highest possible frequency of F (see AC Electrical Characteristics). This is accomplished by adding eight “dummy” clocks after the 24-bit address as shown in figure 10. The dummy clocks allow the devices internal circuits additional time for setting up the initial address.

  • Page 28: Fast Read Dual Output (3Bh)

    W25Q80BV 7.2.12 Fast Read Dual Output (3Bh) The Fast Read Dual Output (3Bh) instruction is similar to the standard Fast Read (0Bh) instruction except that data is output on two pins; IO and IO . This allows data to be transferred from the W25Q80BV at twice the rate of standard SPI devices.

  • Page 29: Fast Read Quad Output (6Bh)

    W25Q80BV 7.2.13 Fast Read Quad Output (6Bh) The Fast Read Quad Output (6Bh) instruction is similar to the Fast Read Dual Output (3Bh) instruction except that data is output on four pins, IO , IO , IO , and IO .

  • Page 30: Fast Read Dual I/O (Bbh)

    W25Q80BV 7.2.14 Fast Read Dual I/O (BBh) The Fast Read Dual I/O (BBh) instruction allows for improved random access while maintaining two IO pins, IO and IO . It is similar to the Fast Read Dual Output (3Bh) instruction but with the capability to input the Address bits (A23-0) two bits per clock.
  • Page 31 W25Q80BV Mode 3 Mode 0 A23-16 A15-8 A7-0 M7-0 = MSB IOs switch from Input to Output Byte 1 Byte 2 Byte 3 Byte 4 Figure 13b. Fast Read Dual I/O Instruction Sequence (Previous instruction set M5-4 = 10) Publication Release Date: Augest 01, 2012 - 31 - Revision G...

  • Page 32: Fast Read Quad I/O (Ebh)

    W25Q80BV 7.2.15 Fast Read Quad I/O (EBh) The Fast Read Quad I/O (EBh) instruction is similar to the Fast Read Dual I/O (BBh) instruction except that address and data bits are input and output through four pins IO , IO , IO and IO and four Dummy...
  • Page 33 W25Q80BV Mode 3 Mode 0 IOs switch from A23-16 A15-8 A7-0 M7-0 Dummy Dummy Input to Output Byte 1 Byte 2 Byte 3 Figure 14b. Fast Read Quad I/O Instruction Sequence (Previous instruction set M5-4 = 10) Fast Read Quad I/O with “8/16/32/64-Byte Wrap Around” The Fast Read Quad I/O instruction can also be used to access a specific portion within a page by issuing a “Set Burst with Wrap”...

  • Page 34: Word Read Quad I/O (E7H)

    W25Q80BV 7.2.16 Word Read Quad I/O (E7h) The Word Read Quad I/O (E7h) instruction is similar to the Fast Read Quad I/O (EBh) instruction except that the lowest Address bit (A0) must equal 0 and only two Dummy clock are required prior to the data output.
  • Page 35 W25Q80BV Mode 3 Mode 0 IOs switch from A23-16 A15-8 A7-0 M7-0 Dummy Input to Output Byte 1 Byte 2 Byte 3 Figure 15b. Word Read Quad I/O Instruction Sequence (Previous instruction set M5-4 = 10) Word Read Quad I/O with “8/16/32/64-Byte Wrap Around” The Word Read Quad I/O instruction can also be used to access a specific portion within a page by issuing a “Set Burst with Wrap”...

  • Page 36: Octal Word Read Quad I/O (E3H)

    W25Q80BV 7.2.17 Octal Word Read Quad I/O (E3h) The Octal Word Read Quad I/O (E3h) instruction is similar to the Fast Read Quad I/O (EBh) instruction except that the lower four Address bits (A0, A1, A2, A3) must equal 0. As a result, the dummy clocks are not required, which further reduces the instruction overhead allowing even faster random access for code execution (XIP).
  • Page 37 W25Q80BV Mode 3 Mode 0 IOs switch from A23-16 A15-8 A7-0 M7-0 Input to Output Byte 1 Byte 2 Byte 3 Byte 4 Figure 16b. Octal Word Read Quad I/O Instruction Sequence (Previous instruction set M5-4 = 10) Publication Release Date: Augest 01, 2012 - 37 - Revision G...

  • Page 38: Set Burst With Wrap (77H)

    W25Q80BV 7.2.18 Set Burst with Wrap (77h) The Set Burst with Wrap (77h) instruction is used in conjunction with “Fast Read Quad I/O” and “Word Read Quad I/O” instructions to access a fixed length of 8/16/32/64-byte section within a 256-byte page. Certain applications can benefit from this feature and improve the overall system code execution performance.

  • Page 39: Continuous Read Mode Bits (M7-0)

    W25Q80BV 7.2.19 Continuous Read Mode Bits (M7-0) The “Continuous Read Mode” bits are used in conjunction with “Fast Read Dual I/O”, “Fast Read Quad I/O”, “Word Read Quad I/O” and “Octal Word Read Quad I/O” instructions to provide the highest random Flash memory access rate with minimum SPI instruction overhead, thus allow true XIP (execute in place) to be performed on serial flash devices.

  • Page 40: Page Program (02H)

    W25Q80BV 7.2.21 Page Program (02h) The Page Program instruction allows from one byte to 256 bytes (a page) of data to be programmed at previously erased (FFh) memory locations. A Write Enable instruction must be executed before the device will accept the Page Program Instruction (Status Register bit WEL= 1). The instruction is initiated by driving the /CS pin low then shifting the instruction code “02h”...

  • Page 41: Quad Input Page Program (32H)

    W25Q80BV 7.2.22 Quad Input Page Program (32h) The Quad Page Program instruction allows up to 256 bytes of data to be programmed at previously erased (FFh) memory locations using four pins: IO , IO , IO , and IO . The Quad Page Program can improve performance for PROM Programmer and applications that have slow clock speeds <5MHz.

  • Page 42: Sector Erase (20H)

    W25Q80BV 7.2.23 Sector Erase (20h) The Sector Erase instruction sets all memory within a specified sector (4K-bytes) to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Sector Erase Instruction (Status Register bit WEL must equal 1).

  • Page 43: 32Kb Block Erase (52H)

    W25Q80BV 7.2.24 32KB Block Erase (52h) The Block Erase instruction sets all memory within a specified block (32K-bytes) to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Block Erase Instruction (Status Register bit WEL must equal 1).

  • Page 44: 64Kb Block Erase (D8H)

    W25Q80BV 7.2.25 64KB Block Erase (D8h) The Block Erase instruction sets all memory within a specified block (64K-bytes) to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Block Erase Instruction (Status Register bit WEL must equal 1).

  • Page 45: Chip Erase (C7H / 60H)

    W25Q80BV 7.2.26 Chip Erase (C7h / 60h) The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Chip Erase Instruction (Status Register bit WEL must equal 1).

  • Page 46: Erase / Program Suspend (75H)

    W25Q80BV 7.2.27 Erase / Program Suspend (75h) The Erase/Program Suspend instruction “75h”, allows the system to interrupt a Sector or Block Erase operation or a Page Program operation and then read from or program/erase data to, any other sectors or blocks. The Erase/Program Suspend instruction sequence is shown in figure 25. The Write Status Register instruction (01h) and Erase instructions (20h, 52h, D8h, C7h, 60h, 44h) are not allowed during Erase Suspend.

  • Page 47: Erase / Program Resume (7Ah)

    W25Q80BV 7.2.28 Erase / Program Resume (7Ah) The Erase/Program Resume instruction “7Ah” must be written to resume the Sector or Block Erase operation or the Page Program operation after an Erase/Program Suspend. The Resume instruction “7Ah” will be accepted by the device only if the SUS bit in the Status Register equals to 1 and the BUSY bit equals to 0.

  • Page 48: Power-Down (B9H)

    W25Q80BV 7.2.29 Power-down (B9h) Although the standby current during normal operation is relatively low, standby current can be further reduced with the Power-down instruction. The lower power consumption makes the Power-down instruction especially useful for battery powered applications (See ICC1 and ICC2 in AC Characteristics). The instruction is initiated by driving the /CS pin low and shifting the instruction code “B9h”...

  • Page 49: Release Power-Down / Device Id (Abh)

    W25Q80BV 7.2.30 Release Power-down / Device ID (ABh) The Release from Power-down / Device ID instruction is a multi-purpose instruction. It can be used to release the device from the power-down state, or obtain the devices electronic identification (ID) number. To release the device from the power-down state, the instruction is issued by driving the /CS pin low, shifting the instruction code “ABh”...
  • Page 50 W25Q80BV Mode 3 Mode 3 Mode 0 Mode 0 tRES2 Instruction (ABh) 3 Dummy Bytes Device ID High Impedance = MSB Power-down current Stand-by current Figure 28b. Release Power-down / Device ID Instruction Sequence Diagram - 50 -...

  • Page 51: Read Manufacturer / Device Id (90H)

    The instruction is initiated by driving the /CS pin low and shifting the instruction code “90h” followed by a 24-bit address (A23-A0) of 000000h. After which, the Manufacturer ID for Winbond (EFh) and the Device ID are shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in figure 29.

  • Page 52: Read Manufacturer / Device Id Dual I/O (92H)

    24-bit address (A23-A0) of 000000h, 8-bit Continuous Read Mode Bits, with the capability to input the Address bits two bits per clock. After which, the Manufacturer ID for Winbond (EFh) and the Device ID are shifted out 2 bits per clock on the falling edge of CLK with most significant bits (MSB) first as shown in figure 30.

  • Page 53: Read Manufacturer / Device Id Quad I/O (94H)

    Address bits four bits per clock. After which, the Manufacturer ID for Winbond (EFh) and the Device ID are shifted out four bits per clock on the falling edge of CLK with most significant bit (MSB) first as shown in figure 31. The Device ID values for the W25Q80BV is listed in Manufacturer and Device Identification table.

  • Page 54: Read Unique Id Number (4Bh)

    W25Q80BV 7.2.34 Read Unique ID Number (4Bh) The Read Unique ID Number instruction accesses a factory-set read-only 64-bit number that is unique to each W25Q80BV device. The ID number can be used in conjunction with user software methods to help prevent copying or cloning of a system.

  • Page 55: Read Jedec Id (9Fh)

    2003. The instruction is initiated by driving the /CS pin low and shifting the instruction code “9Fh”. The JEDEC assigned Manufacturer ID byte for Winbond (EFh) and two Device ID bytes, Memory Type (ID15-ID8) and Capacity (ID7-ID0) are then shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in figure 33.

  • Page 56: Read Sfdp Register (5Ah)

    SFDP register contents are shifted out on the falling edge of the 40 CLK with most significant bit (MSB) first as shown in figure 34. For SFDP register values and descriptions, please refer to the Winbond Application Note for SFDP Definition table.

  • Page 57: Erase Security Registers (44H)

    W25Q80BV 7.2.37 Erase Security Registers (44h) The W25Q80BV offers three 256-byte Security Registers which can be erased and programmed individually. These registers may be used by the system manufacturers to store security and other important information separately from the main memory array. The Erase Security Register instruction is similar to the Sector Erase instruction.

  • Page 58: Program Security Registers (42H)

    W25Q80BV 7.2.38 Program Security Registers (42h) The Program Security Register instruction is similar to the Page Program instruction. It allows from one byte to 256 bytes of security register data to be programmed at previously erased (FFh) memory locations. A Write Enable instruction must be executed before the device will accept the Program Security Register Instruction (Status Register bit WEL= 1).

  • Page 59: Read Security Registers (48H)

    W25Q80BV 7.2.39 Read Security Registers (48h) The Read Security Register instruction is similar to the Fast Read instruction and allows one or more data bytes to be sequentially read from one of the three security registers. The instruction is initiated by driving the /CS pin low and then shifting the instruction code “48h”...

  • Page 60: Electrical Characteristics

    = 104MHz, f = 50MHz Commercial Ambient Temperature, Industrial / Auto. Grade 3 °C Operating Industrial Plus / Auto. Grade 2 +105 Note: 1. For Industrial Plus, Automotive Grade 3 & 2 devices, please contact Winbond for more information. - 60 -...

  • Page 61: Power-Up Timing And Write Inhibit Threshold

    W25Q80BV Power-up Timing and Write Inhibit Threshold spec Parameter Symbol Unit VCC (min) to /CS Low µs Time Delay Before Write Instruction Write Inhibit Threshold Voltage Note: 1. These parameters are characterized only. (max) Program, Erase and Write Instructions are ignored /CS must track VCC (min) tVSL...

  • Page 62: Dc Electrical Characteristics

    W25Q80BV 8.4 DC Electrical Characteristics SPEC PARAMETER SYMBOL CONDITIONS UNIT IN (1) Input Capacitance = 0V Output Capacitance Cout = 0V Input Leakage ±2 µA ±2 µA I/O Leakage /CS = VCC, Standby Current µA VIN = GND or VCC /CS = VCC, Power-down Current µA...

  • Page 63: Ac Measurement Conditions

    W25Q80BV 8.5 AC Measurement Conditions SPEC PARAMETER SYMBOL UNIT Load Capacitance Input Rise and Fall Times Input Pulse Voltages 0.2 VCC to 0.8 VCC Input Timing Reference Voltages 0.3 VCC to 0.7 VCC Output Timing Reference Voltages 0.5 VCC to 0.5 VCC Note: 1.

  • Page 64: Ac Electrical Characteristics

    W25Q80BV 8.6 AC Electrical Characteristics SPEC DESCRIPTION SYMBOL UNIT Clock frequency for all instructions except Read Data instruction (03h) D.C. 2.7V-3.6V VCC Clock frequency for all instructions except Read Data instruction (03h) D.C. 3.0V-3.6V VCC Clock frequency for Read Data instruction (03h) D.C.

  • Page 65: Ac Electrical Characteristics (Cont'd)

    W25Q80BV cont’d) 8.7 AC Electrical Characteristics ( SPEC DESCRIPTION SYMBOL UNIT /HOLD Active Hold Time relative to CLK CHHH /HOLD Not Active Setup Time relative to CLK HHCH /HOLD Not Active Hold Time relative to CLK CHHL /HOLD to Output Low-Z HHQX /HOLD to Output High-Z HLQZ...

  • Page 66: Serial Output Timing

    W25Q80BV Serial Output Timing tCLH tCLQV tCLQV tCLL tSHQZ tCLQX tCLQX MSB OUT LSB OUT output Serial Input Timing tSHSL tCHSL tSLCH tCHSH tSHCH tDVCH tCHDX tCLCH tCHCL MSB IN LSB IN input 8.10 /HOLD Timing tHLCH tCHHL tHHCH tCHHH /HOLD tHLQZ tHHQX...

  • Page 67: Package Specification

    W25Q80BV 9. PACKAGE SPECIFICATION 8-Pin SOIC 150-mil (Package Code SN) θ θ 0.25 0.25 SEATING PLANE SEATING PLANE GAUGE PLANE GAUGE PLANE b b b MILLIMETERS INCHES SYMBOL 1.35 1.75 0.053 0.069 0.10 0.25 0.004 0.010 0.33 0.51 0.013 0.020 0.19 0.25 0.008...

  • Page 68: 8-Pin Vsop 150-Mil (Package Code Sv)

    W25Q80BV 8-Pin VSOP 150-mil (Package Code SV) Millimeters Inches Symbol 1.00 0.039 0.05 0.10 0.15 0.002 0.004 0.006 0.75 0.80 0.85 0.030 0.031 0.033 0.19 0.20 0.21 0.007 0.008 0.008 0.33 0.51 0.013 0.020 0.125 BSC 0.005 BSC 4.80 4.90 5.00 0.189 0.193...

  • Page 69: 8-Pin Soic 208-Mil (Package Code Ss)

    W25Q80BV 8-Pin SOIC 208-mil (Package Code SS) GAUGE PLANE GAUGE PLANE MILLIMETERS INCHES SYMBOL 1.75 1.95 2.16 0.069 0.077 0.085 0.05 0.15 0.25 0.002 0.006 0.010 1.70 1.80 1.91 0.067 0.071 0.075 0.35 0.42 0.48 0.014 0.017 0.019 0.19 0.20 0.25 0.007 0.008...

  • Page 70: 8-Pin Vsop 208-Mil (Package Code St)

    W25Q80BV 8-Pin VSOP 208-mil (Package Code ST) Millimeters Inches Symbol ― ― ― ― 1.00 0.039 0.05 0.10 0.15 0.002 0.004 0.006 0.75 0.80 0.85 0.030 0.031 0.033 0.35 0.42 0.48 0.014 0.017 0.019 0.127 REF 0.005 REF 5.18 5.28 5.38 0.204 0.208...

  • Page 71: 8-Pin Pdip 300-Mil (Package Code Da)

    W25Q80BV 8-Pin PDIP 300-mil (Package Code DA) MILLIMETERS INCHES SYMBO 5.33 0.210 0.38 0.015 3.18 3.30 3.43 0.125 0.130 0.135 9.02 9.27 10.16 0.355 0.365 0.400 7.62 BSC. 0.300 BSC. 6.22 6.35 6.48 0.245 0.250 0.255 2.92 3.30 3.81 0.115 0.130 0.150 8.51...

  • Page 72: 8-Pad Wson 6X5Mm (Package Code Zp)

    W25Q80BV 8-Pad WSON 6x5mm (Package Code ZP) MILLIMETERS INCHES SYMBOL 0.70 0.75 0.80 0.028 0.030 0.031 0.00 0.02 0.05 0.000 0.001 0.002 0.35 0.40 0.48 0.014 0.016 0.019 0.20 REF. 0.008 REF. 5.90 6.00 6.10 0.232 0.236 0.240 3.35 3.40 3.45 0.132 0.134...
  • Page 73 0.026 Notes: 1. Advanced Packaging Information; please contact Winbond for the latest minimum and maximum specifications. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E do not include mold flash protrusions and should be measured from the bottom of the package.

  • Page 74: 8-Pad Uson 2X3-Mm (Package Code Ux)

    W25Q80BV 8-Pad USON 2x3-mm (Package Code UX) INDENT Note: Exposed pad dimension D2 & E2 may be different by die size. MILLIMETER INCHES SYMBO TYP. TYP. 0.50 0.55 0.60 0.020 0.022 0.024 0.00 0.02 0.05 0.000 0.001 0.002 0.20 0.25 0.30 0.008 0.010...

  • Page 75: 24-Ball Tfbga 8X6-Mm (Package Code Tb, 5X5-1 Ball Array)

    W25Q80BV 24-Ball TFBGA 8x6-mm (Package Code TB, 5x5-1 ball array) Note: Ball land: 0.45mm. Ball Opening: 0.35mm PCB ball land suggested <= 0.35mm Millimeters Inches Symbol 1.20 0.047 0.25 0.30 0.35 0.010 0.012 0.014 0.85 0.033 0.35 0.40 0.45 0.014 0.016 0.018 7.90...

  • Page 76: 24-Ball Tfbga 8X6-Mm (Package Code Tc, 6X4 Ball Array)

    W25Q80BV 24-Ball TFBGA 8x6-mm (Package Code TC, 6x4 ball array) MILLIMETERS INCHES SYMBOL 1.20 0.047 0.25 0.30 0.35 0.010 0.012 0.014 0.35 0.40 0.45 0.014 0.016 0.018 7.95 8.00 8.05 0.313 0.315 0.317 5.00 BSC 0.197 BSC 5.95 6.00 6.05 0.234 0.236 0.238...

  • Page 77: Ordering Information

    W25Q80BV 10. ORDERING INFORMATION 25Q 80B V xx W = Winbond 25Q = SpiFlash Serial Flash Memory with 4KB sectors, Dual/Quad I/O 80B = 8M-bit V = 2.7V to 3.6V SN = SOIC-8 150-mil SV = VSOP-8 150-mil ZP = WSON-8 6x5-mm UX = USON-8 2x3-mm...

  • Page 78: Valid Part Numbers And Top Side Marking

    The following table provides the valid part numbers for the W25Q80BV SpiFlash Memory. Please contact Winbond for specific availability by density and package type. Winbond SpiFlash memories use an 12- digit Product Number for ordering. However, due to limited space, the Top Side Marking on all packages use an abbreviated 10-digit number.
  • Page 79 1. WSON package type ZP is not used in the top side marking. 2. These Package types are Special Order only, please contact Winbond for more information. 3. For Industrial Plus, Automotive Grade 2 & Grade 3 Temperature parts, please contact Winbond for more information and availability.

  • Page 80: Revision History

    Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.

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