I2S Clock Lines; Tdm Clock Lines; I2S Data Lines - miniDSP USBStreamer Box User Manual

2.2.2 I2S Clock lines

There are three clock lines. These clocks are always outputs. The connected circuitry must therefore be set to run in
slave mode and accept its clocks from the USBStreamer. (The USBStreamer always runs as clock master; it cannot be
set to run as a slave.)
MCLK The master clock for both playback and recording. This pin is an output only.
LRCLK The frame synchronization clock, also known as the word clock. This clock is equal to the sampling
frequency (Fs) of the audio signal. This pin is an output only.
BCLK The bit clock (also known as shift clock or system clock). This is always equal to 64 x Fs. This pin is an
output only.
The following table summarizes the relation between the clocks. Be sure to double-check that connected circuitry
will accept the clocks at the frequencies and ratios listed here:
Sample rate (LRCLK) Master clock (MCLK) Bit clock (BCLK) MCLK/LRCLK BCLK/LRCLK
44.1 kHz
48 kHz
88.2 kHz
96 kHz
176.4 kHz
192 kHz

2.2.3 TDM Clock lines

The clock lines are the same as per I2S above. Just a different clock rate.
Sample rate (LRCLK) Master clock (MCLK) Bit clock (BCLK) MCLK/LRCLK BCLK/LRCLK
44.1 kHz
48 kHz

2.2.4 I2S Data lines

There are four lines for input data, and four line for output data (as indicated in the pinout on the previous page).
Each line carries two audio channels, in either 16-bit or 24-bit format. The expected I2S data format and timing is
shown in this diagram:
miniDSP Ltd, Hong Kong / www.minidsp.com
22.5792 MHz
24.576 MHz
22.5792 MHz
24.576 MHz
22.5792 MHz
24.576 MHz
22.5792 MHz
24.576 MHz
/ Features and specifications subject to change without prior notice
2.822 MHz
3.072 MHz
5.6448 MHz
6.144 MHz
11.2896 MHz
12.288 MHz
11.2896 MHz
12.288 MHz
512 64
512 64
256 64
256 64
128 64
128 64
512 64
512 64
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