Figure 3.1. Back View Of Ecp5 Vip Input Bridge Board - Lattice EVDK User Manual

JTAG Daisy Chain
Header (J50)
ispClock5406D
(U53)
ECP5
Configuration
Selection
Header (J3)
ProgramN (SW4)
Upstream
Connector (J10)
Nanovesta
Connectors
(CN1, CN2)
Upstream
Connector
(J11)
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FPGA-UG-02073-1.0
ispClock JTAG Bank 2 Voltage
User Header Selection Header
(J54) (J1)
Bank 1, 8, 3 Voltage
Selection Headers
(J6, J9, J5)

Figure 3.1. Back View of ECP5 VIP Input Bridge Board

EVDK Based Vehicle Classification
(J55)
General Purpose Bank 4
Switches (SW3) Voltage Selection
Header (J51)
User Guide
Debug Header (J14)
Power ON/OFF
Switch (SW2)
12V DC Power
Jack (J4) (Front)
USB Mini-B
Connector (J2) (Front)
User LEDs
FTDI TCK Pull
Up/Down (J52)
Bank 0 Voltage
Selection Header (J7)
9