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Corporation general policy does not recommend the use of its products in life support applications where in a failure or malfunction of the product may directly threaten life or injury. Per SanDisk Terms and Conditions of Sale, the user of SanDisk products in life support applications assumes all risk of such use and indemnifies SanDisk against all damages.
Scope Product Models This document describes the key features and The SDP3B FlashDisk is available in 2 to 220 specifications of the SDP3B FlashDisk, as well as megabyte capacities. All SDP3B FlashDisks are the information required to interface this product shipped formatted with a DOS 5.0 file structure.
The FlashDisk defaults to the fastest speed and highest current. See the Set Features command for more details. Note 3. For information on peak currents during power on, hot insertion and writing, please contact SanDisk Technical Support at (408) 542-0400.
In some early platforms, the -VS1 pin (pin 43) is also the Refresh pin for DRAM cards. Plugging The 512 byte sector size of SDP3B FlashDisk is the SDP3B into a platform supporting the the same as that in an IDE magnetic disk drive. To Refresh pin will hang the bus.
For instance, it would take over 34 years correctly, but will be at the normal write speed to wear out an area on the SDP3B FlashDisk on that is slower than a Write without Erase which a file of any size (from 512 bytes to command.
The advantage of the Write without Erase and Erase Sector commands is that they shift the bulk A very unique and valuable feature of the SDP3B of the erase and write time to the Erase Sector FlashDisk is the ability of the host to control the command.
Note: The Sleep to Write and Sleep to Read times are the times it takes the SDP3B FlashDisk to exit sleep mode when any command is issued by the host to when the card is reading or writing. SDP3B FlashDisks do not require a reset to exit sleep mode.
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Present signal in the Master/Slave handshake protocol. -CD1, -CD2 36, 67 These Card Detect pins are connected to ground on the SDP3B (PC Card Memory Mode) FlashDisk. They are used by the host to determine if the product is fully inserted into its socket.
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-IORD This is an I/O Read strobe generated by the host. This signal (PC Card I/O Mode) gates I/O data onto the bus from the SDP3B FlashDisk when the card is configured to use the I/O interface. -IORD In True IDE Mode, this signal has the same function as in PC (True IDE Mode) Card I/O Mode.
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This is an Output Enable strobe generated by the host interface. (PC Card Memory Mode) It is used to read data from the SDP3B FlashDisk in Memory Mode and to read the CIS and configuration registers. In PC Card I/O Mode, this signal is used to read the CIS and (PC Card I/O Mode) configuration registers.
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This signal is the same for all modes. -VS2 (True IDE Mode) -WAIT The -WAIT signal is driven low by the SDP3B FlashDisk to signal (PC Card Memory Mode) the host to delay completion of a memory or I/O cycle that is in progress.
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Table 4-2 Signal Description (continued) Signal Name Dir. Description Memory Mode - The SDP3B FlashDisk does not have a write (PC Card Memory Mode) protect switch. This signal is held low after the completion of the Write Protect reset initialization sequence.
Pull Down Resistor RPD1 Vcc = 5.0V 500k Note: The minimum pullup resistor leakage current meets the PCMCIA specification of 10k ohms but is intentionally higher in the SDP3B FlashDisk to reduce power use. 4.3.2 Input Characteristics Type Parameter Symbol Units VCC = 3.3 V...
Figure 4-1 Attribute Memory Read Timing Diagram Notes: All times are in nanoseconds. Dout signifies data provided by the SDP3B FlashDisk to the system. The -CE signal or both the -OE signal and the -WE signal must be de-asserted between consecutive cycle operations.
The maximum load on -WAIT is 1 LSTTL with 50pF total load. All times are in nanoseconds. Dout signifies data provided by the SDP3B FlashDisk to the system. The -WAIT signal may be ignored if the -OE cycle to cycle time is greater than the Wait Width time.
The maximum load on -WAIT is 1 LSTTL with 50pF total load. All times are in nanoseconds. Din signifies data provided by the system to the SDP3B FlashDisk. The -WAIT signal may be ignored if the -WE cycle to cycle time is greater than the Wait Width time.
The location of the card configuration registers should always be read from the CIS since these locations may vary in future products. No writes should be performed to the SDP3B FlashDisk attribute memory except to the card configuration register addresses. All other attribute memory locations are reserved.
Soft Reset - Setting this bit to one (1), waiting the minimum reset width time and returning to zero (0) places the SDP3B FlashDisk in the Reset state. Setting this bit to one (1) is equivalent to assertion of the +RESET signal except that the SRESET bit is not cleared. Returning this bit to zero (0) leaves the SDP3B FlashDisk in the same un-configured, Reset state as following power- up and hardware reset.
I O i s 8 The host sets this bit to a one (1) if the SDP3B FlashDisk is to be configured in an 8 bit I/O mode. The SDP3B FlashDisk is always configured for both 8- and 16-bit I/O, so this bit is ignored.
I/O Transfer Function 4.5.1 I/O Function The I/O transfer to or from the SDP3B FlashDisk FlashDisk permits both 8- and 16-bit accesses to can be either 8 or 16 bits. When a 16-bit accessible all of its I/O addresses, so -IOIS16 is asserted for...
The Common Memory transfer to or from the The SDP3B FlashDisk may request the host to SDP3B FlashDisk can be either 8 or 16 bits. extend the length of a memory write cycle or extend the length of a memory read cycle until...
SDP3B FlashDisk Product Manual True IDE Mode I/O Transfer Function 4.7.1 True IDE Mode I/O Function The SDP3B FlashDisk can be configured in a True Note: Removing and reinserting the SDP3B FlashDisk IDE Mode of operation. This SDP3B FlashDisk is while the host computer’s power is on will...
SDP3B FlashDisk Product Manual 5.0 ATA Drive Register Set Definition and Protocol The SDP3B FlashDisk can be configured as a high The communication to or from the SDP3B performance I/O device through: FlashDisk is done using the Task File registers which provide all the necessary registers for a.) Standard PC-AT disk I/O address spaces...
8 then 9 will access consecutive (even then odd) bytes from the data buffer. Byte accesses to register 9 access only the odd byte of the data. 3. Address lines which are not indicated are ignored by the SDP3B FlashDisk for accessing all the registers in this table.
0,8,9) access to the 1F1, 171 or offset 1 are not defined for word (-CE2 = 0 and -CE1 = 0) operations. SanDisk products treat these accesses as accesses to the The Data Register is a 16 bit register, and it is Word Data Register.
Bit 3 This bit is 0. Bit 2 (Abort) This bit is set if the command has been aborted because of a SDP3B FlashDisk status condition: (Not Ready, Write Fault, etc.) or when an invalid command has been issued. Bit 1 This bit is 0.
This bit will have the following meaning. DRV is the drive number. When DRV=0, drive (card) 0 is selected When DRV=1, drive (card) 1 is selected. The SDP3B FlashDisk is set to be Card 0 or 1 using the copy field of the PCMCIA Socket & Copy configuration register.
This bit is ignored by the SDP3B FlashDisk. Bit 2 (SW Rst) This bit is set to 1 in order to force the SDP3B FlashDisk to perform an AT Disk controller Soft Reset operation. This does not change the PCMCIA Card Configuration Registers (4.3.2 to 4.3.5) as a hardware Reset does.
Address Space when a Floppy Disk Controller is located at the Primary addresses. 2. Do not install a Floppy and a SDP3B FlashDisk in the system at the same time. 3. Implement a socket adapter which can be programmed to (conditionally) tri-state D7 of I/0 address 3F7/377 when a SDP3B FlashDisk is installed and conversely to tri-state D6-D0 of I/O address 3F7/377 when a floppy controller is installed.
DRQ within 20 msec (assuming the SDP3B FlashDisk is not busy. (The BUSY bit no re-assignments), and clears the BUSY bit in the status and alternate status registers is 0.) within 400 nsec of setting DRQ.
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Y - The register contains a valid parameter for this command. For the Drive/Head Register Y means both the SDP3B FlashDisk and head parameters are used; D - only the SDP3B FlashDisk parameter is valid and not the head parameter.
Sec Cnt (2) Feature (1) This command checks the power mode. If the SDP3B FlashDisk is in Idle mode, the SDP3B FlashDisk sets BSY, sets the Sector Count If the SDP3B FlashDisk is in, going to, or Register to FFh, clears BSY and generates an recovering from the sleep mode, the SDP3B interrupt.
Only Sector Count and offset to the Boot Record based on the number of heads and sectors per track. If a SDP3B Card/Drive/Head registers are used by this FlashDisk is “Formatted” with one head and command. sector per track value, the same SDP3B...
Feature (1) Note: The current revision of the SDP3B FlashDisk only supports a block count of 1 as indicated in the Identify Drive Information command. This command is provided for compatibility with future products which may support a larger block count.
(except the last one) has been the cylinder, head, and sector number of the sector read by the host, the SDP3B FlashDisk sets BSY, where the error occurred. The flawed data is puts the sector of data in the buffer, sets DRQ, pending in the sector buffer.
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Disable Read Look Ahead. Disable Power on Reset (POR) establishment of defaults at Soft Reset. Accepted for backward compatibility with the SDP Series but has no impact on the SDP3B FlashDisk. Disable 8 bit data transfer. Accepted for backward compatibility with the SDP Series but has no impact on the SDP3B FlashDisk.
The current version of and Read Multiple and Write Multiple commands the SDP3B FlashDisk supports only a block size of are disabled. If the Sector Count Register contains 1 sector per block. Future versions may support 0 when the command is issued, Read and Write larger block sizes.
Internet users can obtain technical support and product information along with SanDisk news and much more from the SanDisk Worldwide Web Site, 24 hours a day, seven days a week. The SanDisk Worldwide Web Site is frequently updated. Visit this site often to obtain the most up-to-date...
Below is a list of PC card reader/writers that are compatible with the SanDisk FlashDisk. These reader/writers can be installed in desktop PCs to enable the SDP3B FlashDisk to be used in those systems. The SDP3B FlashDisk will operate in any of these reader/writers.
II. GENERAL PROVISIONS This warranty sets forth the full extent of SanDisk’s responsibilities regarding the SanDisk FlashDisk. In satisfaction of its obligations hereunder, SanDisk, at its sole option, will either repair, replace or refund the purchase price of the product.