u-blox LEA-5 Series Hardware Manual page 19

decides with which peripheral device it wants to communicate. The clock line SCK provides synchronization for
data communication and is brought to the device whether or not it is selected.
The majority of SPI devices provide all four of these lines. Sometimes MOSI and MISO are multiplexed, or else
one is missing. A peripheral device, which must not or cannot be configured, requires no input line but only a
data output. As soon as it gets selected it starts sending data. In some ADCs therefore the MOSI line is missing.
Some devices have no data output (e.g. LCD controllers which can be configured, but cannot send data or status
messages).
The following rules should answer the most common questions concerning these signals:
SCK: The SCK pin is an output when the SPI is configured as a master and an input when the SPI is
configured as a slave. When the SPI is configured as a master, the SCK signal is derived from the internal bus
clock. When the master initiates a transfer, eight clock cycles are automatically generated on the SCK pin.
When the SPI is configured as a slave, the SCK pin is an input, and the clock signal from the master
synchronizes the data transfer between the master and slave devices. Slave devices ignore the SCK signal
unless the slave select pin is active low. In both the master and slave SPI devices, data is shifted on one edge
of the SCK signal and is sampled on the opposite edge where data is stable. Edge polarity is determined by
the SPI transfer protocol.
MISO/MOSI: The MISO and MOSI data pins are used for transmitting and receiving serial data. When the
SPI is configured as a master, MISO is the master data input line, and MOSI is the master data output line.
When the SPI is configured as a slave, these pins reverse roles.
SCS/SS_N: In master mode, the SCS output(s) select external slaves (e.g. SCS1_N, SCS2_N). In slave mode,
SS_N is the slave select input. The chip select pin behaves differently on master and slave devices. On a slave
device, this pin is used to enable the SPI slave for a transfer. If the SS_N pin of a slave is inactive (high), the
device ignores SCK clocks and keeps the MISO output pin in the high-impedance state. On a master device,
the SCS pin can serve as a general-purpose output not affecting the SPI.
1.5.4.2 Connecting serial memory to u-blox 5 modules
Serial SPI memory can be connected to the SPI interface. It will automatically be recognized by firmware when
connected to SCS1_N.
Figure 10 shows how external memory can be connected. Note that an external voltage is required to power the
EEPROM (VDD_IO on the receiver is an input).
SCS1_N
MISO
MOSI
SCK
u-blox GPS Receiver
Figure 10: Connecting external Serial SPI Memory to u-blox GPS receivers
External memory on the SPI interface is only supported by FW 6.00 and above. Only 128 kByte
memory size is supported.
1.5.4.3 Connecting u-blox 5 modules to an SPI master
Figure 11 shows how to connect a u-blox GPS receiver to a host/master. The signal on the pins must meet the
conditions specified in the Data Sheet.
GPS.G5-MS5-09027-A2
VDD
VDD
CE_N
WP_N
SO
SI
SCK
EEPROM
LEA-5, NEO-5, TIM-5H - Hardware Integration Manual
Released Hardware description
Page 19 of 68