u-blox LEA-5 Series Hardware Manual page 18

device is not selected (i.e. its chip select is not activated), its data output enters a high-impedance state (hi-Z) and
does not interfere with SPI bus activities.
The data output MISO functions as the data return signal from the slave to the master.
Figure 9 shows a typical block diagram for an SPI master with several slaves. Here, the SCK and MOSI data lines
are shared by all of the slaves. Also the MISO data lines are linked together and led back to the master. Only the
chip selects are separately brought to each SPI device.
SPI Master
SCS
0
SCS
1
SCS
2
SCK
MOSI
Data Input
MISO
Figure 9: Master with independent slaves
SPI allows multiple microcontrollers to be linked together. These can be configured according to single or
multiple master protocols. In the first variant the microcontroller(s) designated as slave(s) behave like a normal
peripheral device. The second variant allows for several masters and allows each microprocessor the possibility to
take the role of master and to address another microprocessor. In this case one microcontroller must
permanently provide the clock signal.
There are two SPI system errors. The first occurs if several SPI devices want to become master at the same time.
The other is a collision error that occurs for example when SPI devices work with different polarities.
Systems involving multiple microcontrollers are beyond the scope of this document.
Cascading slave peripherals is not supported.
Four I/O pin signals are associated with SPI transfers: the SCK, the MISO data line, the MOSI data line, and the
active low SCS/SS_N pin. In the unselected state the MISO lines are hi-Z and therefore inactive. The master
GPS.G5-MS5-09027-A2
LEA-5, NEO-5, TIM-5H - Hardware Integration Manual
MOSI
SS_N SPI Slave
MISO
0
SCK
MOSI
SPI Slave
MISO
SS_N
1
SCK
MOSI
SPI Slave MISO
SS_N
2
SCK
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