Denon S-81 Service Manual page 34

TC94A14FAG (IC307 : 1U-3760)
48 47 46
DV 49
SS3
RO 50
DV 51
DD3
LPF
DVR 52
LO 53
DV 54
SS3
ZDET 55
V 56
SS5
BUS0 57
BUS1 58
BUS2 59
BUS3 60
BUCK 61
Micro-
/CCE 62
controller
interface
/RST 63
V 64
DD5
1 2 3
Pin Functions
Pin No. Symbol I/O
O
1 BCK
3-5I/F
O
2 LRCK
3-5I/F
O
3 AOUT
3-5I/F
O
4 DOUT
3-5I/F
O
5 I PF
3-5I/F
-
6 V ˇ
DD3
-
7 V ˇ
SS3
O
8 SBOK
3-5I/F
I/O
9 CLCK
3-5I/F
O
10 DATA
3-5I/F
45 44 43 42 41
Clock
generator
1-bit
DAC
Address
circuit
16 k
RAM
Audio out
Digital output
circuit
4 5 6 7 8
Function Description
Bit clock output pin. 32fs, 48fs, or 64fs selectable by command.
L/R channel clock output pin. "L" for L channel and "H" for R
channel. Output polarity can be inverted by command.
Audio data output pin. MSB-first or LSB-first selectable by
command.
Digital data output pin. Outputs up to double-speed playback.
Correction flag output pin. When set to "H", AOUT output cannot
be corrected by C2 correction processing.
Digital 3.3 V power supply voltage pin.
Digital GND pin.
Subcode Q data CRCC result output pin. "H" level when result is
OK.
Subcode P-W data read clock I/O pin. I/O polarity selectable by
command.
Subcode P-W data output pin.
40 39 38 37 36
PWM
A/D
Servo control
ROM Digital equalizer
automatic
RAM
adjustment circuit
CLV servo
Synchronous
guarantee
EFM
decoder
Sub code
decoder TMAX
9 10 11 12 13
34
S-81/S-81DAB
35 34 33
32 TEZI
31 TEI
D/A
30 SBAD
29 FEI
28 RFRP
27 RFZI
26 RFCT
25 AV
DD3
24 RFI
Data
slicer
23 SLCO
22 AV
SS3
VCO
21 VCOF
20 PV
REF
19 LPFO
PLL
18 LPFN
17 TMAX
14 15 16
Remarks
Normal speed:
=
32fs ı 1.4112 MHz
Normal speed: 44.1 kHz
-
ˇ
Based on CP-1201
Alias: C2PO
-
ˇ
-
ˇ
-
ˇ
Schmitt input
-
ˇ