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Altera JESD204B IP CORE User Manual

Altera JESD204B IP CORE User Manual

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JESD204B IP Core User Guide
UG-01142
2015.05.04
101 Innovation Drive
San Jose, CA 95134
www.altera.com

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Summary of Contents for Altera JESD204B IP CORE

  • Page 1 JESD204B IP Core User Guide Last updated for Altera Complete Design Suite: 15.0 101 Innovation Drive UG-01142 Subscribe 2015.05.04 San Jose, CA 95134 Send Feedback www.altera.com...

  • Page 2: Table Of Contents

    Generating and Simulating the IP Core Testbench..............3-8 Compiling the JESD204B IP Core Design..................3-10 Programming an FPGA Device....................3-11 JESD204B IP Core Design Considerations.................... 3-11 Integrating the JESD204B IP core in Qsys................. 3-11 Pin Assignments..........................3-12 Adding External Transceiver PLL....................3-13 Timing Constraints For Input Clocks..................3-13 JESD204B IP Core Parameters.........................3-16...
  • Page 3 System Interface Signals........................5-44 Example Feature: Dynamic Reconfiguration................5-49 Generating and Simulating the Design Example...............5-55 Generating the Design Example For Compilation..............5-56 Compiling the JESD204B IP Core Design Example..............5-57 JESD204B IP Core Deterministic Latency Implementation Guidelines... 6-1 Constraining Incoming SYSREF Signal....................6-1 Programmable RBD Offset.........................6-2 Programmable LMFC Offset........................

  • Page 4: Jesd204B Ip Core Quick Reference

    Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 5 • Arria 10 FPGA device families • Stratix V FPGA device families ® Refer to the device support table andWhat’s New in Altera IP page of the Altera website for detailed information. Design Tools • Qsys parameter editor in the Quartus II software for design creation and compilation •...

  • Page 6: About The Jesd204B Ip Core

    Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 7 About the JESD204B IP Core 2015.05.04 Figure 2-1: Typical System Application for JESD204B IP Core The JESD204B IP core utilizes the Avalon-ST source and sink interfaces, with unidirectional flow of data, to transmit and receive data on the FPGA fabric interface. FPGA...

  • Page 8: Datapath Modes

    TX path. The JESD204B IP core generates a single link with a single lane and up to a maximum of 8 lanes. If there are two ADC links that need to be synchronized, you have to generate two JESD204B IP cores and then manage the deterministic latency and synchronization signals, like SYSREF and SYNC_N, at your custom wrapper level.

  • Page 9: Jesd204B Ip Core Configuration

    For example, if a converter device supports LMF = 442 and LMF = 222, to check the performance for both configurations, you need to generate the JESD204B IP core with maximum F and L, which is L = 4 and F = 2.

  • Page 10: Channel Bonding

    F parameter according to the JESD204B IP Specification for a correct data mapping. To support the High Density (HD) data format, the JESD204B IP core tracks the start of frame and end of frame because F can be either an odd or even number. The start of frame and start of multi-frame wrap around the 32-bits data width architecture.

  • Page 11: Performance And Resource Utilization

    PHY only Non-bonded Arria 10 Bonded Stratix V MAC and PHY Non-bonded Performance and Resource Utilization Table 2-3: JESD204B IP Core FPGA Performance Data Rate PMA Speed FPGA Fabric Device Family Link Clock F (MHz) Enable Hard Enable Soft PCS...
  • Page 12 2.0 to 8.5 2.0 to 8.5 312.50 The following table lists the resources and expected performance of the JESD204B IP core. These results are obtained using the Quartus II software targeting the following Altera FPGA devices: • Cyclone V : 5CGTFD9E5F31I7 •...
  • Page 13 Note: The resource utilization data are extracted from a full design which includes the Altera Transceiver PHY Reset Controller IP Core. Thus, the actual resource utilization for the JESD204B IP core should be smaller by about 15 ALMs and 20 registers.
  • Page 14 MLAB to M20K or M10K was performed for the numbers listed above. The Quartus II software may auto-fit to use MLAB when the memory size is too small. Conversion from MLAB to M20K or M10K was performed for the numbers listed above. About the JESD204B IP Core Altera Corporation Send Feedback...

  • Page 15: Getting Started

    Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 16: Installing And Licensing Ip Cores

    2015.05.04 Installing and Licensing IP Cores The Altera IP Library provides many useful IP core functions for your production use without purchasing an additional license. Some Altera MegaCore IP functions require that you purchase a separate license for production use. However, the OpenCore feature allows evaluation of any Altera IP core in simulation ®...
  • Page 17 IP core version differences and links to Release Notes. IP End of Life Altera designates the IP core as end-of-life status. You may or may not be able to edit the IP core in the parameter editor. Support for this IP core discontinues in future releases of the Quartus II software.
  • Page 18 Runs “Auto Upgrade” on all supported outdated cores Opens editor for manual IP upgrade Note: IP cores older than Quartus II software version 12.0 do not support upgrade. Altera verifies that the current version of the Quartus II software compiles the previous version of each IP core.

  • Page 19: Ip Catalog And Parameter Editor

    • Right-click an IP core name in IP Catalog to display details about supported devices, open the IP core's installation folder, and view links to documentation. • Click Search for Partner IP, to access partner IP information on the Altera website. Getting Started...

  • Page 20: Design Walkthrough

    Design Walkthrough This walkthrough explains how to create a JESD204B IP core design using Qsys in the Quartus II software. After you generate a custom variation of the JESD204B IP core, you can incorporate it into your overall project. Creating a New Quartus II Project You can create a new Quartus II project with the New Project Wizard.

  • Page 21: Parameterizing And Generating The Ip Core

    • Enable Capability Registers To include existing files, you must specify the directory path to where you installed the JESD204B IP core. You must also add the user libraries if you installed the MegaCore IP Library in a different directory from where you installed the Quartus II software.

  • Page 22: Generating And Simulating The Ip Core Testbench

    2. Simulate the testbench using the simulator-specific scripts that you have generated. Refer to Simulating the IP Core Testbench on page 3-9. Note: Some configurations are preset and are not programmable in the JESD204B IP core testbench. For JESD204B IP Core Testbench more details, refer to...
  • Page 23 • VCS MX • Cadence • Aldec Riviera Note: VHDL is not supported in ModelSim-Altera AE, VCS simulators, and Aldec Riviera (for Arria 10 devices only). Table 3-2: Simulation Setup Scripts This table lists the simulation setup scripts and run scripts.

  • Page 24: Compiling The Jesd204B Ip Core Design

    Cadence <example_design_directory> run_altera_jesd204_tb.sh /ip_sim/testbench/cadence To simulate the testbench design using the ModelSim-Altera or Aldec Riviera-PRO simulator, follow these steps: 1. Launch the ModelSim-Altera or Aldec Riviera-PRO simulator. 2. On the File menu, click Change Directory > Select <example_design_directory>/ip_sim/testbench/ <simulator name>.

  • Page 25: Programming An Fpga Device

    Related Information Device Programming JESD204B IP Core Design Considerations You must be aware of the following conditions when integrating the JESD204B IP core in your design: • Intergrating the IP core in Qsys • Pin assignments • Adding external transceiver PLL •...

  • Page 26: Pin Assignments

    You can create virtual pins to avoid making specific pin assignments for top-level signals. This is useful when you want to perform compilation, but are not ready to map the design to hardware. Altera recommends that you create virtual pins for all unused top-level signals to improve timing closure.

  • Page 27: Adding External Transceiver Pll

    ) that specifies the timing constraints for the input clocks to your IP core. .sdc When you generate the JESD204B IP core, your design is not yet complete and the JESD204B IP core is not yet connected in the design. The final clock names and paths are not yet known. Therefore, the...
  • Page 28 • Specify the PLL clock reference pin frequency using the command. create_clock • Derive the PLL generated output clocks from the Altera PLL IP Core (for Arria V, Cyclone V and Stratix V) or Altera I/O PLL IP Core (for Arria 10) using the command.
  • Page 29 The table below shows an example where the in this design is an input into the transceiver device_clk pin. The IP core's Avalon-MM interface shares the same clock source as the transceiver refclk management clock. (10) For Arria 10 device only. Getting Started Altera Corporation Send Feedback...

  • Page 30: Jesd204B Ip Core Parameters

    \ mgmt_clk -group {mgmt_clk \ <base and generated clock names as reported by report_clock commands> \ JESD204B IP Core Parameters Table 3-6: JESD204B IP Core Parameters Parameter Value Description Main Tab Device Family Select the targeted device family.
  • Page 31 UG-01142 3-17 JESD204B IP Core Parameters 2015.05.04 Parameter Value Description Data Path • Receiver Select the operation modes. This selection enables or disables the receiver and transmitter supporting logic. • Transmitter • Duplex • RX—instantiates the receiver to interface to the ADC.
  • Page 32 Enable Capability Registers parameter. (13) To perform dynamic reconfiguration, you have to instantiate the Transceiver Reconfiguration Controller from the IP Catalog and connect it to the JESD204B IP core through the reconfig_to_xcvr interface. reconfig_from_xcvr (14) To support the Transceiver Toolkit in your design, you must turn on this option.
  • Page 33 UG-01142 3-19 JESD204B IP Core Parameters 2015.05.04 Parameter Value Description Enable Control and On, Off Turn on this option to enable soft registers for reading status Status Registers (14) signals and writing control signals on the PHY interface through the embedded debug. Signals include...
  • Page 34 UG-01142 3-20 JESD204B IP Core Parameters 2015.05.04 Frames per multiframe 1–32 Set the number of frames per multiframe. This value is dependent on the value of F and is derived using the following constraints: • The value of K must fall within the range of 17/F <= K <= min(32, floor (1024/F))

  • Page 35: Jesd204B Ip Core Component Files

    Contains a list of required simulation files for your IP core. JESD204B IP Core Testbench The JESD204B IP core includes a testbench to demonstrate a normal link-up sequence for the JESD204B IP core with a supported configuration. The testbench also provides an example of how to control the JESD204B IP core interfaces.
  • Page 36 Link Clock Data rate/40 AVS Clock 125 MHz Figure 3-5: JESD204B IP Core Testbench Block Diagram The external ATX PLL is present only in the JESD204B IP core testbench targeting an Arria 10 FPGA device family. JESD204B Testbench Packet Packet...

  • Page 37: Testbench Simulation Flow

    If no error is detected, the testbench issues a TESTBENCH PASSED message stating that the simulation was successful. If an error is detected, the testbench issues a TESTBENCH FAILED message to indicate that the testbench has failed. Getting Started Altera Corporation Send Feedback...

  • Page 38: Jesd204B Ip Core Functional Description

    Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 39 UG-01142 JESD204B IP Core Functional Description 2015.05.04 Figure 4-1: Overview of the JESD204B IP Core Block Diagram Transport Layer Data Link Layer Physical Layer JESD204B JESD204B IP Core Design Example jesd204_tx_top DAC Application MAC (jesd204_tx_base) PHY (jesd204_tx_phy) SYNC~ Layer Driver...
  • Page 40 JESD204B TX and RX Transport Layer with Base and Transceiver (Design Example) 32-Bits Architecture The JESD204B IP core consist of 32-bit internal datapath per lane. This means that JESD204B IP Core expects the data samples to be assembled into 32-bit data (4 octets) per lane in the transport layer before sending the data to the Avalon-ST data bus.

  • Page 41: Transmitter

    Per Channel 32 Bits per Channel Data Link Per Device Scrambler Serial Interface Layer (TX) JESD204B (TX) Transceiver (TX_n, TX_p) (TX) Per Device The transmitter block consists of the following modules: JESD204B IP Core Functional Description Altera Corporation Send Feedback...

  • Page 42: Tx Data Link Layer

    Alignment Sequence (ILAS), performs scrambling, lane insertion and frame alignment of characters. TX Data Link Layer The JESD204B IP core TX data link layer includes three phases to establish a synchronized link—Code Group Synchronization (CGS), Initial Lane Synchronization (ILAS), and User Data phase.
  • Page 43 S = Number of samples per converter per frame CF[4:0] HD = High Density data format CF = Number of control words per frame clock per link (16) Applies to Subclass 2 only. JESD204B IP Core Functional Description Altera Corporation Send Feedback...
  • Page 44 SYNC_N will stay in ILAS phase indefinitely until this setting changes. • Link reinitialization through CSR is initiated. The JESD204B IP core transmits /K/ character and causes the RX converter to enter CGS phase. After RX deasserts , the CSR enters ILAS phase SYNC_N and will stay in that phase indefinitely until this setting changes.

  • Page 45: Tx Phy Layer

    The receiver performs the following functions: • Data deserializer • 8B/10B decoding • Lane alignment • Character replacement • Data descrambling JESD204B IP Core Functional Description Altera Corporation Send Feedback...

  • Page 46: Rx Data Link Layer

    RX Data Link Layer The JESD204B IP core RX data link layer buffers incoming user data on all lanes until the RX elastic buffers can be released. Special character substitution are done in the TX link so that the RX link can execute frame and lane alignment monitoring based on the JESD204B specification.
  • Page 47 • Arrival of /A/ character from multiple lanes exceed one multi-frame. • Misalignment detected during user data phase. (17) Dynamic frame realignment and correction is not supported. JESD204B IP Core Functional Description Altera Corporation Send Feedback...
  • Page 48 LMFC boundary. If you want to implement an early release mechanism, program it in the register. The is a counter based on the link clock csr_rbd_offset csr_rbd_offset csr_rbd_count boundary (not frame clock boundary). Therefore, the RBD release opportunity is at every four octets. JESD204B IP Core Functional Description Altera Corporation Send Feedback...

  • Page 49: Rx Phy Layer

    The 8B/10B decoder decode the data after receiving the data through the serial line. The JESD204 IP core supports transmission order from MSB first as well as LSB first. The PHY layer can detect 8B/10B not-in-table (NIT) error and also running disparity error. JESD204B IP Core Functional Description Altera Corporation Send Feedback...

  • Page 50: Operation

    2015.05.04 Operation Operating Modes The JESD204B IP core supports Subclass 0, 1, and 2 operating modes. Subclass 0 The JESD204 IP core maintains a LMFC counter that counts from 0 to (F × K/4)–1 and wraps around again. The LMFC counter starts counting at the deassertion of SYNC_N signal from multiple DACs after synchronization.

  • Page 51: Scrambler/Descrambler

    For Subclass 0, you need to multiplex all the SYNC_N dev_sync_n signals in the same multipoint link and then input them to the IP core through dev_sync_n mdev_sync_n signal. JESD204B IP Core Functional Description Altera Corporation Send Feedback...

  • Page 52: Sync_N Signal

    Setting a different RBD offset to each link or setting an early release does not guarantee deterministic latency and data alignment. JESD204B IP Core Functional Description Altera Corporation...

  • Page 53: Link Reinitialization

    DAC Reference Clock FPGA Reference Clock Clock Chip SYSREF SYSREF and SYSREF Related Information Programmable RBD Offset on page 6-2 Link Reinitialization The JESD204B TX and RX IP core support link reinitialization. JESD204B IP Core Functional Description Altera Corporation Send Feedback...

  • Page 54: Link Startup Sequence

    Link Startup Sequence Set the run-time LMF configuration when the signals are asserted. Upon txlink_rst_n rxlink_rst_n deassertion, the JESD204B IP core begins operation. The following txlink_rst_n rxlink_rst_n sections describe the detailed operation for each subclass mode. TX (Subclass 0) Upon reset deassertion, the JESD204B TX IP core is in CGS phase.

  • Page 55: Error Reporting Through Sync_N Signal

    Clocking Scheme This section describes the clocking scheme for the JESD204B IP core and transceiver. Table 4-3: JESD204B IP Core Clocks Clock Signal Formula Description PLL selection during IP The PLL reference clock used by the TX Transceiver...
  • Page 56 2015.05.04 Clock Signal Formula Description Data rate/40 The timing reference for the JESD204B IP core.The TX/RX Link Clock: link clock runs at data rate/40 because the IP core is operating in a 32-bit data bus architecture after 8B/ txlink_clk 10B encoding.

  • Page 57: Device Clock

    PLL based on the user selection. Note: You need to generate the Altera PLL IP core (in Arria V and Stratix V devices) or Altera IOPLL IP core (in Arria 10 devices) to generate the link clock and frame clock. The link clock is used in the JESD204 IP core (MAC) and the transport layer.

  • Page 58: Link Clock

    The phase offset between the SYSREF to the FPGA and converter devices should be minimal. 2. For Arria 10 devices, the transceiver PLL is outside of the JESD204B IP core. For Arria V and Stratix V devices, the transceiver PLL is part of the JESD204B IP core.

  • Page 59: Local Multi-Frame Clock

    SYSREF. Therefore, you can generate both the link clock and frame clock using direct mode in the Altera PLL IP core. If F = 4, where link clock is the same as...

  • Page 60: Clock Correlation

    The link clock and frame clock are running at the same frequency. You only need to generate one clock from the Altera PLL or Altera IO PLL IP core. For this example, the frame clock may not be able to run up to 1 GHz in the FPGA fabric. The JESD204B...

  • Page 61: Reset Scheme

    • on page 4-22 Reset Scheme All resets in the JESD204B IP core are synchronous reset signals and should be asserted and deasserted synchronously. Note: Ensure that the resets are synchronized to the respective clocks for reset assertion and deassertion.

  • Page 62: Reset Sequence

    • Reset Sequence Altera recommends that you assert reset for the JESD204B IP core and transport layer when powering up the PLLs and transceiver. Refer to the Altera Transceiver PHY IP Core User Guide and Altera Arria 10 Transceiver PHY IP Core...

  • Page 63: Signals

    4. Once the transceiver is out of reset, deassert the AV-MM interface reset for the IP core. At the configu‐ ration phase, the subsystem can program the converter devices through the SPI interface. During this configuration phase, the subsystem may program the JESD204B IP core if the default IP core register settings need to change.

  • Page 64: Transmitter

    (22) Input Reset for the transceiver PMA block. This tx_analogreset[] reset is an active high signal. (22) The Transceiver PHY Reset Controller IP Core controls this signal. JESD204B IP Core Functional Description Altera Corporation Send Feedback...
  • Page 65 Channels) bonded mode for Arria 10 FPGA variants. Signal Width Direction Description Transceiver Interface Output Differential high speed serial output data. The tx_serial_data[] clock is embedded in the serial data stream. JESD204B IP Core Functional Description Altera Corporation Send Feedback...
  • Page 66 This signal is only available if you enable dynamic reconfiguration for Arria 10 FPGA variants. The Avalon-MM address. L*1024 Input reconfig_avmm_ address[] This signal is only available if you enable dynamic reconfiguration for Arria 10 FPGA variants. JESD204B IP Core Functional Description Altera Corporation Send Feedback...
  • Page 67 Lane 0 data is always located in the lower 32-bit data. If more than one lane is instantiated, lane 1 is located at bit[63:32], with the first octet position at bit[63:56]. JESD204B IP Core Functional Description Altera Corporation Send Feedback...
  • Page 68 The Avalon-MM interface clock signal. This jesd204_tx_avs_clk clock is asynchronous to all the functional clocks in the JESD204B IP core. The JESD204B IP core can handle any cross clock ratio and therefore the clock frequency can range from 75 MHz to 125 MHz. Input...
  • Page 69 This signal is asserted by the Avalon-MM slave jesd204_tx_avs_ to indicate that it is unable to respond to a waitrequest read or write request. The JESD204B IP core ties this signal to 0 to return the data in the access cycle. Signal...
  • Page 70 Input Indicates a multidevice synchronization mdev_sync_n request. Synchronize signal combination should be done externally and then input to the JESD204B IP core through this signal. • For subclass 0—combine the dev_sync_n signal from all multipoint links before connecting to the signal.
  • Page 71 Output Indicates which lane is powered down. You csr_lane_powerdown[] need to set this signal if you have configured the link and want to reduce the number of active lanes. JESD204B IP Core Functional Description Altera Corporation Send Feedback...
  • Page 72 Signal Width Direction Description Output Indicates the address space that is reserved for csr_tx_testmode[] DLL testing within the JESD204B IP core. • 0—reserved for the IP core. • 1—program different tests in the transport layer. Refer to register. csr_tx_testmode Output...

  • Page 73: Receiver

    Output Recovered clock signal. This clock is derived from rxphy_clk[] the clock data recovery (CDR) and the frequency depends on the JESD204B IP core data rate. (25) Input Reset for the transceiver PCS block. This reset is an rx_digitalreset[] active high signal.
  • Page 74 This signal is only available if you enable dynamic reconfiguration for Arria 10 FPGA variants. The input data. Input reconfig_avmm_ writedata[] This signal is only available if you enable dynamic reconfiguration for Arria 10 FPGA variants. JESD204B IP Core Functional Description Altera Corporation Send Feedback...
  • Page 75 Indicates an empty data stream due to invalid data. jesd204_rx_frame_error This signal is asserted high to indicate an error during data transfer from the RX core to the transport layer. Signal Width Direction Description Avalon-MM Interface JESD204B IP Core Functional Description Altera Corporation Send Feedback...
  • Page 76 The Avalon-MM interface clock signal. This clock jesd204_rx_avs_clk is asynchronous to all the functional clocks in the JESD204B IP core. The JESD204B IP core can handle any cross clock ratio and therefore the clock frequency can range from 75 MHz to 125 MHz.
  • Page 77 This signal is asserted by the Avalon-MM slave to jesd204_rx_avs_ indicate that it is unable to respond to a read or waitrequest write request. The JESD204B IP core ties this signal to 0 to return the data in the access cycle. Signal Width...
  • Page 78 The transport layer can use this signal as a run-time parameter. Output Indicates the high density data format. The csr_hd transport layer can use this signal as a run-time parameter. JESD204B IP Core Functional Description Altera Corporation Send Feedback...
  • Page 79 Signal Width Direction Description Out-of-band (OOB) Output Interrupt pin for the JESD204B IP core. Interrupt jesd204_rx_int is asserted when any error is detected. Configure register to set the type of error rx_err_enable that can trigger an interrupt. Signal Width...

  • Page 80: Registers

    4-43 Registers 2015.05.04 Registers The JESD204B IP core supports a basic one clock cycle transaction bus. There is no support for burst mode and wait-state feature (the signal is tied to 0). The JESD204B IP core Avalon- avs_waitrequest MM slave interface has a data width of 32 bits and is implemented based on word addressing. The Avalon-MM slave interface does not support byte enable access.
  • Page 81 • Software writes 1 shall set the bit to 1. • Hardware clears the bit to 0, if the bit has been set to 1 by software. • Software set has higher priority than hardware clear. JESD204B IP Core Functional Description Altera Corporation Send Feedback...

  • Page 82: Jesd204B Ip Core Design Guidelines

    Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 83 The list below describes the mechanism of the design example architecture (with reference to the note numbers in the design example block diagram). 1. For multiple links, the JESD204B IP core is instantiated multiple times. For example, in 2x112 (LMF) configuration, two cores are instantiated, where each core is configured at LMF=112.

  • Page 84: Design Example Components

    (AVS clock) is generated from an on-board 100 MHz oscillator. For instance, if the JESD204B IP core is configured at data rate of 6.144 Gbps, transceiver reference clock frequency of 153.6 MHz, and number of octets per frame (F) = 2, the example below indicates the PLL clock frequencies: •...
  • Page 85 The PLL reconfiguration utilizes the ALTERA_PLL_RECONFIG IP core to implement reconfiguration logic to facilitate dynamic real-time reconfiguration of PLLs in Altera devices. You can use this megafunc‐ tion IP core to update the output clock frequency, PLL bandwidth, and phase shifts in real time, without reconfiguring the entire FPGA.
  • Page 86 • Reconfiguration Management Avalon-MM slave interface—connects to the control unit. Note: The transceiver reconfiguration controller is only used in Arria V and Stratix V devices. For Arria 10 devices, the control unit directly communicates with the transceiver in the JESD204B IP core through the interface signals.
  • Page 87 • Transceiver Reset Controller The transceiver reset controller uses the Altera's Transceiver PHY Reset Controller IP Core to ensure a reliable initialization of the transceiver. The reset controller has separate reset controls per channel to handle synchronization of reset inputs, hysteresis of PLL locked status, and automatic or manual reset recovery mode.
  • Page 88 To do a comparison, an initial seed internally generates a set of expected data pattern result to XOR'ed with the input data. The seed is updated only when the enable signal is active, which indicates JESD204B IP Core Design Guidelines Altera Corporation...
  • Page 89 Transport Layer The transport layer in the JESD204B IP core consists of an assembler at the TX path and a deassembler at the RX path. The transport layer provides the following services to the application layer (AL) and the DLL: •...
  • Page 90 Data Bit and Content Mapping Scheme One major function of the transport layer is to arrange the data bits in a specific way between the Avalon- ST interface and the DLL in the JESD204B IP core. Figure 5-2 shows the mapping scheme in the transport layer across various TX to RX interfaces for a specific system configuration.
  • Page 91 [10] (Transport Layer to Avalon-ST Interface) 2nd jesd204_rx_ctrlout[0] (Transport Layer to Avalon-ST Interface) TX Path The assembler in the TX path consists of the tail bits dropping, assembling, and multiplexing blocks. JESD204B IP Core Design Guidelines Altera Corporation Send Feedback...
  • Page 92 Number of octets per frame. 1, 2, 4, 8 Number of control bits or conversion sample. 0–3 Number of conversion bits per converter. 12-16 Number of transmitted bits per sample in the user data format. JESD204B IP Core Design Guidelines Altera Corporation Send Feedback...
  • Page 93 FRAMECLK_DIV, F2_FRAMECLK_DIV and txlink_clk. This clock is synchronous to the txlink_clk signal. Refer to the Table 5-7 to set the desired frame clock frequency with different FRAMECLK_DIV and F (29) values. JESD204B IP Core Design Guidelines Altera Corporation Send Feedback...
  • Page 94 Avalon-ST source interface. ready • 0—transport layer is not ready to receive data • 1—transport layer is ready to receive data Signal Clock Domain Direction Description Between Transport Layer and DLL JESD204B IP Core Design Guidelines Altera Corporation Send Feedback...
  • Page 95 Clock Domain Direction Description CSR in DLL If a JESD device of No Multiple-Converter Device Alignment, Single-Lane (NMCDA-SL) class is deployed, (30) Altera recommends that you tie this input signal to "1". JESD204B IP Core Design Guidelines Altera Corporation Send Feedback...
  • Page 96 Connect this signal to the TX DLL output pin. csr_f[] (31) This signal should be static and valid before the deassertion of the signals. link_rst_n frame_rst_n JESD204B IP Core Design Guidelines Altera Corporation Send Feedback...
  • Page 97 Connect this signal to the TX DLL csr_n[] output pin. TX Path Operation The data transfer protocol between the Avalon-ST interface and the TX path transport layer is data transfer with backpressure, where ready_latency = 0. JESD204B IP Core Design Guidelines Altera Corporation Send Feedback...
  • Page 98 TL when the signal equals to "1" (in user data jesd204_tx_link_ready phase). This means all the data transmitted from the TL before signal equals to jesd204_tx_link_ready "1" are ignored. JESD204B IP Core Design Guidelines Altera Corporation Send Feedback...
  • Page 99 TX link is T0 data followed by T1 data. TX Path Data Remapping The JESD204B IP core implements the data transfer in big endian format. JESD204B IP Core Design Guidelines Altera Corporation...
  • Page 100 5. The data is arranged so that the L0 is always on the right (LSB) in the data bus interfacing with the JESD204B IP core. In big endian implementation, the oldest data (F0) is placed at the MSB in L0. 32- bits or 4 octets of data are transferred to the IP core in one link clock cycle.
  • Page 101 Table 5-6: Data Mapping for F=1, L=4 F = 1 Supported M M*S=2 for F=1, L=4 and S F=1 supports either (case1: M=1, S=2) or (case2: M=2, S=1) JESD204B IP Core Design Guidelines Altera Corporation Send Feedback...
  • Page 102 F=2 supports either (case1: M=1, S=4), (case2: M=2, S=2) or (case3: M=4, S=1) The effective frame clock in the Transport Layer is 4x of the link clock. (32) (33) The effective frame clock in the Transport Layer is same as the link clock. JESD204B IP Core Design Guidelines Altera Corporation Send Feedback...
  • Page 103 = M0S1, M0S0} {F14F15,F12F13, F10F11, Case3: M=4, S=2 {M3S1, M3S0, M2S1, M2S0, M1S1, M1S0, F8F9,F6F7,F4F5, M0S1, M0S0} F2F3,F0F1} Case4: M=8, S=1 {M7S0, M6S0, M5S0, M4S0, M3S0, M2S0, M1S0, M0S0} Lane JESD204B IP Core Design Guidelines Altera Corporation Send Feedback...
  • Page 104 DLL by asserting the signal and jesd204_tx_link_error deasserting the signal accordingly, as shown in the timing diagram below. jesd204_tx_link_data_valid JESD204B IP Core Design Guidelines Altera Corporation Send Feedback...
  • Page 105 0 and byte 1 txframe_clk period txframe_clk — period txframe_clk — period txframe_clk RX Path The deassembler in the RX path consists of the tail bits dropping, deassembling, and multiplexing blocks. JESD204B IP Core Design Guidelines Altera Corporation Send Feedback...
  • Page 106 2015.05.04 Figure 5-9: RX Path Assembler Block Diagram Interfaces with JESD204B IP Core Interface with Data Link Layer and Control Unit Avalon-ST JESD204B Transport Layer RX Block JESD204B IP Core Data Link Layer Data Data Data Data Tail Bits Deassembling...
  • Page 107 Reset for the RX frame clock domain logic in the Input rxframe_rst_n rxframe_clk deassembler. This reset is an active low signal and the deassertion is synchronous to the rising-edge rxframe_clk JESD204B IP Core Design Guidelines Altera Corporation Send Feedback...
  • Page 108 The table below illustrates the data mapping for L = 4: jesd204_rx_link_datain [x:y] Lane [31:0] [63:32] [95:64] [127:96] Connect this signal to the RX DLL jesd204_rx_ output pin. link_data[] JESD204B IP Core Design Guidelines Altera Corporation Send Feedback...
  • Page 109 = "0"). The DLL jesd204_rx_data_ready subsequently reports this error to the CSR block. Connect this signal to the RX DLL jesd204_rx_ input pin. frame_error Signal Clock Domain Direction Description CSR in DLL JESD204B IP Core Design Guidelines Altera Corporation Send Feedback...
  • Page 110 DLL to transport layer. Connect this signal to the RX DLL csr_l[] output pin. (35) This signal should be static and valid before the deassertion of the signals. link_rst_n frame_rst_n JESD204B IP Core Design Guidelines Altera Corporation Send Feedback...
  • Page 111 The data transfer protocol between the Avalon-ST interface and the RX path transport layer is data transfer without backpressure. Therefore, the sink shall always be ready to sample the incoming data whenever data at the source is valid. JESD204B IP Core Design Guidelines Altera Corporation Send Feedback...
  • Page 112 The data can be translated to the frame signal is internally generated in the RX control block to correctly stream data to the (36) f2_div1_cnt Avalon-ST interface. JESD204B IP Core Design Guidelines Altera Corporation Send Feedback...
  • Page 113 Relationship Between Frame Clock and Link Clock on page 5-9 RX Path Data Remapping The JESD204B IP core implements the data transfer in big endian format. The RX path data remapping is the reverse of TX path data remapping. Refer to Figure 5-7for the RX transport layer remapping operation.
  • Page 114 {F12, F13, F14, F15} {F8, F9, F10, F11} {F4, F5, F6, F7} {F0, F1, F2, F3} Supported M*S=4 for F=2, L=4 M and S F=2 supports either (case1: M=1, S=4), (case2: M=2, S=2) or (case3: M=4, S=1) JESD204B IP Core Design Guidelines Altera Corporation Send Feedback...
  • Page 115 {M1S3, M1S2, M1S1, M1S0, M0S3, M0S2, dataout[127:0] = M0S1, M0S0} {F14F15, F12F13,F10F11, Case3: M=4, S=2 {M3S1, M3S0, M2S1, M2S0, M1S1, M1S0, F8F9,F6F7,F4F5, M0S1, M0S0} F2F3,F0F1} Case4: M=8, S=1 {M7S0, M6S0, M5S0, M4S0, M3S0, M2S0, M1S0, M0S0} JESD204B IP Core Design Guidelines Altera Corporation Send Feedback...
  • Page 116 DLL by asserting the signal, as shown in the timing jesd204_rx_link_error diagram below. Figure 5-12: RX Error Reporting rxframe_clk rxlink_clk jesd204_rx_data_ready jesd204_rx_data_valid jesd204_rx_link_error JESD204B IP Core Design Guidelines Altera Corporation Send Feedback...
  • Page 117 W1 and W0 represent the number of data bytes to transfer for either a read or write process. For implementation simplicity, W1 and W0 are always set at 0 in this design JESD204B IP Core Design Guidelines Altera Corporation...
  • Page 118 More information about configuring the ALTIOBUF Megafunction IP Core. Control Unit The control unit has access to the CSR interface of the JESD204B IP core duplex base core, PLL reconfiguration, transceiver reconfiguration controller, and SPI master. The control unit also serves as a clock and reset unit (CRU) for the design example.
  • Page 119 SPI slave. A memory initialization file (MIF) contains the initial values for each address in the memory. Each memory block requires a separate file. The MIF can be created in the Quartus II software text editor tool. JESD204B IP Core Design Guidelines Altera Corporation Send Feedback...
  • Page 120 Perform a read transaction from the next ROM and perform the same SPI write transaction to next SPI slave. 2. Initialize the JESD204B IP base core, transport layer, pattern generator, and pattern checker upon successful initialization of the transceiver. JESD204B IP Core Design Guidelines Altera Corporation Send Feedback...

  • Page 121: System Parameters

    If an N of 12-14 is required, PRBS-7 and PRBS-9 are the only feasible options. If an N of 15-16 is required, PRBS-7, PRBS-9, and PRBS-15 are the only feasible options. (37) Values supported or demonstrated by this design example. JESD204B IP Core Design Guidelines Altera Corporation Send Feedback...
  • Page 122 153.6 153.6 Bonded/Non-bonded 153.6 153.6 153.6 Bonded/Non-bonded 153.6 153.6 153.6 Bonded/Non-bonded 153.6 153.6 153.6 Bonded/Non-bonded 153.6 153.6 153.6 Bonded/Non-bonded 153.6 153.6 153.6 (37) Values supported or demonstrated by this design example. JESD204B IP Core Design Guidelines Altera Corporation Send Feedback...
  • Page 123 RX Base Core LMF = 211, S = 1, LMF = 211, S = 1, M = 1, S = 1, N = 16, N = 16 N = 16 FRAMECLK_DIV = 1 JESD204B IP Core Design Guidelines Altera Corporation Send Feedback...
  • Page 124 FRAMECLK_DIV = 1 Run-Time Reconfiguration The JESD204B IP core supports run-time reconfiguration for the LMF and data rate settings. The design example only demonstrates the following set of configuration. To generate the design example with run-time reconfiguration enabled, the LMF and bonding mode parameters must match the default value listed in the table below.

  • Page 125: System Interface Signals

    Aligns all lanes for this device at the RX path. alldev_lane_aligned link_clk For multidevice synchronization, multiplex all the signals before connecting to this dev_lane_aligned signal pin. For single device support, connect the dev_lane_ signal back to this signal. aligned JESD204B IP Core Design Guidelines Altera Corporation Send Feedback...
  • Page 126 SYNC_N active low signal and is asserted 0 to indicate a 1:0] synchronization request. Instead of reporting the link error through this signal, the JESD204B IP core uses signal to indicate an interrupt. jesd204_rx_int Signal Clock Direction Description...
  • Page 127 Assert high to indicate that the control unit is busy. cu_busy mgmt_clk All reconfiguration input will be ignored when this signal is high. Signal Clock Direction Description Domain Avalon- ST User Data JESD204B IP Core Design Guidelines Altera Corporation Send Feedback...
  • Page 128 Indicates that the transport layer is ready to accept avst_usr_din_ready frame_ data from the Avalon-ST source interface. • 0—transport layer is not ready to receive data • 1—transport layer is ready to receive data JESD204B IP Core Design Guidelines Altera Corporation Send Feedback...
  • Page 129 Indicates that the Avalon-ST sink interface is ready avst_usr_dout_ready frame_ to accept data from the transport layer. • 0—Avalon-ST sink interface is not ready to receive data • 1—Avalon-ST sink interface is ready to receive data JESD204B IP Core Design Guidelines Altera Corporation Send Feedback...

  • Page 130: Example Feature: Dynamic Reconfiguration

    1:0] or synchronization request is detected. Example Feature: Dynamic Reconfiguration The JESD204B IP core design example demonstrates dynamic (run-time) reconfiguration of either the LMF or data rate, at any one time. Dynamic Reconfiguration Operation The dynamic reconfiguration feature implements various reconfiguration controller modules such as PLL reconfiguration, Transceiver Reconfiguration Controller, SPI master, and JESD204B IP core Avalon-MM slave.
  • Page 131 Figure 5-19: Dynamic Reconfiguration Block Diagram (For 28 nm Device Families—Stratix V and Arria JESD204B IP Core (Duplex) Transceiver Avalon-MM PHY MIF Reconfiguration Controller Avalon-MM Avalon-MM Control Unit Clock MIF Reconfiguration Avalon-MM Avalon-MM SPI Master PLL MIF JESD MIF ADC MIF DAC MIF JESD204B IP Core Design Guidelines Altera Corporation Send Feedback...
  • Page 132 MIF files. Then, merge the files into one (core_pll.mif). Only the PLL with maximum configuration is used in final compilation. Maximum Configuration MIF WIDTH=32; DEPTH=92; ADDRESS_RADIX=UNS; JESD204B IP Core Design Guidelines Altera Corporation Send Feedback...
  • Page 133 CONTENT BEGIN 0000000000100001; -- Start of MIF opcode (TX_PLL, 6144Mbps) 0000000000100010; 0011000000000000; 0000000000011111; -- End of MIF opcode Maximum Channel Configuration MIF 0000000000100001; -- Start of MIF opcode (Channel, 6144Mbps) 0000000000000010; JESD204B IP Core Design Guidelines Altera Corporation Send Feedback...
  • Page 134 102FF71; -- Start of MIF 103BF01; 1047F04; 1054700; 11AFF00; 11CE020; 11DE020; 3FFFFFF; -- End of MIF Downscale Channel Configuration MIF 102FF71; -- Start of MIF 103BF01; 1047F04; 1054700; 11AFF00; 11CE020; 11DE020; JESD204B IP Core Design Guidelines Altera Corporation Send Feedback...
  • Page 135 0000000000000001; -- L (maximum config) 0000000000000001; -- M 0000000000000001; -- F 1111111111111111; -- End of MIF [4..7] 0000000000000000; Downscale Configuration MIF 0000000000000000; -- L (downscale config) 0000000000000000; -- M 0000000000000001; -- F JESD204B IP Core Design Guidelines Altera Corporation Send Feedback...

  • Page 136: Generating And Simulating The Design Example

    -- End of MIF 95..127] 00000000000000000000000000000000; END; Generating and Simulating the Design Example To use the JESD204B IP core design example testbench, follow these steps: 1. Generate the design example simulation testbench. Refer to Generating the Design Example Simulation Model on page 5-55 2.

  • Page 137: Generating The Design Example For Compilation

    By default, the Quartus II software generates simulator-specific scripts containing commands to compile, elaborate, and simulate Altera IP models and simulation model library files. You can copy the commands into your simulation testbench script, or edit these files to add commands for compiling, elaborating, and simulating your design and testbench.

  • Page 138: Compiling The Jesd204B Ip Core Design Example

    UG-01142 5-57 Compiling the JESD204B IP Core Design Example 2015.05.04 To run the Tcl script using the Quartus II sofware, follow these steps: 1. Launch the Quartus II software. 2. On the View menu, click Utility Windows and select Tcl Console.

  • Page 139: Jesd204B Ip Core Deterministic Latency Implementation Guidelines

    Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 140: Programmable Rbd Offset

    LMFC boundary. In this scenario, you need to configure the RBD offset correctly to avoid lane de-skew error as indicated in bit 4 of register. rx_err0 JESD204B IP Core Deterministic Latency Implementation Guidelines Altera Corporation Send Feedback...
  • Page 141 1 link clock or LMFC count to cater for power cycle variation Aligned outputs on all lanes RBD Elastic Buffers Released Set csr_rbd_offset = 1 JESD204B IP Core Deterministic Latency Implementation Guidelines Altera Corporation Send Feedback...
  • Page 142 RBD offset is one of the techniques to overcome this issue. Not every RBD offset value is legal. Figure below illustrates the technique to decide the legal RBD offset value. JESD204B IP Core Deterministic Latency Implementation Guidelines Altera Corporation...

  • Page 143: Programmable Lmfc Offset

    RX LMFC offset using the csr_lmfc_offset field in the register. This is an alternative to using csr_rbd_offset to achieve deterministic syncn_sysref_ctrl latency. JESD204B IP Core Deterministic Latency Implementation Guidelines Altera Corporation Send Feedback...
  • Page 144 1 link clock or LMFC count LMFC boundary is to cater for power cycle variation at new location delayed by 3 link clock Latest arrival lane in multiple power cycles JESD204B IP Core Deterministic Latency Implementation Guidelines Altera Corporation Send Feedback...
  • Page 145 Latest arrival lane in multiple power cycles You can use the TX LMFC offset to align the LMFC counter in IP core to the LMFC counter in DAC. JESD204B IP Core Deterministic Latency Implementation Guidelines Altera Corporation Send Feedback...
  • Page 146 5. The LMFC phase offset is ~3.5 link clock cycles. 6. The DAC deasserts SYNC_N at the LMFC boundary. 7. SYNC_N deassertion is detected by the JESD204B IP core. 8. Because SYNC_N deassertion is detected after the second LMFC boundary at the FPGA, ILAS transmission begins at the third LMFC boundary.
  • Page 147 5. The LMFC boundary is delayed by 4 link clock. 6. The DAC deasserts SYNC_N at the LMFC boundary. 7. SYNC_N deassertion is detected by the JESD204B IP core. 8. Because LMFC boundary is delayed by 4 link clock, the IP core detects the SYNC_N deassertion before the second LMFC boundary.

  • Page 148: Jesd204B Ip Core Debug Guidelines

    Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 149: Spi Programming

    "0", missing or extra bits in a MIF content row. Check these items: • For example, in the ADI AD9250 converter, Altera recommends that you first perform register bit setting for the scramble (SCR) or lane (L) register at address 0x6E before setting the quick configura‐...

  • Page 150: Debugging Jesd204B Link Using Signaltap Ii And System Console

    The SignalTap II and system console are very useful tools in debugging the JESD204B link related issues. To use the system console, your design must contain a Qsys subsystem with the JTAG-to-Avalon-MM Master bridge component and the Merlin slave translator ports that connect to the JESD204B IP core Avalon-MM interface.
  • Page 151 • sync_n • tx_dev_sync_n • mdev_sync_n • jesd204_tx_int Altera recommends that you verify the JESD204B functionality by accessing the DAC SPI registers or any debug feature provided by the DAC manufacturer. JESD204B IP Core Debug Guidelines Altera Corporation Send Feedback...
  • Page 152 Device lanes alignment is achieved. In this example, there is only one device, the dev_lane_aligned connects to and both signals are asserted together. alldev_lane_aligned k. Start of user data phase where user data is streamed through the JESD204B link JESD204B IP Core Debug Guidelines Altera Corporation Send Feedback...
  • Page 153 You can verify the user data arrangement (shown in jesd204_tx_link_error the data mapping tables in the TX Path Data Remapping on page 5-18) by referring to the bus. jesd204_tx_datain JESD204B IP Core Debug Guidelines Altera Corporation Send Feedback...
  • Page 154 AN 696: Using the JESD204B MegaCore Function in Arria V Devices More information about the performance and interoperability of the JESD204B IP core. AN 729: Implementing JESD204B IP Core System Reference Design with Nios II Processor As • Control Unit Altera Transceiver PHY IP Core User Guide •...

  • Page 155: Additional Information

    Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 156 Version Changes December 2014.12.15 • Updated the JESD204B IP Core FPGA Performance table with the 2014 data rate range. • Updated the JESD204B IP Core FPGA Resource Utilization table. • Updated the JESD204B IP Core Parameters table with the following changes: •...

  • Page 157: How To Contact Altera

    Table 8-1: Altera Contact Information (39) Contact Contact Method Address Technical support Website www.altera.com/support Website www.altera.com/training Technical training Email custrain@altera.com Product literature Website www.altera.com/literature (39) You can also contact your local Altera sales office or sales representative. Additional Information Altera Corporation Send Feedback...
  • Page 158 Contact Contact Method Address General Email nacomp@altera.com Nontechnical support Software licensing Email authorization@altera.com Related Information www.altera.com/support • • www.altera.com/training • www.altera.com/literature (39) You can also contact your local Altera sales office or sales representative. Additional Information Altera Corporation Send Feedback...

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