Altera JESD204B IP CORE Serial Interface Manuals

Manuals and User Guides for Altera JESD204B IP CORE Serial Interface. We have 2 Altera JESD204B IP CORE Serial Interface manuals available for free PDF download: User Manual

Altera JESD204B IP CORE User Manual (158 pages)

Brand: Altera | Category: Network Card | Size: 2.96 MB

Table of Contents
2
JESD204B IP Core Quick Reference

4
About the JESD204B IP Core

6
- Datapath Modes
  8
- IP Core Variation
  8
- JESD204B IP Core Configuration
  9
  - Run-Time Configuration
    9
- Channel Bonding
  10
- Performance and Resource Utilization
  11
Getting Started

15
JESD204B IP Core Functional Description

38
- Transmitter
  41
  - TX Data Link Layer
    42
  - TX PHY Layer
    45
- Receiver
  45
  - RX Data Link Layer
    46
  - RX PHY Layer
    49
- Operation
  50
  - Operating Modes
    50
  - Scrambler/Descrambler
    51
  - SYNC_N Signal
    52
  - Link Reinitialization
    53
  - Link Startup Sequence
    54
  - Error Reporting through SYNC_N Signal
    55
- Clocking Scheme
  55
  - Device Clock
    57
  - Link Clock
    58
  - Local Multi-Frame Clock
    59
  - Clock Correlation
    60
- Reset Scheme
  61
  - Reset Sequence
    62
- Signals
  63
  - Transmitter
    64
  - Receiver
    73
- Registers
  80
  - Register Access Type Convention
    80
JESD204B IP Core Design Guidelines

82
- JESD204B IP Core Design Example
  82
JESD204B IP Core Deterministic Latency Implementation Guidelines

139
- Constraining Incoming SYSREF Signal
  139
- Programmable RBD Offset
  140
- Programmable LMFC Offset
  143
JESD204B IP Core Debug Guidelines

148
- Clocking Scheme
  148
- JESD204B Parameters
  148
- SPI Programming
  149
- Converter and FPGA Operating Conditions
  149
- Signal Polarity and FPGA Pin Assignment
  149
- Debugging JESD204B Link Using Signaltap II and System Console
  150
Additional Information

155
- JESD204B IP Core Document Revision History
  155
- How to Contact Altera
  157

Altera JESD204B IP CORE User Manual (113 pages)

IP Core

Brand: Altera | Category: Recording Equipment | Size: 3.03 MB

Table of Contents
2
JESD204B IP Core Quick Reference

4
About the JESD204B IP Core

7
- Datapath Modes
  9
- IP Core Variation
  9
- JESD204B IP Core Configuration
  10
  - Run-Time Configuration
    10
- Channel Bonding
  11
- Performance and Resource Utilization
  12
Getting Started

17
JESD204B IP Core Functional Description

41
- Transmitter
  44
  - TX Data Link Layer
    45
  - TX PHY Layer
    48
- Receiver
  48
  - RX Data Link Layer
    49
  - RX PHY Layer
    52
- Operation
  53
  - Operating Modes
    53
  - Scrambler/Descrambler
    54
  - SYNC_N Signal
    55
  - Link Reinitialization
    56
  - Link Startup Sequence
    57
  - Error Reporting through SYNC_N Signal
    58
- Clocking Scheme
  58
  - Device Clock
    61
  - Link Clock
    63
  - Local Multi-Frame Clock
    64
  - Clock Correlation
    65
- Reset Scheme
  66
- Signals
  71
  - Transmitter
    71
  - Receiver
    80
- Registers
  88
  - Register Access Type Convention
    88
JESD204B IP Core Deterministic Latency Implementation Guidelines

90
JESD204B IP Core Debug Guidelines

100
JESD204B IP Core Document Archives

108
JESD204B IP Core Document Revision History

109

Altera Categories

Motherboard Microcontrollers Computer Hardware Transceiver Cables and connectors

More Altera Manuals

Altera JESD204B IP CORE Serial Interface Manuals

Altera JESD204B IP CORE User Manual (158 pages)

Table of Contents

JESD204B IP Core Quick Reference

About the JESD204B IP Core

Getting Started

JESD204B IP Core Functional Description

JESD204B IP Core Design Guidelines

JESD204B IP Core Deterministic Latency Implementation Guidelines

JESD204B IP Core Debug Guidelines

Additional Information