Silicon Laboratories C8051F336 User Manual page 12

C8051F336/7/8/9
5.11. Target Board Pin Assignment Summary
Some GPIO pins of the C8051F338 MCU can have an alternate fixed function. For example, pin 22 on the 'F338
MCU is designated P0.4, and can be used as a GPIO pin. Also, if the UART0 peripheral on the MCU is enabled
using the crossbar registers, the TX signal is routed to this pin. This is shown in the "Alternate Fixed Function"
column. The "Target Board Function" column shows that this pin is used as TX on the 'F338 Target Board. The
"Relevant Headers" column shows that this signal is routed to pin 7 of the J1 header and pin 5 of the J3 header.
More details can be found in the C8051F336/7/8/9 data sheet. Some of the GPIO pins of the C8051F338 have
been used for various functions on the target board. Table 6 summarizes the MCU pin assignments on the target
board, and also shows the various headers associated with each signal.
Table 6. C8051F338 Target Board Pin Assignments and Headers
MCU Pin Name Pin#
P0.0 2
P0.1 1
P0.2 24
P0.3 23
P0.4 22
P0.5 21
P0.6 20
P0.7 19
P1.0 18
P1.1 17
P1.2 16
P1.3 15
P1.4 14
P1.5 13
P1.6 12
P1.7 11
P2.0 10
P2.1 9
P2.2 8
P2.3 7
P2.4/C2D 6
/RST/C2CK 5
VDD 4
GND 3
*Note: Headers denoted by this symbol are not directly connected to the MCU pin; the connection might be via one or more
headers and/or pin-sharing resistor(s). See board schematic for details.
12
Primary Alternate Fixed
Function Function
P0.0 VREF
P0.1 IDAC
P0.2 XTAL1
P0.3 XTAL2
P0.4 TX_MCU
P0.5 RX_MCU
P0.6 CNVSTR
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4 C2D
/RST C2CK
VDD
GND
Rev. 0.3
Target Board Relevant Headers
Function
VREF J1[3], TB1[6]*, J5[1]
IDAC J1[4], J1[2]*, TB1[2], J6[1]
XTAL1 J1[5]*, J9[2]
XTAL2 J1[6]*, J10[2]
TX_MCU
RX_MCU
CNVSTR J1[9], TB1[1]
SW2 (switch) J1[10], J3[3]
CP0A J1[11], J11[1]
RTS J1[12], J3[9]
CTS J1[13], J3[11]
LED J1[14], J3[1]
AIN J1[15], TB1[4]
AIN J1[16], TB1[3]
POT J1[17], J8[1]
GPIO
CP0+ J1[19], J11[3]
CP0- J1[20], J11[5]
GPIO
T0 J1[22], J11[7]
P2.4/C2D J1[23]*, J4[6]*, J4[4]
/RST/C2CK J1[24]*, J4[5]*, J4[7]
VDD
GND J1[25], J1[26], TB1[5]
J1[7], J3[5]
J1[8], J3[7]
J1[18]
J1[21]
J2[2]