Vertex Standard VX-350 Series Service Manual page 7

Circuit Description
3-2. Drive and Final amplifier
The modulated signal from the VCO Q1049 (2SC4227) is buff-
ered by Q1042 (2SC5005) and amplified by Q1031
(2SC5005). Then the signal is buffered by Q1026 (2SC3356)
for the final amplifier driver Q1020 (RD01MUS1). The low-
level transmit signal is then applied to Q1013 (RD12MP1) for
final amplification up to 5 watts output power. The transmit
signal then passes through the antenna switch D1002 (RLS135)
and is low pass filtered to suppress away harmonic spurious
radiation before delivery to the antenna.
3-3. Automatic Transmit Power Control
The current detector Q1064-1 (BA2902FV) detects the cur-
rent of Q1013 and Q1020, and converts the current difference
to the voltage difference. The output from the current detector
Q1064-1 is compared with the reference voltage and amplified
by the power control amplifier Q1064-2. The output from
Q1064-2 controls the gate bias of the final amplifiers Q1013
and the final amplifier driver Q1020. The reference voltage
changes into four values (Transmit Power High and Low) con-
trolled by Q1017-CH7 (M62364FP).
3-4. PLL Frequency Synthesizer
The frequency synthesizer consists of PLL IC, Q1059
(SA7025DK), VCO, TCXO (X1002) and buffer amplifier. The
output frequency from TCXO is 16.8MHz and the tolerance is
±2.5 ppm (in the temperature range –30 to +60 degrees).
3-4-1. VCO
While the radio is receiving, the RX oscillator Q1046 in VCO
generates a programmed frequency between 184.85 and 224.85
MHz as 1st local signal. While the radio is transmitting, the TX
oscillator Q1049 in VCO generates a frequency between 134
and 174 MHz. The output from oscillator is amplified by buffer
amplifier Q1042 and becomes output of VCO. The output from
VCO is divided, one is amplified by Q1052 and feed back to
the PLL IC 5 pin. The other is amplified in Q1031 and in case
of the reception, it is put into the mixer as the 1st local signal
through D1019, in transmission, it is buffered Q1026, and more
amplified in Q1020 through D1019 and it is put into the final
amplifier Q1013.
VX-350 Series VHF Band Service Manual
3-4-2. VC0 Tuning Voltage
Tuning voltage of VCO is expanding the lock range of VCO by
controlling the cathode of varactor diode at the voltage and the
control voltage from PLL IC. The control voltage is added to
the anode of varactor diode after converted to by Q1069-1
(BA2904) which is output voltage of D/A converter Q1017-
CH5.
3-4-3. PLL
The PLL IC consists of reference divider, main divider, phase
detector, charge pumps and fractional accumulator. The refer-
ence frequency from TCXO is inputted to 8 pin of PLL IC and
is divided by reference divider. This IC is decimal point divid-
ing PLL IC and the dividing ratio becomes 1/8 of usual PLL
frequency step. Therefore, the output of reference divider is 8
times of frequencies of the channel step. For example, when
the channel stepping is 5 kHz, the output of reference divider
becomes 40 kHz. The other hand, inputted feed back signal to 5
pin of PLL IC from VCO is divided with the dividing ratio
which becomes same frequency as the output of reference di-
vider. These two signals are compared by phase detector, the
phase difference pulse is generated. The phase difference pulse
and the pulse from fractional accumulator pass through the
charge pumps and LPF. It becomes the DC voltage to control
the VCO. The oscillation frequency of VCO is locked by the
control of this DC voltage. The PLL serial data from CPU is
sent with three lines of SDO (64 pin), SCK (1 pin) and PSTB
(32pin). The lock condition of PLL is output from the UL (18
pin) terminal and UL becomes "H" at the time of the lock con-
dition and becomes "L" at the time of the unlocked condition.
The CPU always watches over the UL condition, and when it
becomes "L" unlocked condition, the CPU prohibits transmit-
ting and receiving.
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