Delays Register; Scaler Readout Frequency Register; User Led And Nim Output Selectors - Wiener CC-USB User Manual

Full-featured camac crate controller
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The BuffOpt bits (0-2) define the output buffer length. Bit 3 controls the mode of buffer
filling, such that 0 closes buffers at event boundaries and 1 allows spreading events across
the adjacent buffers:
BuffOpt Value
0
1
2
3
4
5
6
7
The EvtSepOpt set the number of event terminator word (hexadecimal FFFF), such that
EvtSepOpt=0/1 cause one/two terminator word/s written at the end of each event.
The HeaderOpt bit controls the structure of the buffer header, such that HeaderOpt=0 writes
out one header word identifying the buffer type (bit 15=1 – watchdog buffer, bit 14=0 – data
buffer, bit 14=1 – scaler buffer) and the number of events in buffer. When HeaderOpt = 1,
the second header word is written out listing the number of words in the buffer.
The WdgFreq bits define the frequency at which the watchdog is forcing writing of output
buffer during data acquisition. The three bit number represents the time interval in seconds,
counting from the end of an event, after which the watchdog triggers when no new event has
been observed.
The Arbitr Bit, when set to 1 activates CAMAC bus arbitration.

3.1.3 Delays Register

The delays register stores the desired trigger delay (from the start signal applied to the NIM
input to the actual start of the CAMAC readout) – least significant 8 bits and the LAM
timeout period – most significant 8 bits. Both delays are in units of us.

3.1.4 Scaler Readout Frequency Register

The Scaler Readout Frequency Register stores the number defining the frequency at which
scalers are to be read out (scaler stack is executed) during the data acquisition. The stored
value is equal to the number of data events separating the scaler readout events. When the
value is zero, scaler readout is suppressed.

3.1.5 User LED and NIM Output Selectors

Numbers stored in these registers identify sources of User LEDs and NIM Outputs. The
actual selection of sources is firmware specific and subject to customization. The general bit
composition of the selector word is shown in the table below
WIENER, Plein & Baus GmbH
Buffer Length (words)
4096
2048
1024
512
256
128
64
Single Event
13
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