Denon DRA-F107 Service Manual page 41

V
SoftS
5.3V
T
Soft-Start
V
FB
4.8V
V
OUT
V
OUT
T
Start-Up
Figure 14 Start Up Phase
3.4 Oscillator and Frequency
Reduction
3.4.1 Oscillator
The oscillator generates a frequency f
100kHz. A resistor, a capacitor and a current source
and current sink which determine the frequency are
integrated. The charging and discharging current of the
implemented oscillator
trimmed, in order to achieve a very accurate switching
frequency. The ratio of controlled charge to discharge
current is adjusted to reach a max. duty cycle limitation
of D =0.72.
max
3.4.2 Frequency Reduction
The frequency of the oscillator is depending on the
voltage at pin FB. The dependence is shown in Figure
15. This feature allows a power supply to operate at
lower frequency at light loads thus lowering the
switching losses while maintaining good cross
regulation performance and low output ripple. In case
of low power the power consumption of the whole
SMPS can now be reduced very effective. The minimal
reachable frequency is limited to 20kHz/21.5 kHz to
avoid audible noise in any case.
t
t
t
= 67kHz/
switch
capacitor are internally
DRA-F107 / DRA-F107DAB
kHz
100
65
21.5
1.0 1.1 1.2 1.3
ICE2Axxxx ICE2Bxxxx
100kHz
f
norm
21.5kHz
f
standby
Figure 15 Frequency Dependence
3.5 Current Limiting
There is a cycle by cycle current limiting realized by the
Current-Limit Comparator to provide an overcurrent
detection. The source current of the integrated
TM
CoolMOS is sensed via an external sense resistor
R . By means of R
Sense
transformed to a sense voltage V
voltage V exceeds the internal threshold voltage
Sense
V the Current-Limit-Comparator immediately turns
csth
off the gate drive. To prevent the Current Limiting from
distortions caused by leading edge spikes a Leading
Edge Blanking is integrated at the Current Sense.
Furthermore a Propagation Delay Compensation is
added to support the immediate shut down of the
CoolMOS™ in case of overcurrent.
3.5.1 Leading Edge Blanking
V
Sense
V
csth
Figure 16 Leading Edge Blanking
Each time when CoolMOS™ is switched on a leading
spike is generated
capacitances and secondary-side rectifier reverse
recovery time. To avoid a premature termination of the
switching pulse this spike is blanked out with a time
constant of t = 220ns. During that time the output of
LEB
41
Functional Description
1.4 1.5 1.6 1.7 1.8 1.9 2.0
V
V
FB
67kHz
20kHz
the source current is
Sense
. When the
Sense
t = 220ns
LEB
due to the primary-side
t