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Bit 7 (BUSY)
The busy bit is set when the device has access to the command buffer and registers
and the host is locked out from accessing the command register and buffer. No other
bits in this register are valid when this bit is set to a 1.
Bit 6 (RDY)
RDY indicates whether the device is capable of performing operations requested by the
host. This bit is cleared at power up and remains cleared until the device is ready to
accept a command.
Bit 5 (DWF)
This bit, if set, indicates a write fault has occurred.
Bit 4 (DSC)
This bit is set when the device is ready.
Bit 3 (DRQ)
The Data Request is set when the device requires that information be transferred
either to or from the host through the Data register.
Bit 2 (CORR) This bit is set when a Correctable data error has been encountered and the data has
been corrected. This condition does not terminate a multi-sector read operation.
Bit 1 (IDX)
This bit is always set to 0.
Bit 0 (ERR)
This bit is set when the previous command has ended in some type of error. The bits in
the Error register contain additional information describing the error.
5.1.10. Device Control Register
This register is used to control the drive interrupt request and to issue an ATA soft reset to
the drive. The bits are defined as follows:
D7
D6
HOB
X
Bit 7
This bit is used in 48-bit addressing mode. When cleared, the host can read the most recently
written values of the Sector Count,Drive/Head and LBA registers. When set, the host will read
the previous written values of these registers. A write to any Command block register will
clear this bit.
Bit 6
This bit is an X (Do not care).
Bit 5
This bit is an X (Do not care).
Bit 4
This bit is an X (Do not care).
Bit 3
This bit is ignored by the drive.
Bit 2 (SW Rst) This bit is set to 1 in order to force the drive to perform an AT Disk controller Soft Reset
operation. The drive remains in Reset until this bit is reset to '0'.
Bit 1 (-IEn)
The Interrupt Enable bit enables interrupts when the bit is 0. When the bit is 1,
interrupts from the drive are disabled. This bit is set to 0 at power on and Reset.
Bit 0
This bit is ignored by the drive.
5.1.11. Drive Address Register
This register is provided for compatibility with the AT disk drive interface. It is recommended
that this register not be mapped into the host's I/O space because of potential conflicts on
Bit 7. The bits are defined as follows:
D7
D6
X
-WTG
Bit 7
This bit is unknown.
Implementation Note:
Cactus Technologies Limited
Cactus Technologies, Limited
D5
D4
X
X
D5
D4
-HS3
-HS2
OEM Grade -245S Series mSATA SSD Product Manual
D3
D2
1
SW Rst
D3
D2
-HS1
-HS0
D1
D0
-IEn
0
D1
D0
-nDS1
-nDS0
v1.2
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