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NXP Semiconductors MKW01Z128 Reference Manual

Sub 1 ghz low power transceiver plus microcontroller

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MKW01Z128

Sub 1 GHz Low Power Transceiver plus Microcontroller

Reference Manual

Document Number: MKW01xxRM

Rev. 3

04/2016

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Summary of Contents for NXP Semiconductors MKW01Z128

Page 1 MKW01Z128 Sub 1 GHz Low Power Transceiver plus Microcontroller Reference Manual Document Number: MKW01xxRM Rev. 3 04/2016...
Page 2: Table Of Contents
Chapter 1 MKW01Z128 Introduction and Chip Configuration KW01 family introduction ........... . . 1-2 Ordering information .
Page 3 Debug Port Pin Descriptions..........4-13 MKW01Z128 GPIO (Mixed I/O from Transceiver and MCU) ......4-13 4.5.1...
Page 4 5.5.2 CLKOUT Output ............5-3 5.5.3 PLL Architecture .
Page 5 Automatic Sequencer and Wake-Up Times ........6-1 6.2.1 Transmitter Startup Time .
Page 6 Chapter 8 MKW01Z128 Transceiver - MCU SPI Interface SiP Level SPI Pin Connections..........8-1 Features .
Page 7 MKW01xxRM Reference Manual, Rev. 3, 04/2016 viii Freescale Semiconductor, Inc.
Page 8 Chapter 2 • Updated Figure 2-1. MKW01Z128 pinout • Updated Table 2-1. Pin Function Description • Updated description of pin # 58 in Table 2-2 MKW01Z128 Internal Functional Interconnects. Chapter 3 • Updated Table 3-2 Reset State of PORTx_PCRn Register Bit Fields.
Page 9 Definitions, Acronyms, and Abbreviations The following list defines the acronyms and abbreviations used in this document. Acknowledgement Frame Application Programming Interface Baseband Clear Channel Assessment Cyclical Redundancy Check Differential Chip Decoding Device Management Entity Frame Check Sequence Full Function Device FFD-C Full Function Device Coordinator Frame Length Indicator...
Page 10: References
Serial Peripheral Interface SSCS Service Specific Convergence Layer Software Voltage Controlled Oscillator References The following sources were referenced to produce this book: [1] IEEE 802.15.4 Standard MKW01xx [2] Freescale Data Sheet MKW01xxRM Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 11 MKW01xxRM Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 12: Mkw01Z128 Introduction And Chip Configuration
Chapter 1 MKW01Z128 Introduction and Chip Configuration Kinetis is the most scalable portfolio of low power, mixed-signal ARM®Cortex™ MCUs in the industry. Kinetis MCU families are peripheral- and software-compatible devices. Each family offers excellent performance, memory and feature scalability with common peripherals, memory maps, and packages providing easy migration both within and between families.
Page 13: Kw01 Family Introduction
MKW01Z128 Introduction and Chip Configuration — Fast, high precision 16-bit ADCs, 12-bit DACs, high speed comparators and an internal voltage reference. Powerful signal conditioning, conversion and analysis capability with reduced system cost • Human Machine Interface (HMI): — Capacitive Touch Sensing Interface with full low-power support and minimal current adder when enabled •...
Page 14: General Platform Features
MKW01Z128 Introduction and Chip Configuration Table 1-2. Devices in the MKW01 Family Operating Temp Device Package Memory Options Description Range (TA.) MKW01Z128CHN –40° to 85° C 60 LGA 16 KB RAM, The primary target market is communications for 128 KB flash last mile metering, sub metering and associated devices such as concentrators.
Page 15: Rf Transceiver Features
Packet engine with CRC, AES-128 encryption and 66-byte FIFO • Built-in temperature sensor and Low battery indicator • 32 MHz (typical) crystal oscillator clock source Software solutions Freescale will support the MKW01Z128 platform with several software solutions: MKW01xxRM Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 16: System Overview
MKW01Z128 Introduction and Chip Configuration • A radio utility GUI will be available that allows testing of various features and setting registers. A firmware-based connectivity test will allow a limited set of testing controlled with a terminal emulator on any computer.
Page 17 MKW01Z128 Introduction and Chip Configuration Figure 1-1. MKW01 system level block diagram MKW01xxRM Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 18: Transceiver Overview
MKW01Z128 Introduction and Chip Configuration 1.7.1 Transceiver overview The transceiver (see Figure 1-1) is a single-chip integrated circuit ideally suited for today's high performance ISM band RF applications. Its advanced features set, including state of the art packet engine, greatly simplifies system design while the high level of integration reduces the external RF component bill of material (BOM) to a handful of passive de-coupling and matching components.
Page 19: Arm Cortex-M0 Core Modules
MKW01Z128 Introduction and Chip Configuration Table 1-3. Module functional categories Module category Description ARM Cortex-M0+ core System • System integration module • Power management and mode controllers — Multiple power modes available based on run, wait, stop, and powerdown modes •...
Page 20: System Modules
MKW01Z128 Introduction and Chip Configuration Table 1-4. Core modules Module Description ARM Cortex-M0+ The ARM Cortex-M0+ is the newest member of the Cortex M Series of processors targeting microcontroller applications focused on very cost sensitive, deterministic, interrupt driven environments. The Cortex M0+ processor is based on the ARMv6 Architecture and Thumb®-2 ISA and is 100% instruction set compatible with its...
Page 21: Memories And Memory Interfaces
MKW01Z128 Introduction and Chip Configuration Table 1-5. System modules (continued) Module Description Direct memory access (DMA) The DMA controller provides programmable channels with transfer control descriptors for controller data movement via dual-address transfers for 8-, 16- and 32-bit data values.
Page 22: Analog Modules
MKW01Z128 Introduction and Chip Configuration 1.7.2.7 Analog modules The following analog modules are available on this device. Table 1-9. Analog Modules Module Description 16-bit analog-to-digital converters 16-bit successive-approximation ADC (ADC) Internal analog comparators Compares two analog input voltages, one of which can be a reference provided by the internal 6-bit DAC, across the full range of the supply voltage.
Page 23: Communication Interfaces
MKW01Z128 Introduction and Chip Configuration 1.7.2.10 Communication interfaces The following wired communication interfaces are available on this device. Table 1-12. Communication interfaces Module Description Internal serial peripheral interface Synchronous serial bus for communication to an external device (SPI) Inter-integrated circuit (I2C) Allows communication between a number of devices.
Page 24: Mkw01Z128 Pins And Connections
Chapter 2 MKW01Z128 Pins and Connections Device pin assignment Figure 2-1. MKW01Z128 pinout MKW01xxRM Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 25: Pin Definitions
MKW01Z128 Pins and Connections Pin definitions Table 2-1 details the MKW01Z128 pinout and functionality. Table 2-1. Pin Function Description (Sheet 1 of 5) Pin # Pin Name Type Description Functionality VREFH Input MCU high reference voltage for ADC VREFL Input...
Page 26 MKW01Z128 Pins and Connections Table 2-1. Pin Function Description (Sheet 2 of 5) Pin # Pin Name Type Description Functionality PTA2/TSI0_CH3/UART0_TX/ Digital Input / MCU Port A Bit 2/Touch Screen Interface TPM2_CH1 Output Channel 3/UART module 0 Transmit / TPM...
Page 27 MKW01Z128 Pins and Connections Table 2-1. Pin Function Description (Sheet 3 of 5) Pin # Pin Name Type Description Functionality PTC3/LLWU_P7/UART1_RX/ Digital Input / MCU Port C Bit 3 / Low Leakage Wake Up TPM0_CH2/CLKOUTa Output Port 7 / UART module 1 Receive / TPM...
Page 28 MKW01Z128 Pins and Connections Table 2-1. Pin Function Description (Sheet 4 of 5) Pin # Pin Name Type Description Functionality VR_ANA (RF) Power Transceiver regulated output voltage for Decouple to ground with Output analog circuitry. 100 nF capacitor VR_DIG (RF)
Page 29: Internal Functional Interconnects
SPI1 is intended for applications usage. SPI0 is dedicated to the radio interface and should not be used for applications. Table 2-2. MKW01Z128 Internal Functional Interconnects Transceiver Pin #...
Page 30 MKW01Z128 Pins and Connections Table 2-2. MKW01Z128 Internal Functional Interconnects Transceiver Pin # MCU Signal Description Signal MISO/PTC7/SPI0_ MISO SPI data from transceiver to MCU MISO/SPI0_MOSI NSS/PTD0/SPI0_ PTD0 programmed as SPI chip select PCS0 SCK/PTC5/SPI0_ SPI Clock MOSI/PTC6/SPI0_ MOSI SPI data from MCU to transceiver...
Page 31 MKW01Z128 Pins and Connections MKW01xxRM Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 32: Chapter 3 Signal Multiplexing And Signal Descriptions
Signal Multiplexing and Signal Descriptions Chapter 3 Signal Multiplexing and Signal Descriptions Introduction To optimize functionality in small packages, pins have several functions available via signal multiplexing. This chapter illustrates which of this device's signals are multiplexed on which external pin. The Port Control block controls which signal is present on the external pin.
Page 33: Clock Gating
Signal Multiplexing and Signal Descriptions • Port A and port D are each assigned one interrupt. For DMA requests, port A and port D each have a dedicated input to the DMA multiplex. • Port A is assigned a dedicated interrupt and port C and port D share an interrupt. For DMA requests, port A, port C, and port D each have a dedicated input to the DMA multiplex.
Page 34: Pin Assignments And Signal Multiplexing
Signal Multiplexing and Signal Descriptions To ensure the best signal timing for a given peripheral's interface, choose the pins in closest proximity to each other. Pin Assignments and Signal Multiplexing The following table shows the signals available on each pin and the locations of these pins on the MKW01. The Port Control Module is responsible for selecting which ALT functionality is available on each MCU pin.
Page 35 Signal Multiplexing and Signal Descriptions Table 3-3. MKW01 Pin Assignments and Signal Multiplexing (Sheet 2 of 4) XCVR MCU die Default alt 0 alt 1 alt 2 alt 3 alt 4 alt 5 alt 6 alt 7 Name PTA4 PTA4 NMI_b TSI0_ PTA4...
Page 36 Signal Multiplexing and Signal Descriptions Table 3-3. MKW01 Pin Assignments and Signal Multiplexing (Sheet 3 of 4) XCVR MCU die Default alt 0 alt 1 alt 2 alt 3 alt 4 alt 5 alt 6 alt 7 Name PTC3 PTC3 DISABL PTC3/ UART1...
Page 37 Signal Multiplexing and Signal Descriptions Table 3-3. MKW01 Pin Assignments and Signal Multiplexing (Sheet 4 of 4) XCVR MCU die Default alt 0 alt 1 alt 2 alt 3 alt 4 alt 5 alt 6 alt 7 Name RESET RESET RESET DIO0 / PTE2...
Page 38: System Considerations
System Considerations Introduction The MKW01Z128 is the embodiment of a sub-1 GHz wireless node in a single SiP package. All control of the node is done through the in-package Kinetis KL26 48 MHz processor, and all MCU peripherals, MCU GPIO, transceiver functionality, and transceiver GPIO are manipulated by the processor. The MCU GPIO and MCU peripherals are accessed as ports from the MCU internal bus and can be programmed directly.
Page 39 Connect to ground. Flags on bottom of package are electrically separate. Both must be connected to ground. When designing power to the MKW01Z128 SiP, the following points need to be considered: • The SiP package has two ground flags (VSS) on chip the package (pin 4 and pin 20). These are separated and both must be connected to system ground.
Page 40: System Functional Interconnects
ADC module is commonly also tied to the VDD common supply and the VREFL low reference voltage is tied to ground. System functional interconnects The MKW01Z128 comprises two separate devices in a single package. The MCU controls the transceiver and there are connections between the devices for several functions. •...
Page 41: System Reset
Transceiver Reset The transceiver can be reset via two means: • A power-on reset (POR) of the MKW01Z128 transceiver is triggered when VDD is applied to VBAT1 and VBAT2. • A hardware reset can be issued by controlling Pin 48 (transceiver RESET).
Page 42: Mcu Control Of Transceiver Reset
Any CLKOUT activity can also be used to detect when the chip is ready. 4.3.2.2.2 Transceiver Hardware Reset A hardware reset of the transceiver on MKW01Z128 is also possible by asserting RESET high for a minimum of one hundred microseconds, and then releasing. The application must wait 5 ms before using the chip.
Page 43: System Clock Sources And Configurations
MCU clock to an internal low-power clock immediately prior to asserting Listen mode to prevent loss of clock affecting MCU performance. System Clock Sources and Configurations The MKW01Z128 clock connections are shown in Figure 4-4. The device allows for a wide array of system clock configurations.
Page 44: Additional Transceiver Status Signals
Figure 4-4. MKW01Z128 Clock Connections (Upper figure is the preferred configuration.) 4.4.1 Additional Transceiver Status Signals The MKW01Z128 transceiver has a total of six outputs (DIO5:DIO0) that can be programmed as status indicators: • DIO1 and DIO0 are connected to MCU GPIOs, PTE3 & PTE2, internally to the package. For certain software configurations, improved performance can be obtained by connecting to MKW01xxRM Reference Manual, Rev.
Page 45: Transceiver Oscillator
Crystal Resonator Specification Table 4-2 shows the crystal resonator specification for the crystal reference oscillator circuit of the MKW01Z128 transceiver. This specification covers the full range of operation and is employed in the reference design. Table 4-2. Crystal Specification Symbol...
Page 46: Transceiver Clkout Output (Dio5)
System Considerations NOTE • The initial frequency tolerance (cut tolerance), temperature stability and aging performance should be chosen in accordance with the target operating temperature range and the receiver bandwidth selected. • The loading capacitance should be applied externally, and adapted to the actual C specification of the crystal.
Page 47: Mcu Clock Sources
System Considerations 4.4.3 MCU Clock Sources The MCU has several options for its primary clock source depending on its mode of operation as well as its hardware configuration. • The ICS module has an on-chip 32 kHz (nominal) oscillator and FLL - —...
Page 48: Mcu Internal Clock Source
Because of the multiple clock configurations of the MCU, the availability of external clock source pins of both the transceiver and the MCU, and the ClkOut output from the transceiver, there are a number of variations for MKW01Z128 system clock configurations. Key considerations for any system clock configuration are: •...
Page 49: Single Crystal With Clkout Driving Mcu Extal Input
System Considerations NOTE In the following sub-sections, it is assumed that the MCU GPIO is connected to drive the transceiver reset. 4.4.4.1 Single crystal with ClkOut driving MCU EXTAL input The single crystal (transceiver) with ClkOut driving the MCU EXTAL input (external clock) is the most common configuration for low cost and excellent frequency accuracy.
Page 50: Debug Port Pin Descriptions
Serial wire debug data input/output. This pin is used by an external debug tool for communication and device control. This pin is pulled up internally. MKW01Z128 GPIO (Mixed I/O from Transceiver and MCU) The MKW01Z128 SiP supports a total of 43 GPIO pins that originate from the transceiver and/or the MCU: •...
Page 51: Mcu Gpio Characteristics
The internal MCU GPIO hardware consists of 5 ports with 32 signals per port for a total of 160 signals (not all are available on the MKW01Z128). There are 8 signals from PTA, 5 from PTB, 9 from PTC, 5 from PTD and 9 from PTE, many of which are dedicated to some function.
Page 52: Transceiver Rf Configurations And External Connections
System Considerations Transceiver RF Configurations and External Connections The MKW01Z128 transceiver radio has features that allow for a flexible as well as low cost RF interface: • Sensitivity down to -120 dBm at 1.2 kbps • High selectivity w/16-tap FIR channel filter •...
Page 53: Higher Output Power Rf Configuration (Dual Port With Optional External Power Amplifier)
System Considerations • Inductor L8 and capacitor C19 provide an ac blocking network for the PA power supply. • The remaining external components are a generalized RF network - — Provides impedance match between the antenna and the transceiver RFIO —...
Page 54 System Considerations • Similar to the single-port configuration, generalized RF circuit topologies are shown for both the TX and RX paths - — The TX path network provides both impedance matching and low pass filtering for TX harmonic trapping and out-of-band suppression —...
Page 55 System Considerations AC Blocking Network VR_PA ANT_RF DEVICE_RF Figure 4-7. General RF Filter/Matching Network Topology NOTE These component values are given only as suggested initial design values. The user must evaluate his particular design and adjust/change components as required to meet targeted specifications. Table 4-5.
Page 56: Sub 1 Ghz Transceiver Architecture Description
Chapter 5 Sub 1 GHz Transceiver Architecture Description This chapter describes the architecture and operation of the MKW01Z128 low-power, highly integrated transceiver chip. Overview The MKW01Z128 transceiver is a single-chip integrated circuit ideally suited for today's high performance ISM band RF applications. The transceivers's advanced features set, including state of the art packet engine greatly simplifies system design while the high level of integration reduces the external BOM to a handful of passive decoupling and matching components.
Page 57: Transceiver Power Supply
Figure 5-1. MKW01Z128 Transceiver Block Diagram Transceiver Power Supply The MKW01Z128 has separate power pins for both the MCU and the transceiver. The transceiver employs on-chip regulation and management that provides stable operating characteristics over the full temperature and voltage range of operation. This includes the full output power of +17dBm which is maintained from 1.8 to 3.6 V.
Page 58: Frequency Synthesis
5.5.1 Reference Oscillator The crystal oscillator is the main timing reference of the MKW01Z128. It is used as a reference for the transceiver frequency synthesizer and as a clock for the digital processing. In turn, the transceiver ClkOut signal can be used to provide an external reference clock for the MCU (see Section 4.4, “System Clock...
Page 59: Pll Architecture
Sub 1 GHz Transceiver Architecture Description 5.5.3 PLL Architecture The frequency synthesizer generating the LO frequency for both the receiver and the transmitter is a fractional-N sigma-delta PLL. The PLL incorporates a third order loop capable of fast auto-calibration, and it has a fast switching-time. The VCO and the loop filter are both fully integrated, removing the need for an external tight-tolerance, high-Q inductor in the VCO tank circuit.
Page 60: Lock Detect Indicator
The lock detect block may indicate an unlock condition (signal toggling low) when the transmitter is FSK modulated with large frequency deviation settings. Transmitter Description The transmitter of MKW01Z128 transceiver is comprised of the frequency synthesizer, modulator and power amplifier blocks. Receiver Chain RFIO...
Page 61: Bit Rate Setting
Sub 1 GHz Transceiver Architecture Description 5.6.1 Bit Rate Setting When using the transceiver in Continuous mode, the data stream to be transmitted can be input directly to the modulator via pin DIO2/DATA in an asynchronous manner, unless Gaussian filtering is used, in which case the DCLK signal on pin 10 (DIO1/DCLK) is used to synchronize the data stream.
Page 62: Fsk Modulation
In FSK mode, a Gaussian filter with BT = 0.3, 0.5 or 1 is used to filter the modulation stream, at the input of the sigma-delta modulator. If the Gaussian filter is enabled when the MKW01Z128 is in Continuous mode, DCLK signal on pin 10 (DIO1/DCLK) will trigger an interrupt on the MCU each time a new bit has to be transmitted.
Page 63 Sub 1 GHz Transceiver Architecture Description NOTE When PA1 and PA2 are combined to deliver +17 dBm to the antenna, a specific impedance matching / harmonic filtering design is required to ensure impedance transformation and regulatory compliance. All PA settings are controlled by RegPaLevel, and the truth table of settings is given in Table 5-2.
Page 64: Over Current Protection
Vbatt will be higher Receiver Description The MKW01Z128 transceiver features a digital receiver with the analog to digital conversion process being performed directly following the LNA-Mixers block. The zero-IF receiver is able to handle (G)FSK and (G)MSK modulation. ASK and OOK modulation is, however, demodulated by a low-IF architecture.
Page 65: Automatic Gain Control
Sub 1 GHz Transceiver Architecture Description NOTE Due to circuit specifics and matching topology, optimum performance in any given design may be achieved with LNA Zin set to either 50  or 200 . Both settings should be tested for sensitivity in the actual system in development.
Page 66 Sub 1 GHz Transceiver Architecture Description both cases (AutoRxRestartOn=0 or AutoRxRestartOn=1), the receiver can also re-enter the WAIT mode by setting RestartRx bit to 1. The user can decide to do so, to manually launch a new AGC procedure. — Continuous mode: upon reception of valid data, the user can decide to either leave the receiver enabled with the same LNA gain, or to restart the procedure, by setting RestartRx bit to 1, resuming the WAIT mode of the receiver, described above.
Page 67: Rssithreshold Setting
Sub 1 GHz Transceiver Architecture Description 5.7.2.1 RssiThreshold Setting For correct operation of the AGC, RssiThreshold in RegRssiThresh must be set to the sensitivity of the receiver. The receiver will remain in WAIT mode until RssiThreshold is exceeded. NOTE When AFC is enabled and performed automatically at the receiver startup, the channel filter is used by the receiver during the AFC and the AGC is RxBwAfc instead of the standard RxBw setting.
Page 68: Channel Filter
Sub 1 GHz Transceiver Architecture Description In the lower bands of operation (290 to 510 MHz), the multi-phase mixing architecture with weighted phases improves the rejection of the LO harmonics in receiver mode, hence increasing the receiver immunity to out-of-band interferers. The I and Q digitalization is made by two 5 order continuous-time Sigma-Delta Analog to Digital Converters (ADC).
Page 69: Dc Cancellation
Sub 1 GHz Transceiver Architecture Description Table 5-5. Available RxBw Settings 10b / 24 01b / 20 00b / 16 10b / 24 10.4 01b / 20 12.5 00b / 16 15.6 10b / 24 20.8 10.4 01b / 20 25.0 12.5 00b / 16...
Page 70: Complex Filter - Ook
Sub 1 GHz Transceiver Architecture Description Table 5-6. Available DCC Cutoff Frequencies Expressed as Percentage of RXBW (continued) DccFreq in RegRxBw fc in % of RxBw 0.25 0.125 The default value of DccFreq cutoff frequency is typically 4% of the RxBw (channel filter BW). The cutoff frequency of the DCC can however be increased to slightly improve the sensitivity under wider modulation conditions.
Page 71: Cordic
Sub 1 GHz Transceiver Architecture Description NOTE • The receiver is capable of automatic gain calibration in order to improve the precision of its RSSI measurements. This function injects a known RF signal at the LNA input, and calibrates the receiver gain accordingly. This calibration is automatically performed during the PLL start-up, making it a transparent process to the end-user •...
Page 72: Fsk Demodulator
Sub 1 GHz Transceiver Architecture Description Q(t) Real-time Magnitude Real-time Phase I(t) Figure 5-6. Cordic Extraction 5.7.10 FSK Demodulator The FSK demodulator of the receiver is designed to demodulate FSK, GFSK, MSK and GMSK modulated signals. It is most efficient when the modulation index of the signal is greater than 0.5 and below 10: ...
Page 73: Optimizing The Floor Threshold
Sub 1 GHz Transceiver Architecture Description Figure 5-7. OOK Peak Demodulator Description In peak threshold mode the comparison threshold level is the peak value of the RSSI, reduced by 6dB. In the absence of an input signal, or during the reception of a logical "0", the acquired peak value is decremented by one OokPeakThreshStep every OokPeakThreshDec period.
Page 74: Optimizing Ook Demodulator For Fast Fading Signals
Sub 1 GHz Transceiver Architecture Description It is therefore important to note that the setting of OokFixedThresh will be application dependant. The following procedure is recommended to optimize OokFixedThresh. Set SX12 31 in OOK Rx mode MKW01 Adjust Bit Rate, Channel filter BW Default OokFixedThreshsetting No input signal Continuous Mode...
Page 75 Sub 1 GHz Transceiver Architecture Description settings. However, for optimum receiver performance its use when running Continuous mode is strongly advised. The Bit Synchronizer is automatically activated in Packet mode. Its bit rate is controlled by BitRateMsb and BitRateLsb in RegBitrate. Figure 5-9.
Page 76: Frequency Error Indicator (Fei)
Sub 1 GHz Transceiver Architecture Description 5.7.13 Frequency Error Indicator (FEI) This function provides information about the frequency error of the local oscillator (LO) compared with the carrier frequency of a modulated signal at the input of the receiver. When the FEI block is launched, the frequency error is measured and the signed result is loaded in FeiValue in RegFei, in 2’s complement format.
Page 77: Automatic Frequency Correction (Afc)
Sub 1 GHz Transceiver Architecture Description 5.7.14 Automatic Frequency Correction (AFC) The AFC is based on the FEI block, and therefore the same input signal and receiver setting conditions apply. When the AFC procedure is done, AfcValue is directly subtracted to the register that defines the frequency of operation of the chip, F .
Page 78: Temperature Sensor
Sub 1 GHz Transceiver Architecture Description & FeiValue AfcValue Standard AFC AfcLowBetaOn = 0 FeiValue AfcValue LowBetaAfcOffset Optimized AFC AfcLowBetaOn = 1 Before AFC After AFC Figure 5-11. Optimized AFC (AfcLowBetaOn=1) As shown on Figure 5-11, a standard AFC sequence uses the result of the FEI to correct the LO frequency and align both local oscillators.
Page 79: Timeout Function
TempMeasStart to 1 to TempMeasRunning reset). 5.7.17 Timeout Function The MKW01Z128 includes a Timeout function, which allows it to automatically shut-down the receiver after a receive sequence and therefore save energy. • Timeout interrupt is generated TimeoutRxStart * 8 * Tbit after switching to RX mode if RssiThreshold flag does not raise within this time frame •...
Page 80: Transceiver Operating Modes
Chapter 6 Transceiver Operating Modes This chapter describes the operating modes of the MKW01Z128 transceiver. Basic Modes The transceiver can be programmed to 5 different basic modes which are described in Table 6-1. By default, when switching from a mode to another one, the sub-blocks are woken up according to a pre-defined and optimized sequence.
Page 81: Transmitter Startup Time
Transceiver Operating Modes • Receiver Wake Up time from Sleep mode = TS_OSC + TS_FS + TS_RE • Receiver Wake Up time from Sleep mode, AGC enabled = TS_OSC + TS_FS + TS_RE_AGC • Receiver Wake Up time from Sleep mode, AGC and AFC enabled = TS_OSC + TS_FS + TS_RE_AGC&AFC In applications where the target average power consumption, or the target startup time, do not require setting the transceiver in the lowest power modes (Sleep or Standby), the respective timings TS_OSC and...
Page 82: Receiver Startup Time
Transceiver Operating Modes • In Packet mode - the transmitter will automatically modulate the RF signal with preamble bytes as soon as TxReady or ModeReady happen. The actual packet transmission (starting with the number of preambles specified in PreambleSize) will start when the TxStartCondition is fulfilled. 6.2.3 Receiver Startup Time It is highly recommended to use the built-in sequencer of the transceiver to optimize the delays when...
Page 83: Rx Start Procedure
Transmitter hop from Ch A to Ch B - it is advised to step through the RX mode: 1.Transceiver is in TX mode in Ch A 2.Program the MKW01Z128 in RX mode 3.Change the carrier frequency in the RegFrf registers 4.Turn the transceiver back to TX mode...
Page 84: Listen Mode
Transceiver Operating Modes Listen Mode The receiver can be set to Listen mode, by setting ListenOn in RegOpMode to 1 while in Standby mode. In this mode, transceiver spends most of the time in Idle mode, during which only the RC oscillator runs. Periodically the receiver is awakened and listens for an RF signal.
Page 85: Criteria
Transceiver Operating Modes where ListenResolX is the RX or Idle resolution and is independently programmable on three values (64us, 4.1ms or 262ms), whereas ListenCoefX is an integer between 1 and 255. All parameters are located in RegListen registers. The timing ranges are tabulated in Table 6-2 below.
Page 86: Rc Timer Accuracy
Transceiver Operating Modes Table 6-4. End of Listen Cycle Actions Chip stays in RX mode until PayloadReady or Timeout interrupt occurs. It then goes to the mode defined by Mode. Listen mode stops and must be disabled. Chip stays in RX mode until PayloadReady or Timeout interrupt occurs. Listen mode then resumes in Idle state.
Page 87 Transceiver Operating Modes The initial and the final state is the one configured in Mode in RegOpMode. The initial & final states can be different by configuring the modes register while the chip is in intermediate mode. The pictorial description of the auto modes is shown below. Intermediate State defined by IntermediateMode ExitCondition...
Page 88: Transceiver Digital Control And Communications
Transceiver Digital Control and Communications Overview The following figure shows the MKW01Z128 data processing circuit. Its role is to interface the data to/from the modulator/demodulator and the MCU access points (SPI and DIO pins). It also controls all the configuration registers.
Page 89: Control Block Description
Transceiver Digital Control and Communications • Packet mode (recommended): user only provides/retrieves payload bytes to/from the FIFO. The packet is automatically built with preamble, Sync word, and optional AES, CRC, and DC-free encoding schemes The reverse operation is performed in reception. The MCU processing overhead is hence significantly reduced compared to Continuous mode.
Page 90: Fifo
Transceiver Digital Control and Communications • wnr bit, which is 1 for write access and 0 for read access • 7 bits of address, MSB first The second byte is a data byte, either sent on MOSI by the master in case of a write access, or received by the master on MISO in case of read access.
Page 91: Size
Transceiver Digital Control and Communications 7.2.2.2 Size The FIFO size is fixed to 66 bytes. 7.2.2.3 Interrupt Sources and Flags • FifoNotEmpty: FifoNotEmpty interrupt source is low when byte 0, i.e. whole FIFO, is empty. Otherwise it is high. Note that when retrieving data from the FIFO, FifoNotEmpty is updated on NSS falling edge, i.e.
Page 92: Fifo Clearing
Transceiver Digital Control and Communications 7.2.2.4 FIFO Clearing Table below summarizes the status of the FIFO when switching between different modes. Table 7-1. Status of FIFO when Switching Between Different Modes of the Chip From FIFO status Comments Stdby Sleep Not cleared Sleep Stdby...
Page 93: Configuration
The control block configures and controls the full chip's behavior according to the settings programmed in the configuration registers. Digital IO Pins Mapping Six general purpose IO pins are available on the MKW01Z128, and their configuration in Continuous or Packet mode is controlled through RegDioMapping1 and RegDioMapping2. MKW01xxRM Reference Manual, Rev. 3, 04/2016...
Page 94: Dio Pins Mapping In Continuous Mode
Transceiver Digital Control and Communications 7.3.1 DIO Pins Mapping in Continuous Mode Table 7-2. DIO Mapping, Continuous Mode Mode Diox DIO5 DIO4 DIO3 DIO2 DIO1 DIO0 Mapping Sleep LowBat LowBat AutoMode LowBat LowBat ModeReady ModeReady Stdby ClkOut LowBat LowBat AutoMode LowBat LowBat ModeReady...
Page 95: Continuous Mode
Transceiver Digital Control and Communications NOTE Received Data is only shown on the Data signal between RxReady and PayloadReady’s rising edges Continuous Mode 7.4.1 General Description As illustrated in Figure 7-6, in Continuous mode the NRZ data to (from) the (de)modulator is directly accessed by the MCU on the bidirectional DIO2/DATA pin.
Page 96: Rx Processing
In Packet mode the NRZ data to (from) the (de)modulator is not directly accessed by the MCU but stored in the FIFO and accessed via the SPI interface. In addition, the MKW01Z128 packet handler performs several packet oriented tasks such as Preamble and Sync word generation, CRC calculation/check, whitening/dewhitening of data, Manchester encoding/decoding, address filtering, AES encryption/decryption, etc.
Page 97: Packet Format
Transceiver Digital Control and Communications Figure 7-9. Packet Mode Conceptual View NOTE The Bit Synchronizer is automatically enabled in Packet mode. 7.5.2 Packet Format 7.5.2.1 Fixed Length Packet Format Fixed length packet format is selected when bit PacketFormat is set to 0 and PayloadLength is set to any value greater than 0.
Page 98: Variable Length Packet Format
Transceiver Digital Control and Communications DC free Data encoding CRC checksum calculation AES Enc/Dec Preamble Sync Word Address Message 0 to 65535 0 to 8 bytes byte Up to 255 bytes 2-bytes bytes Payload (min 1 byte) Fields added by the packet handler in Tx and processed and removed in Rx Optional User provided fields which are part of the payload Message part of the payload Figure 7-10.
Page 99: Unlimited Length Packet Format
Transceiver Digital Control and Communications 7.5.2.3 Unlimited Length Packet Format Unlimited length packet format is selected when bit PacketFormat is set to 0 and PayloadLength is set to 0. The user can then transmit and receive packet of arbitrary length and PayloadLength register is not used in TX/RX modes for counting the length of the bytes transmitted/received.
Page 100: Rx Processing (Without Aes)
Transceiver Digital Control and Communications The transmission of packet data is initiated by the Packet Handler only if the chip is in TX mode and the transmission condition defined by TxStartCondition is fulfilled. If transmission condition is not fulfilled then the packet handler transmits a preamble sequence until the condition is met. This happens only if the preamble length ...
Page 101: Aes
Transceiver Digital Control and Communications 7.5.5 AES is the symmetric-key block cipher that provides the cryptographic capabilities to the transceiver. The system proposed can work with 128-bit long fixed keys. The fixed key is stored in a 16-byte write only user configuration register, which retains its value in Sleep mode.
Page 102: Handling Large Packets
FIFO at the same time to perform encryption. 7.5.7 Packet Filtering MKW01Z128's packet handler offers several mechanisms for packet filtering, ensuring that only useful packets are made available to the MCU, reducing significantly system power consumption and software complexity.
Page 103: Address Based
Transceiver Digital Control and Communications Every received packet which does not start with this locally configured Sync word is automatically discarded and no interrupt is generated. When the Sync word is detected, payload reception automatically starts and SyncAddressMatch is asserted. NOTE Sync Word values containing 0x00 byte(s) are forbidden.
Page 104: Dc-Free Data Mechanisms
Transceiver Digital Control and Communications • On RX side the checksum is calculated on the received payload and compared with the two checksum bytes received. The result of the comparison is stored in bit CrcOk. By default, if the CRC check fails then the FIFO is automatically cleared and no interrupt is generated. This filtering function can be disabled via CrcAutoClearOff bit and in this case, even if CRC fails, the FIFO is not cleared and only PayloadReady interrupt goes high.
Page 105: Data Whitening
Transceiver Digital Control and Communications Figure 7-14. Manchester Encoding/Decoding 7.5.8.2 Data Whitening Another technique called whitening or scrambling is widely used for randomizing the user data before radio transmission. The data is whitened using a random sequence on the TX side and de-whitened on the RX side using the same sequence.
Page 106 Transceiver Digital Control and Communications Table 7-4. Registers Summary Default Reset Address Register Name (recomme Description (built-in) nded) 0x05 RegFdevMsb 0x00 Frequency Deviation setting, Most Significant Bits 0x06 RegFdevLsb 0x52 Frequency Deviation setting, Least Significant Bits 0x07 RegFrfMsb 0xE4 RF Carrier Frequency, Most Significant Bits 0x08 RegFrfMid 0xC0...
Page 107 Transceiver Digital Control and Communications Table 7-4. Registers Summary Default Reset Address Register Name (recomme Description (built-in) nded) 0x24 RegRssiValue 0xFF RSSI value in dBm 0x25 RegDioMapping1 0x00 Mapping of pins DIO0 to DIO3 0x26 RegDioMapping2 0x05 0x07 Mapping of pins DIO4 and DIO5, ClkOut frequency 0x27 RegIrqFlags1 0x80...
Page 108: Common Configuration Registers
Transceiver Digital Control and Communications NOTE Reset values are automatically refreshed in the chip at Power On Reset. Default values are the recommended register values, optimizing the device operation. Registers for which the Default value differs from the Reset value are denoted by a * in the appropriate tables.
Page 109 Transceiver Digital Control and Communications Table 7-5. Common Configuration Registers (Sheet 2 of 4) Name Default Bits Variable Name Mode Description (Address) Value RegDataModul unused (0x02) DataMode Data processing mode: 00  Packet mode 01  reserved 10  Continuous mode with bit synchronizer 11 ...
Page 110 Transceiver Digital Control and Communications Table 7-5. Common Configuration Registers (Sheet 3 of 4) Name Default Bits Variable Name Mode Description (Address) Value RegOsc1 RcCalStart Triggers the calibration of the RC oscillator when set. (0x0A) Always reads 0. RC calibration must be triggered in Standby mode.
Page 111 Transceiver Digital Control and Communications Table 7-5. Common Configuration Registers (Sheet 4 of 4) Name Default Bits Variable Name Mode Description (Address) Value RegListen1 ListenResolIdle Resolution of Listen mode Idle time (calibrated RC osc): 00  reserved (0x0D) 01  64 us 10 ...
Page 112: Transmitter Registers
Transceiver Digital Control and Communications Transmitter Registers Table 7-6. Transmitter Registers Name Default Bits Variable Name Mode Description (Address) Value RegPaLevel Pa0On * Enables PA0, connected to RFIO and LNA (0x11) Pa1On * Enables PA1, on PA_BOOST pin Pa2On * Enables PA2, on PA_BOOST pin OutputPower 11111...
Page 113: Receiver Registers
Transceiver Digital Control and Communications Receiver Registers Table 7-7. Receiver Registers Name Default Bits Variable Name Mode Description (Address) Value Reserved14 0x40 unused (0x14) Reserved15 0xB0 unused (0x15) Reserved16 0x7B unused (0x16) Reserved17 0x9B unused (0x17) RegLna LnaZin LNA’s input impedance 0 ...
Page 114 Transceiver Digital Control and Communications Table 7-7. Receiver Registers (continued) RegAfcBw DccFreqAfc DccFreq parameter used during the AFC (0x1A) RxBwMantAfc RxBwMant parameter used during the AFC RxBwExpAfc 011 * RxBwExp parameter used during the AFC RegOokPeak OokThreshType Selects type of threshold in the OOK data slicer: 00 ...
Page 115 Transceiver Digital Control and Communications Table 7-7. Receiver Registers (continued) RegAfcFei unused (0x1E) 0  FEI is on-going FeiDone 1  FEI finished FeiStart Triggers a FEI measurement when set. Always reads 0. 0  AFC is on-going AfcDone 1  AFC has finished AfcAutoclearOn Only valid if AfcAutoOn is set 0 ...
Page 116: Irq And Pin Mapping Registers
Transceiver Digital Control and Communications 7.10 IRQ and Pin Mapping Registers Table 7-8. IRQ and Pin Mapping Registers Name Default Bits Variable Name Mode Description (Address) Value RegDioMapping1 Dio0Mapping (0x25) Mapping of pins DIO0 to DIO5 Dio1Mapping Table 7-2 for mapping in Continuous mode Dio2Mapping Table 7-3 for mapping in Packet mode...
Page 117 Transceiver Digital Control and Communications Table 7-8. IRQ and Pin Mapping Registers (continued) RegIrqFlags1 ModeReady Set when the operation mode requested in (0x27) Mode , is ready - Sleep: Entering Sleep mode - Standby: XO is running - FS: PLL is locked - RX: RSSI sampling starts - TX: PA ramp-up completed Cleared when changing operating mode.
Page 118 Transceiver Digital Control and Communications Table 7-8. IRQ and Pin Mapping Registers (continued) RegIrqFlags2 FifoFull Set when FIFO is full (i.e. contains 66 bytes), (0x28) else cleared. FifoNotEmpty Set when FIFO contains at least one byte, else cleared FifoLevel Set when the number of bytes in the FIFO strictly exceeds FifoThreshold , else cleared.
Page 119: Packet Engine Registers
Transceiver Digital Control and Communications 7.11 Packet Engine Registers Table 7-9. Packet Engine Registers Name Default Bits Variable Name Mode Description (Address) Value RegPreambleMsb PreambleSize(15:8) 0x00 Size of the preamble to be sent (from TxStartCondition (0x2c) fulfilled). (MSB byte) RegPreambleLsb PreambleSize(7:0) 0x03 Size of the preamble to be sent (from TxStartCondition...
Page 120 Transceiver Digital Control and Communications Table 7-9. Packet Engine Registers (continued) RegPacketConfig1 PacketFormat Defines the packet format used: 0  Fixed length (0x37) 1  Variable length DcFree Defines DC-free encoding/decoding performed: 00  None (Off) 01  Manchester 10  Whitening 11 ...
Page 121 Transceiver Digital Control and Communications Table 7-9. Packet Engine Registers (continued) RegAutoModes EnterCondition Interrupt condition for entering the intermediate mode: 000  None (AutoModes Off) (0x3B) 001  Rising edge of FifoNotEmpty 010  Rising edge of FifoLevel 011  Rising edge of CrcOk 100 ...
Page 122 Transceiver Digital Control and Communications Table 7-9. Packet Engine Registers (continued) RegAesKey2 AesKey(119:112) 0x00 byte of cipher key (0x3F) RegAesKey3 AesKey(111:104) 0x00 byte of cipher key (0x40) RegAesKey4 AesKey(103:96) 0x00 byte of cipher key (0x41) RegAesKey5 AesKey(95:88) 0x00 byte of cipher key (0x42) RegAesKey6 AesKey(87:80)
Page 123: Temperature Sensor Registers
Transceiver Digital Control and Communications 7.12 Temperature Sensor Registers Table 7-10. Temperature Sensor Registers Name Default Bits Variable Name Mode Description (Address) Value RegTemp1 0000 unused (0x4E) TempMeasStart Triggers the temperature measurement when set. Always reads 0. TempMeasRunning Set to 1 while the temperature measurement is running. Toggles back to 0 when the measurement has completed.
Page 124: Mkw01Z128 Transceiver - Mcu Spi Interface
Chapter 8 MKW01Z128 Transceiver - MCU SPI Interface The MKW01 transceiver and CPU communicate primarily through the onboard SPI interface. MCU has SPI0 is dedicated to the transceiver SPI interface and should not be used for other applications. The transceiver is a SPI slave only, and the MCU SPI module must be programmed and used as a master only.
Page 125: Features
MKW01Z128 Transceiver - MCU SPI Interface Features Features of the SPI bus interface: • MCU is the SPI Bus master • Transceiveris bus slave • Bi-directional data transfer • Dedicated interface; must meet transceiver protocol requirements • Programmable SPI clock rate; maximum transfer rate is 10 MHz as determined by the transceiver •...
Page 126: Spi Signal Definitions
MKW01Z128 Transceiver - MCU SPI Interface 8.3.1 SPI Signal Definitions The SPI signals of SS, SCK, MOSI, and MISO are defined in the following paragraphs. 8.3.1.1 Slave Select (SS or NSS) A transaction on the SPI port is framed by the active low Slave Select (SS) input signal which is driven by the MCU as master.
Page 127: Mkw0Xxx Spi Transaction Timing
MKW01Z128 Transceiver - MCU SPI Interface — The NSS pin goes low at the beginning of the frame and stays low between bytes. It goes high only after the last byte transfer. • FIFO access - special case of burst access for the FIFO —...
Page 128 MKW01Z128 Transceiver - MCU SPI Interface Figure 8-3. Transceiver SPI Read Single Access Timing Diagram The SPI Bus timing is determined by the transceiver specification as given in Table 8-1. Table 8-1. Transceiver SPI Timing Specifications Parameter Unit SPSCK period...
Page 129 MKW01Z128 Transceiver - MCU SPI Interface MKW01xxRM Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 130 Appendix A MKW01Z128 MCU Reference Manual MKW01xxRM Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 131 MKW01Z128 MCU Reference Manual MKW01xxRM Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 132: Mkw01Z128 Mcu Reference Manual
MKW01Z128 MCU Reference Manual Sub 1 GHz Low-Power Transceiver plus Microcontroller Reference Manual - Microcontroller Information Document Number: MKW01xxRM Rev. 3, 04/2016...
Page 133 MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 134 Computer operating properly (COP) watchdog configuration..............49 Clock modules................................52 1.5.1 MCG configuration............................52 1.5.2 OSC configuration............................53 Memories and memory interfaces..........................54 1.6.1 Flash memory configuration.......................... 54 1.6.2 Flash memory controller configuration......................56 MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 135 Alternate non-volatile IRC user trim description...................82 SRAM memory map..............................83 Bit Manipulation Engine...............................83 Peripheral bridge (AIPS-Lite) memory map.........................84 2.6.1 Read-after-write sequence and required serialization of memory operations..........84 2.6.2 Peripheral bridge (AIPS-Lite) memory map....................85 MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 136 SPI clocking..............................100 3.7.7 I2C clocking..............................101 3.7.8 UART clocking.............................. 101 Chapter 4 Reset and Boot Introduction...................................103 Reset....................................103 4.2.1 Power-on reset (POR)............................ 104 4.2.2 System reset sources............................104 4.2.3 MCU resets..............................107 MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 137 Debug port pin descriptions............................125 SWD status and control registers..........................126 6.3.1 MDM-AP Control Register..........................127 6.3.2 MDM-AP Status Register..........................128 Debug resets..................................130 Micro Trace Buffer (MTB)............................131 Debug in low-power modes............................131 Debug and security............................... 132 MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 138 System Options Register 4 (SIM_SOPT4)....................154 8.2.4 System Options Register 5 (SIM_SOPT5)....................155 8.2.5 System Options Register 7 (SIM_SOPT7)....................157 8.2.6 System Device Identification Register (SIM_SDID)..................158 8.2.7 System Clock Gating Control Register 4 (SIM_SCGC4)................160 MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 139 Power mode transitions..........................182 9.4.2 Power mode entry/exit sequencing........................ 185 9.4.3 Run modes..............................187 9.4.4 Wait modes..............................189 9.4.5 Stop modes..............................190 9.4.6 Debug in low power modes........................... 193 Chapter 10 MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 140 LLWU Pin Enable 4 register (LLWU_PE4)....................211 11.4.5 LLWU Module Enable register (LLWU_ME)....................212 11.4.6 LLWU Flag 1 register (LLWU_F1).......................214 11.4.7 LLWU Flag 2 register (LLWU_F2).......................215 11.4.8 LLWU Flag 3 register (LLWU_F3).......................217 MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 141 BME decorated stores............................ 232 13.3.2 BME decorated loads............................. 239 13.3.3 Additional details on decorated addresses and GPIO accesses..............245 13.4 Application information..............................246 Chapter 14 Miscellaneous Control Module (MCM) 14.1 Introduction...................................249 14.1.1 Features................................249 MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 142 16.3.1 General operation............................290 Chapter 17 Peripheral Bridge (AIPS-Lite) 17.1 Introduction...................................291 17.1.1 Features................................291 17.1.2 General operation............................291 17.2 Memory map/register definition........................... 292 17.2.1 Master Privilege Register A (AIPS_MPRA)....................292 MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 143 DMA Controller Module 19.1 Introduction...................................317 19.1.1 Overview................................ 317 19.1.2 Features................................318 19.2 DMA Transfer Overview..............................319 19.3 Memory Map/Register Definition..........................320 19.3.1 Source Address Register (DMA_SARn)....................... 321 19.3.2 Destination Address Register (DMA_DARn)....................322 MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 144 20.3.10 MCG Auto Trim Compare Value Low Register (MCG_ATCVL)..............348 20.3.11 MCG Control 7 Register (MCG_C7)......................349 20.3.12 MCG Control 8 Register (MCG_C8)......................349 20.3.13 MCG Control 10 Register (MCG_C10)......................350 20.3.14 MCG Control 12 Register (MCG_C12)......................350 MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 145 Memory Map/Register Definitions..........................374 21.7.1 OSC Memory Map/Register Definition......................375 21.8 Functional Description..............................376 21.8.1 OSC module states............................376 21.8.2 OSC module modes............................378 21.8.3 Counter................................380 21.8.4 Reference clock pin requirements........................380 MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 146 Register Descriptions............................. 392 23.4 Functional Description..............................401 23.4.1 Flash Protection..............................401 23.4.2 Interrupts................................ 402 23.4.3 Flash Operation in Low-Power Modes......................403 23.4.4 Functional Modes of Operation........................403 23.4.5 Flash Reads and Ignored Writes........................403 MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 147 ADC Data Result Register (ADCx_Rn)......................438 24.4.5 Compare Value Registers (ADCx_CVn)....................... 440 24.4.6 Status and Control Register 2 (ADCx_SC2)....................441 24.4.7 Status and Control Register 3 (ADCx_SC3)....................443 24.4.8 ADC Offset Correction Register (ADCx_OFS).....................444 MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 148 User-defined offset function.......................... 467 24.5.8 Temperature sensor............................468 24.5.9 MCU wait mode operation..........................469 24.5.10 MCU Normal Stop mode operation....................... 469 24.5.11 MCU Low-Power Stop mode operation......................470 24.6 Initialization information.............................. 471 MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 149 Power modes..............................495 25.3.3 Startup and operation............................. 496 25.3.4 Low-pass filter............................... 497 25.4 CMP interrupts................................499 25.5 DMA support................................499 25.6 CMP Asynchronous DMA support..........................499 25.7 Digital-to-analog converter............................500 25.8 DAC functional description............................500 MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 150 26.5.3 Resets................................510 26.5.4 Low-Power mode operation...........................511 Chapter 27 Timer/PWM Module (TPM) 27.1 Introduction...................................513 27.1.1 TPM Philosophy............................513 27.1.2 Features................................513 27.1.3 Modes of operation............................514 27.1.4 Block diagram..............................514 MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 151 27.4.9 DMA................................538 27.4.10 Output triggers............................... 538 27.4.11 Reset Overview.............................. 539 27.4.12 TPM Interrupts............................... 539 Chapter 28 Periodic Interrupt Timer (PIT) 28.1 Introduction...................................541 28.1.1 Block diagram..............................541 28.1.2 Features................................542 MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 152 Low Power Timer Control Status Register (LPTMRx_CSR)................555 29.3.2 Low Power Timer Prescale Register (LPTMRx_PSR)..................556 29.3.3 Low Power Timer Compare Register (LPTMRx_CMR)................558 29.3.4 Low Power Timer Counter Register (LPTMRx_CNR)................. 558 29.4 Functional description..............................559 MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 153 RTC Interrupt Enable Register (RTC_IER)....................571 30.3 Functional description..............................572 30.3.1 Power, clocking, and reset..........................572 30.3.2 Time counter..............................573 30.3.3 Compensation..............................574 30.3.4 Time alarm..............................574 30.3.5 Update mode..............................575 30.3.6 Register lock..............................575 MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 154 31.3.10 SPI control register 3 (SPIx_C3)........................595 31.4 Functional description..............................596 31.4.1 General................................596 31.4.2 Master mode..............................597 31.4.3 Slave mode..............................598 31.4.4 SPI FIFO Mode.............................. 600 31.4.5 SPI Transmission by DMA..........................601 MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 155 UART Control Register 3 (UARTx_C3)....................... 631 32.2.8 UART Data Register (UARTx_D).........................632 32.2.9 UART Match Address Registers 1 (UARTx_MA1)..................633 32.2.10 UART Match Address Registers 2 (UARTx_MA2)..................634 32.2.11 UART Control Register 4 (UARTx_C4)....................... 634 MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 156 33.3.8 UART Data Register (UARTx_D).........................658 33.3.9 UART Control Register 4 (UARTx_C4)....................... 659 33.4 Functional description..............................660 33.4.1 Baud rate generation............................660 33.4.2 Transmitter functional description......................... 661 33.4.3 Receiver functional description........................663 MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 157 Port Toggle Output Register (FGPIOx_PTOR)..................... 683 34.3.5 Port Data Input Register (FGPIOx_PDIR).....................684 34.3.6 Port Data Direction Register (FGPIOx_PDDR).................... 684 34.4 Functional description..............................685 34.4.1 General-purpose input............................685 34.4.2 General-purpose output..........................685 34.4.3 IOPORT................................. 685 Chapter 35 MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 158 35.4.10 Out-of-range interrupt............................ 701 35.4.11 Wake up MCU from low power modes......................702 35.4.12 DMA function support........................... 702 35.4.13 Noise detection mode.............................702 Chapter 36 Inter-Integrated Circuit (I2C) 36.1 Introduction...................................713 36.1.1 Features................................713 MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 159 System management bus specification......................736 36.4.5 Resets................................738 36.4.6 Interrupts................................ 738 36.4.7 Programmable input glitch filter........................741 36.4.8 Address matching wake-up..........................741 36.4.9 DMA support..............................742 36.5 Initialization/application information........................... 742 MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 160: Chip Configuration
ADC trigger is for supporting A and B triggering. In Stop and VLPS modes, the second trigger must be set to >10 µs after the first trigger Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 161 EXTRG_IN TPMx TPM Trigger TPMx_CONF[TRGSEL] (4-bit field) EXTRG_IN is not input available on MKW01. CMP0 CMP0_OUT TPMx TPM Trigger TPMx_CONF[TRGSEL] (4-bit field) — input Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 162: Analog Reference Options
Selected by DACx_C0[DACRFS] bit 2 - VDDA CMP with 6-bit DAC Vin1 - VREFH Selected by CMPx_DACCR[VRSEL] Vin2 - VDD 1. Use this option for the best ADC operation. 1.3 Core modules MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 163 Arch Clock Gating 1 = Present Implements architectural clock gating DAP Slave Port Support AHBSLV Supports any AHB debug access port (like the CM4 DAP) Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 164 • Single 32-bit AMBA-3 AHB-Lite system interface that provides connections to peripherals and all system memory, which includes flash memory and RAM • Single 32-bit I/O port bus interfacing to the GPIO with 1-cycle loads and stores MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 165: Nested Vectored Interrupt Controller (Nvic) Configuration
Reference Full description Nested vectored ARM Cortex-M0+ Technical Reference Manual interrupt controller (NVIC) System memory map — System memory map Clocking — Clock distribution Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 166 • IRQ number — non-core interrupt source count, which is the vector number minus The IRQ number is used within ARM's NVIC documentation. NOTE The NVIC wake-up sources in the following table support only down to VLPS. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 167 Status and error 0x0000_0074 UART1 Status and error 0x0000_0078 UART2 Status and error 0x0000_007C ADC0 — 0x0000_0080 CMP0 — 0x0000_0084 TPM0 — 0x0000_0088 TPM1 — Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 168 • NVICIPR2 field starting location = 8 * (IRQ mod 4) + 6 = 22 Since the NVICIPR fields are 2-bit wide (4 priority levels), the NVICIPR2 field range is 22–23. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 169: Asynchronous Wake-Up Interrupt Controller (Awic) Configuration
RESET pin when LPO is its clock source Low-voltage detect Power management controller—functional in Stop mode Low-voltage warning Power management controller—functional in Stop mode Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 170: System Modules
Figure 1-4. SIM configuration Table 1-11. Reference links to related information Topic Related module Reference Full description System memory map — System memory map Clocking — Clock distribution Power management — Power management MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 171: System Mode Controller (Smc) Configuration
VLLS2 power mode is not supported on this device. 1.4.3 PMC configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 172: Low-Leakage Wake-Up Unit (Llwu) Configuration
1.4.4 Low-Leakage Wake-up Unit (LLWU) Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 173 M7IF are connections to the internal peripheral interrupt flags. NOTE In addition to the LLWU wakeup sources, the device also wakes from low power modes when NMI or RESET pins are enabled and the respective pin is asserted. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 174: Mcm Configuration
System memory map — System memory map Clocking — Clock distribution Power management — Power management Private peripheral bus ARM Cortex-M0+ core ARM Cortex-M0+ core (PPB) Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 175: Crossbar-Light Switch Configuration
DMA controller Crossbar switch slave Flash memory Flash memory controller controller Crossbar switch slave SRAM controller SRAM configuration Crossbar switch slave Peripheral bridge Peripheral bridge 2-ported peripheral GPIO controller GPIO controller MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 176: Peripheral Bridge Configuration
Table 1-18. Reference links to related information Topic Related module Reference Full description Peripheral bridge Peripheral bridge (AIPS-Lite) (AIPS-Lite) System memory map — System memory map Clocking — Clock distribution Crossbar switch Crossbar switch Crossbar switch MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 177: Dma Request Multiplexer Configuration
Full description DMA request DMA Mux multiplexer System memory map System memory map Clocking Clock distribution Power management Power management Channel request DMA controller DMA Controller Requests DMA request sources MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 178 Reserved — — — TPM0 Channel 0 TPM0 Channel 1 TPM0 Channel 2 TPM0 Channel 3 TPM0 Channel 4 TPM0 Channel 5 Reserved — Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 179 DMA MUX Always enabled DMA MUX Always enabled DMA MUX Always enabled 1. Configuring a DMA channel to select source 0 or any of the reserved sources disables that DMA channel. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 180: Dma Controller Configuration
Power management Crossbar switch Crossbar switch Crossbar switch Requests DMA request sources 1.4.10 Computer operating properly (COP) watchdog configuration This section summarizes how the module has been configured in the chip. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 181 COP timeout period is restarted. If the program fails to perform this restart during the timeout period, the microcontroller resets. Also, if any value other than 0x55 or 0xAA is written to the SRVCOP register, the microcontroller immediately resets. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 182 If the 1 kHz clock source is selected, the COP counter is re-initialized to 0 upon entry to either Debug mode or Stop (including VLPS or LLS) mode. The counter begins from 0 upon exit from Debug mode or Stop mode. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 183: Clock Modules
Table 1-24. Reference links to related information Topic Related module Reference Full description System memory map — System memory map Clocking — Clock distribution Power management — Power management Signal multiplexing Port control Signal multiplexing MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 184: Osc Configuration
OSC_CR also provides control for enabling the OSC module and configuring internal load capacitors for the EXTAL and XTAL pins. See the chapters for more details. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 185: Memories And Memory Interfaces
Flash memory controller controller Register access Peripheral bridge Peripheral bridge 1.6.1.1 Flash memory sizes The devices covered in this document contain 2 program flash blocks consisting of 1 KB sectors. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 186 The flash memory chapter defines two modes of operation: NVM normal and NVM special modes. On this device, the flash memory only operates in NVM normal mode. All references to NVM special mode must be ignored. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 187: Flash Memory Controller Configuration
Full description Flash memory Flash memory controller controller System memory map — System memory map Clocking — Clock distribution Transfers Flash memory Flash memory Transfers Crossbar switch Crossbar switch Register access MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 188: Sram Configuration
The on-chip SRAM is split into two ranges, 1/4 is allocated SRAM_L and 3/4 is allocated to SRAM_U. The on-chip RAM is implemented such that the SRAM_L and SRAM_U ranges form a contiguous block in the memory map. As such: MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 189 • SRAM_L: 0x1FFF_F000 – 0x1FFF_FFFF • SRAM_U: 0x2000_0000 – 0x2000_2FFF 1.6.3.3 SRAM retention in low power modes The SRAM is retained down to VLLS3 mode. In VLLS1 and VLLS0, no SRAM is retained. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 190: System Register File Configuration
1.7.1 16-bit SAR ADC configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 191 CPU. The ADC supports DMA request functionality for higher performance when the ADC is sampled at a very high rate. The ADC can trigger the DMA (via DMA req) on conversion completion. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 192 Reserved 10011 AD19 Reserved Reserved 10100 AD20 Reserved Reserved 10101 AD21 Reserved Reserved 10110 AD22 Reserved Reserved 10111 AD23 Reserved 12-bit DAC0 Output/ ADC0_SE23 Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 193: Cmp Configuration
ADC clock operating frequency. 1.7.2 CMP configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 194 CMP_CR1[WE]. The sample function has limited functionality since the SAMPLE input to the block is not connected to a valid input. Usage of sample operation is limited to a divided version of the bus clock (CMP_CR1[SE] = 0). MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 195 TCF flag is set. The delay to the second signal that triggers the CMP to capture the result of the compare operation is dependent on the LPTMR configuration. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 196: 12-Bit Dac Configuration
Signal multiplexing 1.7.3.1 12-bit DAC instantiation information This device contains one 12-bit digital-to-analog converter (DAC) with programmable reference generator output. The DAC includes a two word FIFO for DMA support. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 197: Timers
1.8 Timers 1.8.1 Timer/PWM module configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 198 There are several connections to and from the TPMs in order to facilitate customer use cases. For complete details on the TPM module interconnects please refer to the Module- to-Module section. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 199 0101 PIT trigger 1 0110 Reserved 0111 Reserved 1000 TPM0 overflow 1001 TPM1 overflow 1010 TPM2 overflow 1011 Reserved 1100 RTC alarm 1101 RTC seconds 1110 LPTMR trigger 1111 Reserved MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 200: Pit Configuration
System memory map Clocking Clock Distribution Power management Power management 1.8.2.1 PIT/DMA periodic trigger assignments The PIT generates periodic trigger events to the DMA channel mux as shown in this table. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 201: Low-Power Timer Configuration
1.8.3 Low-power timer configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 202 LPTMR_CSR[TPS] configures the input source used in pulse counter mode. The following table shows the chip-specific input assignments for this field. LPTMR_CSR[TPS] Pulse counter input number Chip input CMP0 output LPTMR_ALT1 pin Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 203: Rtc Configuration
1.8.4 RTC configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 204 SIM_SOPT2[RTCCLKOUTSEL]. When SIM_SOPT2[RTCCLKOUTSEL] = 0, the RTC 1 Hz clock is output is selected on the RTC_CLKOUT pin. When SIM_SOPT2[RTCCLKOUTSEL] = 1, OSCERCLK clock is output on the RTC_CLKOUT pin. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 205: Communication Interfaces
The SPI supports DMA request and can operate in VLPS mode. When the SPI is operating in VLPS mode, it will operate as a slave. SPI can wake the MCU from VLPS mode upon reception of SPI data in slave mode. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 206: I2C Configuration
The digital glitch filter implemented in the IIC1 module, controlled by the I2C1_FLT[FLT] registers, is clocked from the system clock and thus has filter granularity in system clock cycle counts. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 207: Uart Configuration
ISO7816 protocol is intended to be handled in software for this product. To support smart card reading, TxD pin can be configured as pseudo open drain for 1-wire half-duplex like ISO7816 communication via SIM_SOPT5[UART0ODE]. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 208: Human-Machine Interfaces (Hmi)
These pins can be used to drive LED or power MOSFET directly. The high drive capability applies to all functions which are multiplexed on these pins (UART, TPM, SPI, I2C, CLK_OUT...etc) MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 209 Disabled Disabled Disabled Disabled Disabled enable at reset Pin mux control Pin mux at reset PTA0/PTA3/ ALT0 ALT0 ALT0 ALT0 PTA4=ALT7; Others=ALT0 Lock bit Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 210: Tsi Configuration
Table 1-49. Reference links to related information Topic Related module Reference Full description System memory map System memory map Clocking Clock Distribution Power management Power management Signal Multiplexing Port control Signal Multiplexing MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 211 The TSI has multiple sources of interrupt requests. However, these sources are OR'd together to generate a single interrupt request. When a TSI interrupt occurs, read the TSI status register to determine the exact interrupt source. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 212: Introduction
Bit Manipulation Engine (BME) access to AIPS Peripherals for Cortex-M0+ core slots 0-127 0x6000_0000–0xDFFF_FFFF Reserved – 0xE000_0000–0xE00F_FFFF Private Peripherals Cortex-M0+ core 0xE010_0000–0xEFFF_FFFF Reserved – Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 213: Flash Memory Map
Access to the flash memory ranges outside the amount of flash on the device causes the bus cycle to be terminated with an error followed by the appropriate response in the requesting bus master. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 214: Alternate Non-Volatile Irc User Trim Description
See the Bit Manipulation Engine Block Guide (BME) for a detailed description of BME functionality. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 215: Peripheral Bridge (Aips-Lite) Memory Map
In these situations, the application software must perform a read-after-write sequence to guarantee the required serialization of the memory operations: 1. Write the peripheral register. 2. Read the written peripheral register to verify the write. 3. Continue with subsequent operations. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 216: Peripheral Bridge (Aips-Lite) Memory Map
0x4001_9000 — 0x4001_A000 — 0x4001_B000 — 0x4001_C000 — 0x4001_D000 — 0x4001_E000 — 0x4001_F000 — 0x4002_0000 Flash memory 0x4002_1000 DMA channel mutiplexer 0 0x4002_2000 — Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 217 — 0x4004_4000 — 0x4004_5000 Touch sense interface (TSI) 0x4004_6000 — 0x4004_7000 SIM low-power logic 0x4004_8000 System integration module (SIM) 0x4004_9000 Port A multiplexing control Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 218 0x4006_5000 System oscillator (OSC) 0x4006_6000 0x4006_7000 0x4006_8000 — 0x4006_9000 — 0x4006_A000 UART0 0x4006_B000 UART1 0x4006_C000 UART2 0x4006_D000 — 0x4006_E000 — 0x4006_F000 — 0x4007_0000 — Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 219: Modules Restricted Access In User Mode
System 32-bit Address Range Resource Additional Range Detail Resource 0xE000_0000–0xE000_DFFF Reserved 0xE000_E000–0xE000_EFFF System Control Space 0xE000_E000–0xE000_E00F Reserved (SCS) 0xE000_E010–0xE000_E0FF SysTick 0xE000_E100–0xE000_ECFF NVIC 0xE000_ED00–0xE000_ED8F System Control Block Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 220 Chapter 2 Memory Map Table 2-3. PPB memory map (continued) System 32-bit Address Range Resource Additional Range Detail Resource 0xE000_ED90–0xE000_EDEF Reserved 0xE000_EDF0–0xE000_EEFF Debug 0xE000_EF00–0xE000_EFFF Reserved 0xE000_F000–0xE00F_EFFF Reserved 0xE00F_F000–0xE00F_FFFF Core ROM Space (CRS) MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 221 Private Peripheral Bus (PPB) memory map MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 222: Clock Distribution
3.3 High-level device clocking diagram The following system oscillator, MCG, and module registers control the multiplexers, dividers, and clock gates shown in the following figure: MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 223: Clock Definitions
CG — Clock gate Note: See subsequent sections for details on where these clocks are used. Figure 3-1. Clocking diagram 3.4 Clock definitions This table describes the clocks in the block diagram. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 224: Device Clock Summary
MCGOUTCLK Up to 100 MHz Up to 4 MHz In all stop modes except for partial stop modes and during PLL locking when Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 225 External reference 30–40 kHz 30–40 kHz System OSC OSC_CR[ERCLKEN] 32kHz cleared , or RTC_CLKIN (ERCLK32K) and RTC_CR[OSCE] cleared Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 226: Internal Clocking Requirements
The following is a common clock configuration for this device: Clock Frequency Core clock 48 MHz Platform clock 48 MHz System clock 48 MHz Bus clock 24 MHz Flash clock 24 MHz MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 227: Clock Divider Values After Reset
800 kHz or less. In this case, one example of correct configuration is MCG_SC[FCRDIV] = 000b, SIM_CLKDIV1[OUTDIV1] = 0000b, and SIM_CLKDIV1[OUTDIV4] = 100b, resulting in a divide-by-5 setting. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 228: Clock Gating
MCGFLLCLK, MCGIRCLK, OSCERCLK Bus clock OSCERCLK — Memory and memory interfaces Flash Controller Platform clock Flash clock — Flash memory Flash clock — — Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 229: Pmc 1-Khz Lpo Clock
VLLS0. This 1-kHz source is commonly referred to as LPO clock or 1-kHz LPO clock. 3.7.2 COP clocking The COP may be clocked from two clock sources as shown in the following figure. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 230: Rtc Clocking
The prescaler and glitch filters in each of the LPTMRx modules can be clocked as shown in the following figure. NOTE The chosen clock must remain enabled if the LPTMRx is to continue operating in all required low-power modes. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 231: Tpm Clocking
SPI1 is clocked from the system clock. That is, the SPI1 module clock is connected to the chip-level system clock. SPI1 is therefore disabled in "Partial Stop Mode". MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 232: I2C Clocking
The chosen clock must remain enabled if the UART0 is to continue operating in all required low-power modes. MCGIRCLK OSCERCLK UART0 clock MCGFLLCLK MCGPLLCLK ÷2 SIM_SOPT2[PLLFLLSEL] SIM_SOPT2[UART0SRC] Figure 3-6. UART0 clock generation MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 233 Module clocks MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 234: Reset And Boot
The information found here discusses basic reset mechanisms and sources. Some modules that cause resets can be configured to cause interrupts instead. Consult the individual peripheral chapters for more information. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 235: Power-On Reset (Por)
When this option is selected, there could be a short period of contention during a POR ramp where the device drives the pin-out low prior to establishing the setting of this option and releasing the reset function on the pin. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 236 (or refreshing) the COP watchdog. If this periodic refreshing does not occur, the watchdog issues a system reset. The COP reset causes RCM_SRS0[WDOG] to set. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 237 Status field (MCG_S[LOLS0]) becomes set, the MCU resets. RCM_SRS0[LOL] is set to indicate this reset source. NOTE This reset source does not cause a reset if the chip is in any stop mode. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 238: Mcu Resets
Set the Core Hold Reset field in the MDM-AP control register to hold the core in reset as the rest of the chip comes out of system reset. 4.2.3 MCU resets A variety of resets are generated by the MCU to reset different modules. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 239 The Early Chip Reset asserts on all reset sources. It resets only the flash memory module. It negates before flash memory initialization begins ("earlier" than when the Chip Reset negates). MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 240: Reset Pin
• MDM-AP (MDM control and status registers) CDBGRSTREQ does not reset the debug-related registers within the following modules: • CM0+ core (core debug registers: DHCSR, DCRSR, DCRDR, DEMCR) • BPU MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 241: Boot
For more details on programming the option byte, see the flash memory chapter. 1. CDBGRSTREQ does not affect AHB resources so that debug resources on the private peripheral bus are available during System Reset. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 242 Core and system clock divider (OUTDIV1) is 0x3 (divide by 4). Core and system clock divider (OUTDIV1) is 0x1 (divide by 2). Core and system clock divider (OUTDIV1) is 0x0 (divide by 1). MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 243: Boot Sequence
NMI interrupt. The processor executes an Exception Entry and reads the NMI interrupt handler address from vector-table offset 8. The CPU begins execution at the NMI interrupt handler. Subsequent system resets follow this same reset flow. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 244: Power Management
If configured, a DMA request (using the asynchronous DMA wakeup) can also be used to exit Partial Stop for the duration of a DMA transfer before the device is transitioned back into PSTOP2. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 245: Dma Wakeup
Stop mode and then requesting bus slaves to enter Stop mode. In STOP and VLPS modes the MCG and PMC would then also enter their appropriate modes. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 246: Compute Operation
VLPS mode. The MCG, PMC, SRAM, and Flash read port are not affected by Compute Operation, although the Flash register interface is disabled. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 247: Peripheral Doze
• The CPU is in Stop mode, including the entry sequence and for the duration of a DMA wakeup. • The CPU is in Compute Operation, including the entry sequence and for the duration of a DMA wakeup. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 248: Clock Gating
ARM Sleep modes. Stop modes (VLPS, STOP) are similar to ARM Sleep Deep mode. The Very Low Power Run (VLPR) operating mode can drastically reduce runtime power when the maximum bus frequency is not required to handle the application needs. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 249 • Most peripherals are in state retention mode (with clocks Interrupt stopped), but OSC, LLWU,LPTMR, RTC, CMP, TSI can be used. • NVIC is disabled; LLWU is used to wake up. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 250: Entering And Exiting Power Modes
On VLLS recoveries, the I/O pins continue to be held in a static state after code execution begins, allowing software to reconfigure the system before unlocking the I/O. RAM is retained in VLLS3 only. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 251: Module Operation In Low-Power Modes
Brown-out ON in VLLS1/3, Detection optionally disabled in VLLS0 Async operation Async operation static Async operation in CPO Watchdog static static static Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 252 500 kbit/s, 500 kbit/s, mode receive mode receive slave mode 250 slave mode 250 FF in PSTOP2 kbit/s kbit/s Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 253 OFF in VLLS0 static in CPO FF in PSTOP2 12-bit DAC static static static static static in CPO FF in PSTOP2 Human-machine interfaces Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 254 VLLSx only supports low speed external pin to pin or external pin to DAC compares. Windowed, sampled & filtered modes of operation are not available while in Stop, VLPS, LLS, or VLLSx modes. 7. TSI wake-up from all low-power modes is limited to a single selectable pin. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 255 Module operation in low-power modes MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 256: Debug
SWD_DIO Input / Output Serial Wire Debug Data Input/Output The SWD_DIO pin is used by an external debug tool for communication and device control. This pin is pulled up internally. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 257: Swd Status And Control Registers
Table 6-2. MDM-AP register summary Address Register Description 0x0100_0000 Status MDM-AP Status Register 0x0100_0004 Control MDM-AP Control Register 0x0100_00FC Read-only identification register that always reads as 0x001C_0020 MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 258: Mdm-Ap Control Register
Set to disable debug. Clear to allow debug operation. When set, it overrides the C_DEBUGEN bit within the DHCSR and force disables Debug logic. Debug Request Set to force the core to halt. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 259: Mdm-Ap Status Register
This bit is used by the debugger to clear the sticky LLS and VLLSx mode entry status bits. This bit is asserted and cleared by the debugger. 8 – Reserved for future use 1. Command available in secure mode MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 260 Once communication is reestablished, this bit indicates that the system had been in LLS. Since the debug modules held their state during LLS, they do not need to be reconfigured. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 261: Debug Resets
• SYSRESETREQ field in the NVIC Application Interrupt and Reset control register • A system reset in the DAP control register which allows the debugger to hold the core in reset. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 262: Micro Trace Buffer (Mtb)
Stop or VLPS, FCLK continues to run to support core register access. In these modes in which FCLK is left active the debug modules have access to core registers but not to system memory resources accessed via the crossbar. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 263: Debug And Security
In the secure state, the debugger still has access to the status register and can determine the current security state of the device. In the case of a secure device, the debugger has the capability of only performing a mass erase operation. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 264: Port Control And Interrupts (Port)
• Support for interrupt or DMA request configured per pin • Asynchronous wake-up in low-power modes • Pin interrupt is functional in all digital pin muxing modes • Port control MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 265: Modes Of Operation
In Stop mode, the PORT can be configured to exit the Low-Power mode via an asynchronous wake-up signal if an enabled interrupt is detected. 7.2.2.4 Debug mode In Debug mode, PORT operates normally. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 266: External Signal Description
Pin Control Register n (PORTA_PCR0) See section 7.5.1/141 4004_9004 Pin Control Register n (PORTA_PCR1) See section 7.5.1/141 4004_9008 Pin Control Register n (PORTA_PCR2) See section 7.5.1/141 Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 267 Pin Control Register n (PORTB_PCR0) See section 7.5.1/141 4004_A004 Pin Control Register n (PORTB_PCR1) See section 7.5.1/141 4004_A008 Pin Control Register n (PORTB_PCR2) See section 7.5.1/141 Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 268 Pin Control Register n (PORTC_PCR0) See section 7.5.1/141 4004_B004 Pin Control Register n (PORTC_PCR1) See section 7.5.1/141 4004_B008 Pin Control Register n (PORTC_PCR2) See section 7.5.1/141 Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 269 4004_C000 Pin Control Register n (PORTD_PCR0) See section 7.5.1/141 4004_C004 Pin Control Register n (PORTD_PCR1) See section 7.5.1/141 4004_C008 Pin Control Register n (PORTD_PCR2) See section 7.5.1/141 Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 270 4004_D000 Pin Control Register n (PORTE_PCR0) See section 7.5.1/141 4004_D004 Pin Control Register n (PORTE_PCR1) See section 7.5.1/141 4004_D008 Pin Control Register n (PORTE_PCR2) See section 7.5.1/141 Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 271 4004_D080 Global Pin Control Low Register (PORTE_GPCLR) (always 0000_0000h 7.5.2/144 reads 0) 4004_D084 Global Pin Control High Register (PORTE_GPCHR) (always 0000_0000h 7.5.3/144 reads 0) 4004_D0A0 Interrupt Status Flag Register (PORTE_ISFR) 0000_0000h 7.5.4/145 MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 272: Pin Control Register N (Portx_Pcrn)
This field is read-only for pins that do not support interrupt generation. The pin interrupt configuration is valid in all digital pin muxing modes. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 273 Alternative 5 (chip-specific). Alternative 6 (chip-specific). Alternative 7 (chip-specific). This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 274 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 275: Global Pin Control Low Register (Portx_Gpclr)
Corresponding Pin Control Register is updated with the value in GPWD. GPWD Global Pin Write Data Write value that is written to all Pin Control Registers bits [15:0] that are selected by GPWE. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 276: Interrupt Status Flag Register (Portx_Isfr)
The lower half of the Pin Control register configures the following functions for each pin within the 32-bit port. • Pullup or pulldown enable on selected pins • Drive strength and slew rate configuration on selected pins MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 277: Global Pin Control
The global pin control registers are write-only registers, that always read as 0. 7.6.3 External interrupts The external interrupt capability of the PORT module is available in all digital pin muxing modes provided the PORT module is enabled. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 278 During Stop mode, the interrupt status flag for any enabled interrupt is asynchronously set if the required level or edge is detected. This also generates an asynchronous wake-up signal to exit the Low-Power mode. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 279 Functional description MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 280: System Integration Module (Sim)
• TPM external clock and input capture selection • UART receive/transmit source selection/configuration 8.2 Memory map and register definition The SIM module contains many bitfields for selecting the clock source and dividers for various module clocks. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 281 4004_805C Unique Identification Register Mid Low (SIM_UIDML) See section 8.2.15/171 4004_8060 Unique Identification Register Low (SIM_UIDL) See section 8.2.16/171 4004_8100 COP Control Register (SIM_COPC) 0000_000Ch 8.2.17/172 4004_8104 Service COP (SIM_SRVCOP) 0000_0000h 8.2.18/173 MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 282: System Options Register 1 (Sim_Sopt1)
This field is reserved. Reserved This read-only field is reserved and always has the value 0. Reserved This field is reserved. This read-only field is reserved and always has the value 0. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 283: System Options Register 2 (Sim_Sopt2)
TPM Clock Source Select TPMSRC Selects the clock source for the TPM counter clock Clock disabled MCGFLLCLK clock, or MCGPLLCLK/2 OSCERCLK clock MCGIRCLK clock Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 284 RTC 1 Hz clock is output on the RTC_CLKOUT pin. OSCERCLK clock is output on the RTC_CLKOUT pin. Reserved This field is reserved. This read-only field is reserved and always has the value 0. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 285: System Options Register 4 (Sim_Sopt4)
NOTE: The selected pin must also be configured for the TPM external clock function through the appropriate pin control register in the port control module. TPM0 external clock driven by TPM_CLKIN0 pin. TPM0 external clock driven by TPM_CLKIN1 pin. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 286: System Options Register 5 (Sim_Sopt5)
This field is reserved. This read-only field is reserved and always has the value 0. 8.2.4 System Options Register 5 (SIM_SOPT5) Address: 4004_7000h base + 1010h offset = 4004_8010h Reset Reset MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 287 UART0 Transmit Data Source Select Selects the source for the UART0 transmit data. UART0_TX pin UART0_TX pin modulated with TPM1 channel 0 output UART0_TX pin modulated with TPM2 channel 0 output Reserved MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 288: System Options Register 7 (Sim_Sopt7)
ADC0_RA register. Pre-trigger ADHWTSB is selected, thus ADC0 will use ADC0_SC1B configuration for the next ADC conversion and store the result in ADC0_RB register. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 289: System Device Identification Register (Sim_Sdid)
REVID field: Device specific value. • PINID field: Device specific value. SIM_SDID field descriptions Field Description 31–28 Kinetis family ID FAMID Specifies the Kinetis family of the device. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 290 This read-only field is reserved and always has the value 0. PINID Pincount Identification Specifies the pincount of the device. 0000 16-pin 0001 24-pin 0010 32-pin 0011 36-pin 0100 48-pin 0101 64-pin Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 291: System Clock Gating Control Register 4 (Sim_Scgc4)
Controls the clock gate to the SPI1 module. Clock disabled Clock enabled SPI0 Clock Gate Control SPI0 Controls the clock gate to the SPI0 module. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 292 Controls the clock gate to the I C1 module. Clock disabled Clock enabled I2C0 Clock Gate Control I2C0 Controls the clock gate to the I C0 module. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 293: System Clock Gating Control Register 5 (Sim_Scgc5)
This read-only field is reserved and always has the value 0. Port E Clock Gate Control PORTE Controls the clock gate to the Port E module. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 294 This read-only field is reserved and always has the value 1. Low Power Timer Access Control LPTMR Controls software access to the Low Power Timer module. Access disabled Access enabled MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 295: System Clock Gating Control Register 6 (Sim_Scgc6)
Controls the clock gate to the ADC0 module. Clock disabled Clock enabled TPM2 Clock Gate Control TPM2 Controls the clock gate to the TPM2 module. Clock disabled Clock enabled Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 296 Controls the clock gate to the flash memory. Flash reads are still supported while the flash memory is clock gated, but entry into low power modes is blocked. Clock disabled Clock enabled MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 297: System Clock Gating Control Register 7 (Sim_Scgc7)
OUTDIV1 field: The reset value depends on the FTFA_FOPT[LPBOOT]. It is loaded with 0000 (divide by 1), 0001 (divide by 2), 0011 (divide by 4, or 0111 (divide by 8). MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 298 0001 (divide by 2). Divide-by-1. Divide-by-2. Divide-by-3. Divide-by-4. Divide-by-5. Divide-by-6. Divide-by-7. Divide-by-8. Reserved This field is reserved. This read-only field is reserved and always has the value 0. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 299: Flash Configuration Register 1 (Sim_Fcfg1)
256 KB of program flash memory, 8 KB protection region 1111 128 KB of program flash memory, 4 KB protection region256 KB of program flash memory, 8 KB protection region Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 300: Flash Configuration Register 2 (Sim_Fcfg2)
Address: 4004_7000h base + 1050h offset = 4004_8050h MAXADDR0 MAXADDR1 Reset Reset * Notes: • MAXADDR0 field: Device specific value indicating amount of implemented flash. • MAXADDR1 field: Device specific value indicating amount of implemented flash. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 301: Unique Identification Register Mid-High (Sim_Uidmh)
UID field: Device specific value. SIM_UIDMH field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Unique Identification Unique identification for the device. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 302: Unique Identification Register Mid Low (Sim_Uidml)
8.2.16 Unique Identification Register Low (SIM_UIDL) Address: 4004_7000h base + 1060h offset = 4004_8060h Reset * Notes: • UID field: Device specific value. SIM_UIDL field descriptions Field Description Unique Identification Unique identification for the device. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 303: Cop Control Register (Sim_Copc)
COP Windowed Mode COPW Windowed mode is supported only when COP is running from the bus clock. The COP window is opened three quarters through the timeout period. Normal mode Windowed mode MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 304: Service Cop (Sim_Srvcop)
Service COP Register Write 0x55 and then 0xAA (in that order) to reset the COP timeout counter, writing any other value will generate a system reset. 8.3 Functional description Introduction section. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 305 Functional description MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 306: System Mode Controller (Smc)
The WFI or WFE instruction is used to invoke Sleep and Deep Sleep modes. Run, Wait, and Stop are the common terms used for the primary operating modes of Freescale microcontrollers. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 307 The core clock is gated off. System clocks to other masters and bus clocks are gated off after all stop acknowledge signals from supporting peripherals are valid. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 308: Memory Map And Register Descriptions
MCU enters the low power mode. Failure to do this may result in the low power mode not being entered correctly. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 309: Power Mode Protection Register (Smc_Pmprot)
Provided the appropriate control bits are set up in PMCTRL, this write-once field allows the MCU to enter any very-low-power mode (VLPR, VLPW, and VLPS). Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 310: Power Mode Control Register (Smc_Pmctrl)
Chip POR not VLLS. See the Reset section details for more information. Address: 4007_E000h base + 1h offset = 4007_E001h Read STOPA Reserved RUNM STOPM Write Reset MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 311: Stop Control Register (Smc_Stopctrl)
Reserved 9.3.3 Stop Control Register (SMC_STOPCTRL) The STOPCTRL register provides various control bits allowing the user to fine tune power consumption during the stop mode selected by the STOPM field. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 312 This bit is reserved for future expansion and should always be written zero. VLLSM VLLS Mode Control This field controls which VLLS sub-mode to enter if STOPM = VLLSx. VLLS0 VLLS1 Reserved VLLS3 Reserved Reserved Reserved Reserved MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 313: Power Mode Status Register (Smc_Pmstat)
9.4 Functional description 9.4.1 Power mode transitions The following figure shows the power mode state transitions available on the chip. Any reset always brings the MCU back to the normal RUN state. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 314 Sleep-now or sleep-on-exit modes entered with SLEEPDEEP clear, controlled in System Control Register in ARM core. See note. WAIT Interrupt or Reset STOP PMCTRL[RUNM]=00, PMCTRL[STOPM]=000 Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 315 VLPR VLLSx PMPROT[AVLLS]=1, PMCTRL[STOPM]=100, STOPCTRL[LLSM]=x (VLLSx), Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, which is controlled in System Control Register in ARM core. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 316: Power Mode Entry/Exit Sequencing
The SMC manages the system's entry into and exit from all power modes. This diagram illustrates the connections of the SMC with other system components in the chip that are necessary to sequence the system through all power modes. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 317 5. Clock generators are disabled in the MCG. 6. The on-chip regulator in the PMC and internal power switches are configured to meet the power consumption goals for the targeted low-power mode. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 318: Run Modes
RUN and VLPR mode clocking configuration. 9.4.3 Run modes The run modes supported by this device can be found here. • Run (RUN) • Very Low-Power Run (VLPR) MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 319 In addition, do not modify the clock source in the MCG module or any clock divider registers. Module clock enables in the SIM can be set, but not cleared. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 320: Wait Modes
To further reduce power in this mode, disable the clocks to unused modules by clearing the peripherals' corresponding clock gating control bits in the SIM (or PCC). VLPR mode restrictions also apply to VLPW. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 321: Stop Modes
STOP mode is entered via the sleep-now or sleep-on-exit with the SLEEPDEEP bit set in the System Control Register in the ARM core. The MCG module can be configured to leave the reference clocks running. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 322 Before entering LLS mode, the user should configure the Low-Leakage Wake-up (LLWU) module to enable the desired wake-up sources. The available wake-up sources in LLS are detailed in the chip configuration details for this device. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 323 When entering VLLS, each I/O pin is latched as configured before executing VLLS. Because all digital logic in the MCU is powered off, all port and peripheral data is lost during VLLS. This information must be restored before PMC_REGSC[ACKISO] is set. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 324: Debug In Low Power Modes
The VLLDBGACK bit is cleared by the debugger (or can be left set as is) or clears automatically due to the reset generated as part of the next VLLS recovery. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 325 Functional description MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 326: Power Management Controller (Pmc)
(V ) or low (V ). The trip voltage is selected by LVDH LVDL LVDSC1[LVDV]. The LVD is disabled upon entering VLPx, LLS, and VLLSx modes. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 327: Lvd Reset Operation
LVD voltage. The LVW also has an interrupt, which is enabled by setting LVDSC2[LVWIE]. If enabled, an LVW interrupt request occurs when LVDSC2[LVWF] is set. LVDSC2[LVWF] is cleared by writing 1 to LVDSC2[LVWACK]. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 328: I/O Retention
Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) Low Voltage Detect Status And Control 1 register 4007_D000 10.5.1/198 (PMC_LVDSC1) Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 329: Low Voltage Detect Status And Control 1 Register (Pmc_Lvdsc1)
PMC_LVDSC1 field descriptions Field Description Low-Voltage Detect Flag LVDF This read-only status field indicates a low-voltage detect event. Low-voltage event not detected Low-voltage event detected Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 330: Low Voltage Detect Status And Control 2 Register (Pmc_Lvdsc2)
LVWV is reset solely on a POR Only event. The other fields of the register are reset on Chip Reset Not VLLS. For more information about these reset types, refer to the Reset section details. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 331: Regulator Status And Control Register (Pmc_Regsc)
CMP and ADC. The internal regulator provides a status bit (REGONS) indicating the regulator is in run regulation. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 332 Certain peripherals and I/O pads are in an isolated and latched state. Regulator In Run Regulation Status REGONS This read-only field provides the current status of the internal voltage regulator. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 333 This field is reserved. Reserved NOTE: This reserved bit must remain cleared (set to 0). Bandgap Buffer Enable BGBE Enables the bandgap buffer. Bandgap buffer not enabled Bandgap buffer enabled MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 334: Low-Leakage Wakeup Unit (Llwu)
The LLWU module also includes two optional digital pin filters for the external wakeup pins. AN4503: Power Management for Kinetis MCUs for further details on using the LLWU. 11.2.1 Features The LLWU module features include: MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 335: Modes Of Operation
The LLWU is not active in all non-low leakage modes where detection and control logic are in a static state. The LLWU registers are accessible in non-low leakage modes and are available for configuring and reading status when bus transactions are possible. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 336: Block Diagram
Upon an exit from the LLS or VLLSx mode, the LLWU becomes inactive. 11.2.3 Block diagram The following figure is the block diagram for the LLWU module. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 337: Llwu Signal Descriptions
The external wakeup input pins can be enabled to detect either rising-edge, falling-edge, or on any change. Table 11-1. LLWU signal descriptions Signal Description LLWU_Pn Wakeup inputs (n = 0-15 ) MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 338: Memory Map/Register Definition
4007_C006 LLWU Flag 2 register (LLWU_F2) 11.4.7/215 4007_C007 LLWU Flag 3 register (LLWU_F3) 11.4.8/217 4007_C008 LLWU Pin Filter 1 register (LLWU_FILT1) 11.4.9/219 4007_C009 LLWU Pin Filter 2 register (LLWU_FILT2) 11.4.10/220 MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 339: Llwu Pin Enable 1 Register (Llwu_Pe1)
Enables and configures the edge detection for the wakeup pin. External input pin disabled as wakeup input External input pin enabled with rising edge detection Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 340: Llwu Pin Enable 2 Register (Llwu_Pe2)
Enables and configures the edge detection for the wakeup pin. External input pin disabled as wakeup input External input pin enabled with rising edge detection Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 341: Llwu Pin Enable 3 Register (Llwu_Pe3)
Enables and configures the edge detection for the wakeup pin. External input pin disabled as wakeup input External input pin enabled with rising edge detection Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 342: Llwu Pin Enable 4 Register (Llwu_Pe4)
Enables and configures the edge detection for the wakeup pin. External input pin disabled as wakeup input External input pin enabled with rising edge detection Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 343: Llwu Module Enable Register (Llwu_Me)
Chip Reset not VLLS. See the Introduction details for more information. Address: 4007_C000h base + 4h offset = 4007_C004h Read WUME7 WUME6 WUME5 WUME4 WUME3 WUME2 WUME1 WUME0 Write Reset MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 344 Wakeup Module Enable For Module 0 WUME0 Enables an internal module as a wakeup source input. Internal module flag not used as wakeup source Internal module flag used as wakeup source MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 345: Llwu Flag 1 Register (Llwu_F1)
Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag, write a 1 to WUF5. LLWU_P5 input was not a wakeup source LLWU_P5 input was a wakeup source Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 346: Llwu Flag 2 Register (Llwu_F2)
The external wakeup flags are read-only and clearing a flag is accomplished by a write of a 1 to the corresponding WUFx bit. The wakeup flag (WUFx), if set, will remain set if the associated WUPEx bit is cleared. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 347 1 to WUF11. LLWU_P11 input was not a wakeup source LLWU_P11 input was a wakeup source Wakeup Flag For LLWU_P10 WUF10 Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 348: Llwu Flag 3 Register (Llwu_F3)
Chip Reset not VLLS. See the Introduction details for more information. Address: 4007_C000h base + 7h offset = 4007_C007h Read MWUF7 MWUF6 MWUF5 MWUF4 MWUF3 MWUF2 MWUF1 MWUF0 Write Reset MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 349 Module 1 input was not a wakeup source Module 1 input was a wakeup source Wakeup flag For module 0 MWUF0 Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 350: Llwu Pin Filter 1 Register (Llwu_Filt1)
Filter any edge detect enabled This field is reserved. Reserved This read-only field is reserved and always has the value 0. FILTSEL Filter Pin Select Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 351: Llwu Pin Filter 2 Register (Llwu_Filt2)
Filter any edge detect enabled This field is reserved. Reserved This read-only field is reserved and always has the value 0. FILTSEL Filter Pin Select Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 352: Functional Description
11.5.1 LLS mode Wakeup events triggered from either an external pin input or an internal module interrupt, result in a CPU interrupt flow to begin user code execution. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 353: Vlls Modes
LLWU flag from being falsely set when PMC_REGSC[ACKISO] is cleared. The signal selected as a wake-up source pin must be a digital pin, as selected in the pin mux control. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 354: Reset Control Module (Rcm)
System Reset Status Register 0 (RCM_SRS0) 12.2.1/224 4007_F001 System Reset Status Register 1 (RCM_SRS1) 12.2.2/225 4007_F004 Reset Pin Filter Control register (RCM_RPFC) 12.2.3/226 4007_F005 Reset Pin Filter Width register (RCM_RPFW) 12.2.4/227 MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 355: System Reset Status Register 0 (Rcm_Srs0)
Reset not caused by watchdog timeout Reset caused by watchdog timeout This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 356: System Reset Status Register 1 (Rcm_Srs1)
• POR (including LVD) — 0x00 • LVD (without POR) — 0x00 • VLLS mode wakeup — 0x00 • Other reset — a bit is set if its corresponding reset source caused the reset MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 357: Reset Pin Filter Control Register (Rcm_Rpfc)
This read-only field is reserved and always has the value 0. 12.2.3 Reset Pin Filter Control register (RCM_RPFC) NOTE The reset values of bits 2-0 are for Chip POR only. They are unaffected by other reset types. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 358: Reset Pin Filter Width Register (Rcm_Rpfw)
The reset values of the bits in the RSTFLTSEL field are for Chip POR only. They are unaffected by other reset types. Address: 4007_F000h base + 5h offset = 4007_F005h Read RSTFLTSEL Write Reset MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 359 Bus clock filter count is 28 11100 Bus clock filter count is 29 11101 Bus clock filter count is 30 11110 Bus clock filter count is 31 11111 Bus clock filter count is 32 MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 360: Bit Manipulation Engine (Bme)
KB space based at 0x400F_F000 for GPIO accesses. This organization provides compatibility with the Kinetis K Family. Attempted accesses to the memory space located between 0x4008_0000 - 0x400F_EFFF are error terminated due to an illegal address. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 361: Overview
AHB system bus protocol into the IPS/APB protocol used by the attached slave peripherals. 13.1.2 Features The key features of the BME include: • Lightweight implementation of decorated storage for selected address spaces MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 362: Modes Of Operation
4 KB space based at 0x400F_F000 for GPIO accesses; the decorated address space is mapped to the 448 MB region located at 0x4400_0000–0x5FFF_FFFF. 13.3 Functional description Information found here details the specific functions supported by the BME. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 363: Bme Decorated Stores
AHB data phase, and then the write is performed in the second AHB data phase. A generic timing diagram of a decorated store showing a peripheral bit field insert operation is shown as follows: MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 364 NOTE Any wait states inserted by the slave device are simply passed through the BME back to the master input bus, stalling the AHB transaction cycle for cycle. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 365 Table 13-1. Cycle definitions of decorated store: logical AND Pipeline stage Cycle BME AHB_ap Forward addr to memory; Recirculate captured addr + <next> Decode decoration; Convert attr to memory as slave_wt Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 366 & 0xE00FFFFF, size] // memory read tmp | wdata // modify mem[accessAddress & 0xE00FFFFF, size] = tmp // memory write The cycle-by-cycle BME operations are detailed in the following table. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 367 & 0xE00FFFFF, size] // memory read tmp ^ wdata // modify mem[accessAddress & 0xE00FFFFF, size] = tmp // memory write The cycle-by-cycle BME operations are detailed in the following table. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 368 The "-" indicates an address bit "don't care". Note, unlike the other decorated store operations, BFI uses addr[19] as the least significant bit in the "w" specifier and not as an address bit. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 369 Capture address, attributes BME AHB_dp <previous> Perform memory read; Form Perform write sending bit mask; Form bitwise registered data to memory ((mask) ? wdata : rdata)) and capture destination data in register MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 370: Bme Decorated Loads
AHB data phase. This is the only decorated transaction that is not an atomic read-modify-write, as it is a simple data read. A generic timing diagram of a decorated load showing a peripheral load-and-set 1-bit operation is shown as follows. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 371 4. Cycle x+2, second AHB data phase: The selected original 1-bit is right-justified, zero-filled and then driven onto the input read data bus, while the registered write data is sourced onto the output write data bus MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 372 • Cycle x, 1st AHB address phase: Read from input bus is translated into a read operation on the output bus with the actual memory address (with the decoration removed) and then captured in a register • Cycle x+1, 2nd AHB address phase: Idle cycle MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 373 // generate bit mask rdata = (tmp & mask) >> b // read data returned to core tmp & ~mask // modify mem[accessAddress & 0xE00FFFFF, size] = tmp // memory write MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 374 // decorated load-and-set 1 mem[accessAddress & 0xE00FFFFF, size] // memory read mask 1 << b // generate bit mask rdata = (tmp & mask) >> b // read data returned to core MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 375 13-11, where addr[30:29] = 10 for peripheral, addr[28] = 1 specifies the unsigned bit field extract operation, addr[27:23] is "b", the LSB identifier, addr[22:19] is "w", the bit field width minus 1 identifier, and mem_addr[18:0] specifies the address MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 376: Additional Details On Decorated Addresses And Gpio Accesses
AND, OR, XOR, LAC1 and LAS1, this bit functions as a true address bit, while for BFI and UBFX, this bit defines the least significant bit of the "w" bit field specifier. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 377: Application Information
:: [addr] "r" (ADDR), [wdata] "r" (WDATA) : "r2", "r3"); #define IOANDB(ADDR,WDATA) __asm("ldr r3, =(1<<26);" "orr r3, %[addr];" "mov r2, %[wdata];" "strb r2, [r3];" :: [addr] "r" (ADDR), [wdata] "r" (WDATA) : "r2", "r3"); MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 378 :: [addr] "r" (ADDR), [wdata] "r" (WDATA) : "r2", "r3"); #define IOXORB(ADDR,WDATA) __asm("ldr r3, =(3<<26);" "orr r3, %[addr];" "mov r2, %[wdata];" "strb r2, [r3];" :: [addr] "r" (ADDR), [wdata] "r" (WDATA) : "r2", "r3"); MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 379 Application information MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 380: Miscellaneous Control Module (Mcm)
MCM memory map Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) Crossbar Switch (AXBS) Slave Configuration F000_3008 0007h 14.2.1/250 (MCM_PLASC) Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 381: Crossbar Switch (Axbs) Slave Configuration (Mcm_Plasc)
Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port. A bus slave connection to AXBS input port n is absent. A bus slave connection to AXBS input port n is present. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 382: Crossbar Switch (Axbs) Master Configuration (Mcm_Plamc)
DFCS EFDS Description Speculation buffer is on for instruction and off for data. Speculation buffer is on for instruction and on for data. Speculation buffer is off. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 383 This read-only field is reserved and always has the value 0. Enable Stalling Flash Controller ESFC Enables stalling flash controller when flash is busy. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 384 Arbitration select Fixed-priority arbitration for the crossbar masters Round-robin arbitration for the crossbar masters Reserved This field is reserved. This read-only field is reserved and always has the value 0. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 385: Compute Operation Control Register (Mcm_Cpo)
Compute operation entry has completed or compute operation exit has not completed. Compute Operation Request CPOREQ This bit is auto-cleared by vector fetching if CPOWOI = 1. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 386 Chapter 14 Miscellaneous Control Module (MCM) MCM_CPO field descriptions (continued) Field Description Request is cleared. Request Compute Operation. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 387 Memory map/register descriptions MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 388: Micro Trace Buffer (Mtb)
This document details the functionality of both the MTB_RAM and MTB_DWT capabilities. 15.1.1 Overview A generic block diagram of the processor core and platform for this class of ultra low-end microcontrollers is shown as follows: MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 389 PC value changes non-sequentially. A non-sequential PC change can occur during branch instructions or during exception entry. The processor can cause a trace packet to be generated for any instruction. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 390 For an exception return operation, two packets are generated: • The first packet has the: • Source address field set to the address of the instruction that causes the exception return, BX or POP. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 391: Features
• Program trace information in RAM available to MCU's application code or external debugger • Program trace watchpoint configuration accessible by MCU's application code or debugger • Location and size of RAM trace buffer is configured by software MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 392: Modes Of Operation
PC >> 1. ATOMIC Input Indicates the processor is performing non-instruction related activities. EDBGRQ Output Request for the processor to enter the Debug state, if enabled, and halt. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 393: Memory Map And Register Definition
See section 15.3.1.3/ F000_0008 MTB Flow Register (MTB_FLOW) Undefined 15.3.1.4/ F000_000C MTB Base Register (MTB_BASE) Undefined 15.3.1.5/ F000_0F00 Integration Mode Control Register (MTB_MODECTRL) 0000_0000h Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 394 F000_0FF0 Component ID Register (MTB_COMPID0) See section 15.3.1.15/ F000_0FF4 Component ID Register (MTB_COMPID1) See section 15.3.1.15/ F000_0FF8 Component ID Register (MTB_COMPID2) See section 15.3.1.15/ F000_0FFC Component ID Register (MTB_COMPID3) See section MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 395 See the MTB_FLOW register description for more details. Address: F000_0000h base + 0h offset = F000_0000h POINTER Reset POINTER Reset MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 396 If MTB_FLOW[WATERMARK] is used to stop tracing or to halt the processor, MTB_MASTER[MASK] must still be set to a value that prevents MTB_POSITION[POINTER] from wrapping before it reaches the MTB_FLOW[WATERMARK] value. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 397 1, then only privileged AHB read and write accesses to the RAM are permitted and user accesses are RAZ/WI. The HPROT[1] signal determines if an access is a user or privileged mode reference. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 398 Cortex-M0+ processor to enter the Debug state. To enter Debug state, the Cortex-M0+ processor might have to perform additional branch type operations. Therefore, the MTB_FLOW[WATERMARK] field must be set below the final entry in the trace buffer region. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 399 Cortex-M0+ processor by asserting the EDBGRQ signal. AUTOSTOP AUTOSTOP If this field is 1 and WATERMARK is equal to MTB_POSITION[POINTER], then MTB_MASTER[EN] is automatically set to 0. This stops tracing. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 400 It is hardwired to specific values used during the auto-discovery process by an external debug agent. Address: F000_0000h base + F00h offset = F000_0F00h MODECTRL Reset MTB_MODECTRL field descriptions Field Description MODECTRL MODECTRL Hardwired to 0x0000_0000 MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 401 0. It is hardwired to specific values used during the auto- discovery process by an external debug agent. Address: F000_0000h base + FA4h offset = F000_0FA4h TAGCLEAR Reset MTB_TAGCLEAR field descriptions Field Description TAGCLEAR TAGCLEAR Hardwired to 0x0000_0000 MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 402 Where functionality changes on a given security level, this change must be reported in this register. It is connected to specific signals used during the auto-discovery process by an external debug agent. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 403 This register indicates the device architecture. It is hardwired to specific values used during the auto-discovery process by an external debug agent. Address: F000_0000h base + FBCh offset = F000_0FBCh DEVICEARCH Reset MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 404 This register indicates the device type ID. It is hardwired to specific values used during the auto-discovery process by an external debug agent. Address: F000_0000h base + FCCh offset = F000_0FCCh DEVICETYPID Reset MTB_DEVICETYPID field descriptions Field Description DEVICETYPID DEVICETYPID Hardwired to 0x0000_0031. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 405: Mtb_Dwt Memory Map
Component ID0 is hardwired to 0x0000_000D; ID1 to 0x0000_0090; ID2 to 0x0000_0005; ID3 to 0x0000_00B1. 15.3.2 MTB_DWT Memory Map The MTB_DWT programming model supports a very simplified subset of the v7M debug architecture and follows the standard ARM DWT definition. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 406 F000_1FF0 Component ID Register (MTBDWT_COMPID0) See section 15.3.2.10/ F000_1FF4 Component ID Register (MTBDWT_COMPID1) See section 15.3.2.10/ F000_1FF8 Component ID Register (MTBDWT_COMPID2) See section 15.3.2.10/ F000_1FFC Component ID Register (MTBDWT_COMPID3) See section MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 407 MTBDWT_CTRL[8:5] = POSTINIT = 0, cycle counter is not supported MTBDWT_CTRL[4:1] = POSTPRESET = 0, cycle counter is not supported MTBDWT_CTRL[0] = CYCCNTENA = 0, cycle counter is not supported MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 408 [31:x]. The maximum MASK value is 24, producing a 16 Mbyte mask. An attempted write of a MASK value > 24 is limited by the MTBDWT hardware to 24. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 409 FUNCTION Reset MTBDWT_FCT0 field descriptions Field Description 31–25 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 410 Disabled. 0100 Instruction fetch. 0101 Data operand read. 0110 Data operand write. 0111 Data operand (read + write). others Reserved. Any attempts to use this value results in UNPREDICTABLE behavior. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 411 If this read-only flag is asserted, it indicates the operation defined by the FUNCTION field occurred since the last read of the register. Reading the register clears this bit. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 412 MTB's control logic by setting the appropriate enable bits, MTB_MASTER[TSTARTEN, TSTOPEN]. In the event of simultaneous assertion of both TSTART and TSTOP, TSTART takes priority. Address: F000_1000h base + 200h offset = F000_1200h NUMCOMP Reset MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 413 • Data match in MTBDWT_COMP0 and address match in MTBDWT_COMP1 when MTBDWT_FCT0[DATAVMATCH, DATAVADDR0] = {1,1} Trigger TSTOP based on the assertion of MTBDWT_FCT0[MATCHED]. Trigger TSTART based on the assertion of MTBDWT_FCT0[MATCHED]. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 414 This register indicates the device type ID. It is hardwired to specific values used during the auto-discovery process by an external debug agent. Address: F000_1000h base + FCCh offset = F000_1FCCh DEVICETYPID Reset MTBDWT_DEVICETYPID field descriptions Field Description DEVICETYPID DEVICETYPID Hardwired to 0x0000_0004. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 415: System Rom Memory Map
Component ID0 is hardwired to 0x0000_000D; ID1 to 0x0000_0090; ID2 to 0x0000_0005; ID3 to 0x0000_00B1. 15.3.3 System ROM Memory Map The System ROM Table registers are also mapped into a sparsely-populated 4 KB address space. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 416 15.3.3.2/ F000_200C End of Table Marker Register (ROM_TABLEMARK) 0000_0000h 15.3.3.3/ F000_2FCC System Access Register (ROM_SYSACCESS) 0000_0001h 15.3.3.4/ F000_2FD0 Peripheral ID Register (ROM_PERIPHID4) See section Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 417 Reset ROM_ENTRYn field descriptions Field Description ENTRY ENTRY MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 418 This register indicates system access. It is hardwired to specific values used during the auto-discovery process by an external debug agent. Address: F000_2000h base + FCCh offset = F000_2FCCh SYSACCESS Reset ROM_SYSACCESS field descriptions Field Description SYSACCESS SYSACCESS Hardwired to 0x0000_0001 MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 419 Reset ROM_COMPIDn field descriptions Field Description COMPID Component ID Component ID0 is hardwired to 0x0000_000D; ID1 to 0x0000_0010; ID2 to 0x0000_0005; ID3 to 0x0000_00B1. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 420: Crossbar Switch Lite (Axbs-Lite)
• Allows concurrent accesses from different masters to different slaves • Up to single-clock 32-bit transfer • Programmable configuration for fixed-priority or round-robin slave port arbitration (see the chip-specific information). MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 421: Memory Map / Register Definition
This is done to save the initial clock of arbitration delay that otherwise would be seen if the same master had to arbitrate to gain control of the slave port. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 422: Peripheral Bridge (Aips-Lite)
The register maps of the peripherals are located on 4-KB boundaries. Each peripheral is allocated one or more 4-KB block(s) of the memory map. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 423: Memory Map/Register Definition
At reset, the default value loaded into the MPRA fields is chip- specific. See the chip configuration details for the value of a particular device. A register field that maps to an unimplemented master or peripheral behaves as read- only-zero. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 424 This read-only field is reserved and always has the value 0. Master 2 Trusted For Read MTR2 Determines whether the master is trusted for read accesses. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 425: Peripheral Access Control Register (Aips_Pacrn)
See this chip's memory map for the assignment of a particular peripheral. The following table shows the location of each peripheral slot's PACR field in the PACR registers. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 426 Address: 0h base + 20h offset + (4d × i), where i=0d to 3d Reset Reset * Notes: • The reset value is chip-dependent and can be found in the AIPS chip-specific information. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 427 Accesses from an untrusted master are allowed. Accesses from an untrusted master are not allowed. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 428 Accesses from an untrusted master are allowed. Accesses from an untrusted master are not allowed. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 429 Accesses from an untrusted master are allowed. Accesses from an untrusted master are not allowed. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 430 Accesses from an untrusted master are allowed. Accesses from an untrusted master are not allowed. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 431: Peripheral Access Control Register (Aips_Pacrn)
Accesses from an untrusted master are allowed. Accesses from an untrusted master are not allowed. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 432 Accesses from an untrusted master are allowed. Accesses from an untrusted master are not allowed. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 433 Accesses from an untrusted master are allowed. Accesses from an untrusted master are not allowed. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 434 Accesses from an untrusted master are allowed. Accesses from an untrusted master are not allowed. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 435: Functional Description
Bus decomposition is terminated by a transfer error caused by an access to an empty register area. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 436: Direct Memory Access Multiplexer (Dmamux)
18.1.1 Overview The Direct Memory Access Multiplexer (DMAMUX) routes DMA sources, called slots, to any of the four DMA channels. This process is illustrated in the following figure. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 437: Features
• Each channel router can be assigned to one of the possible peripheral DMA slots or to one of the always-on slots. 18.1.3 Modes of operation The following operating modes are available: • Disabled mode MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 438: External Signal Description
18.3.1 Channel Configuration register (DMAMUXx_CHCFGn) Each of the DMA channels can be independently enabled/disabled and associated with one of the DMA slots (peripheral slots or always-on slots) in the system. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 439: Functional Description
However, if the procedure outlined in Enabling and configuring sources is followed, the configuration of the DMAMUX may be changed during the normal operation of the system. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 440: Dma Channels With Periodic Triggering Capability
Because of the dynamic nature of the system (due to DMA channel priorities, bus arbitration, interrupt service routine lengths, etc.), the number of clock cycles between a trigger and the actual DMA transfer cannot be guaranteed. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 441 This means that if a trigger is seen, but the peripheral is not requesting a transfer, then that trigger will be ignored. This situation is illustrated in the following figure. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 442: Dma Channels With No Triggering Capability
18.4.2 DMA channels with no triggering capability The other channels of the DMAMUX provide the normal routing functionality as described in Modes of operation. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 443: Always-Enabled Dma Sources
DMA registers after every minor loop. For this option, the DMA channel must be disabled in the DMA channel MUX. • Use an always-enabled DMA source. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 444: Initialization/Application Information
DMA channels that have triggering capability. To configure source #5 transmit for use with DMA channel 1, with periodic triggering capability: 1. Write 0x00 to CHCFG1. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 445 *CHCFG10= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000A); volatile unsigned char *CHCFG11= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000B); volatile unsigned char *CHCFG12= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000C); volatile unsigned char *CHCFG13= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000D); MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 446 *CHCFG12= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000C); volatile unsigned char *CHCFG13= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000D); volatile unsigned char *CHCFG14= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000E); volatile unsigned char *CHCFG15= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000F); MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 447 Initialization/application information In File main.c: #include "registers.h" *CHCFG8 = 0x00; *CHCFG8 = 0x87; MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 448: Dma Controller Module
(DARn), Status register (DSRn), Byte Count register (BCRn), and Control register (DCRn). Collectively, the combined program-visible registers associated with each channel define a transfer control descriptor (TCD). All transfers are dual address, moving MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 449: Features
The DMA provides hardware handshake signals: either a DMA acknowledge (DACK) or a done indicator back to the peripheral. 19.1.2 Features The DMA controller module features: • Four independently programmable DMA controller channels MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 450: Dma Transfer Overview
DMA request. The read data is temporarily held in the DMA channel hardware until the write operation. Two types of single transfers occur: a read from a source address followed by a write to a destination address. See the following figure. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 451: Memory Map/Register Definition
The concatenation of the source and destination address registers, the status and byte count register, and the control register create a 128-bit transfer control descriptor (TCD) that defines the operation of each DMA channel. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 452: Source Address Register (Dma_Sarn)
For more information about the configuration error, see the description of the field of DSR. Address: 4000_8000h base + 100h offset + (16d × i), where i=0d to 3d Reset MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 453: Destination Address Register (Dma_Darn)
Restriction: Bits 31-20 of this register must be written with one of only several allowed values. Each of these allowed values corresponds to a valid region of the device's memory map. The allowed values are: MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 454: Dma Status Register / Byte Count Register (Dma_Dsr_Bcrn)
DMA is configured for 32-bit or 16-bit transfers, respectively, DSRn[CE] is set and no transfer occurs. Address: 4000_8000h base + 108h offset + (16d × i), where i=0d to 3d Reset MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 455 DMA channel is inactive. Cleared when the DMA has finished the last transaction. BSY is set the first time the channel is enabled after a transfer is initiated. Transactions Done DONE Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 456: Dma Control Register (Dma_Dcrn)
EINT SINC SSIZE DINC DSIZE Reset SMOD DMOD LINKCC LCH1 LCH2 Reset DMA_DCRn field descriptions Field Description Enable Interrupt on Completion of Transfer EINT Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 457 The SAR increments by 1, 2, 4 as determined by the transfer size. 21–20 Source Size SSIZE Determines the data size of the source bus cycle for the DMA controller. 32-bit 8-bit Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 458 Defines the size of the destination data circular buffer used by the DMA Controller. If enabled (DMOD value is non-zero), the buffer base address is located on a boundary of the buffer size. The value of this Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 459 Indicates the DMA channel assigned as link channel 1. The link channel number cannot be the same as the currently executing channel, and generates a configuration error if this is attempted (DSRn[CE] is set). DMA Channel 0 DMA Channel 1 Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 460: Functional Description
DCRn[START] or when the selected peripheral request asserts and DCRn[ERQ] is set. Setting DCRn[ERQ] enables recognition of the peripheral DMA requests. Selecting between cycle-steal and continuous modes minimizes bus usage for either type of request. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 461: Channel Initialization And Startup
The DMA module itself does not have a mechanism to prevent writes to registers during a channel's execution. General guidelines for programming the DMA are: • TCDn is initialized. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 462: Dual-Address Data Transfer Mode
• Changes to DCRn are effective immediately while the channel is active. To avoid problems with changing a DMA channel setup, write a one to DSRn[DONE] to stop the DMA channel. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 463: Advanced Data Transfer Controls: Auto-Alignment
If BCRn is less than 16 at the start of a transfer, the number of bytes remaining dictates transfer size. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 464: Termination
The processor can read DSRn to determine whether the transfer terminated successfully or with an error. DSRn[DONE] is then written with a 1 to clear the interrupt, DSRn[DONE], and error status bits. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 465 Functional Description MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 466: Multipurpose Clock Generator (Mcg)
• Option to program and maximize DCO output frequency for a low frequency external reference clock source. • Option to prevent FLL from resetting its current locked frequency when switching clock modes if FLL reference frequency is not changed. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 467 • Can be selected as the clock source for the MCU. • External clock from the Crystal Oscillator (OSC1) • Can be used as a source for the PLL only. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 468: Modes Of Operation
The MCG has the following modes of operation: FEI, FEE, FBI, FBE, PBE, PEE, BLPI, BLPE, and Stop. For details, see MCG modes of operation. 20.2 External Signal Description There are no MCG signals that connect off chip. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 469: Memory Map/Register Definition
20.3.14/351 4006_4013 MCG Test 3 Register (MCG_T3) 20.3.14/351 20.3.1 MCG Control 1 Register (MCG_C1) Address: 4006_4000h base + 0h offset = 4006_4000h Read CLKS FRDIV IREFS IRCLKEN IREFSTEN Write Reset MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 470 Internal reference clock is disabled in Stop mode. Internal reference clock is enabled in Stop mode if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 471: Mcg Control 2 Register (Mcg_C2)
BLPI mode. In any other MCG mode, LP bit has no affect. FLL or PLL is not disabled in bypass modes. FLL or PLL is disabled in bypass modes (lower power) Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 472: Mcg Control 3 Register (Mcg_C3)
1. A value for SCTRIM is loaded during reset from a factory programmed location. 20.3.4 MCG Control 4 Register (MCG_C4) Address: 4006_4000h base + 3h offset = 4006_4003h Read DMX32 DRST_DRS FCTRIM SCFTRIM Write Reset * Notes: • x = Undefined at reset. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 473 1. A value for FCTRIM is loaded during reset from a factory programmed location. 2. A value for SCFTRIM is loaded during reset from a factory programmed location. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 474: Mcg Control 5 Register (Mcg_C5)
Divide Factor Factor Factor Factor 00000 01000 10000 11000 00001 01001 10001 11001 Reserve 00010 01010 10010 11010 Reserve 00011 01011 10011 11011 Reserve Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 475: Mcg Control 6 Register (Mcg_C6)
(FEE, FBE, PEE, PBE, or BLPE) . Whenever the CME0 bit is set to a logic 1, the value of the RANGE0 bits in the C2 register should not be changed. CME0 bit should be set to a logic 0 before the MCG enters Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 476: Mcg Status Register (Mcg_S)
LOLS is set. This bit is cleared by reset or by writing a logic 1 to it when set. Writing a logic 0 to this bit has no effect. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 477 The IRCST bit will only be updated if the internal reference clock is enabled, either by the MCG being in a mode that uses the IRC or by setting the C1[IRCLKEN] bit . Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 478: Mcg Status And Control Register (Mcg_Sc)
FLL filter and FLL frequency will reset on changes to currect clock mode. Fll filter and FLL frequency retain their previous values during new clock mode change. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 479: Mcg Auto Trim Compare Value High Register (Mcg_Atcvh)
Values are used by Auto Trim Machine to compare and adjust Internal Reference trim values during ATM SAR conversion. 20.3.10 MCG Auto Trim Compare Value Low Register (MCG_ATCVL) Address: 4006_4000h base + Bh offset = 4006_400Bh Read ATCVL Write Reset MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 480: Mcg Control 7 Register (Mcg_C7)
Selects the MCG FLL external reference clock Selects Oscillator (OSCCLK). Selects 32 kHz RTC Oscillator. 20.3.12 MCG Control 8 Register (MCG_C8) Address: 4006_4000h base + Dh offset = 4006_400Dh Read LOLRE Write Reset MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 481: Mcg Control 10 Register (Mcg_C10)
This field is reserved. This read-only field is reserved and always has the value 0. 20.3.14 MCG Control 12 Register (MCG_C12) Address: 4006_4000h base + 11h offset = 4006_4011h Read Write Reset MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 482: Mcg Status 2 Register (Mcg_S2)
20.4.1 MCG mode state diagram The nine states of the MCG are shown in the following figure and are described in Table 20-3. The arrows indicate the permitted MCG mode transitions. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 483 2’b10. 20.4.1.1 MCG modes of operation The MCG operates in one of the following modes. Note The MCG restricts transitions between modes. For the permitted transitions, see Figure 20-2. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 484 • C1[FRDIV] must be written to divide external reference clock to be within the range of 31.25 kHz to 39.0625 kHz. • 0 is written to C6[PLLS]. • 0 is written to C2[LP]. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 485 In BLPE mode, MCGOUTCLK is derived from the OSCSEL external reference clock. The FLL is disabled and PLL is disabled even if the C5[PLLCLKEN] is set to 1. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 486 If C4[DRST_DRS] write bits are changed while in FLL engaged internal (FEI) or FLL engaged external (FEE) mode, the MCGOUTCLK switches to the new selected DCO range within three clocks of the selected DCO clock. After switching to the new DCO MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 487: Low-Power Bit Usage
MCGOUTCLK frequency if the MCG is in FEI mode. Additionally, this clock can be enabled in Stop mode by setting C1[IRCLKEN] and C1[IREFSTEN], otherwise this clock is disabled in Stop mode. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 488: Mcg Fixed Frequency Clock
MCG module. For more details, see the clock distribution chapter of this MCU. The MCGPLLCLK is prevented from coming out of the MCG until it is enabled and S[LOCK0] is set. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 489: Mcg Auto Trim (Atm)
Internal Reference Clock (IRC) frequency, and the frequency of the external reference clock using the following formula: ATCV • Fr = Target Internal Reference Clock (IRC) Trimmed Frequency • Fe = External Clock Frequency MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 490: Initialization / Application Information
• If entering FEE mode, set C1[FRDIV] appropriately, clear C1[IREFS] bit to switch to the external reference, and leave C1[CLKS] at 2'b00 so that the output of the FLL is selected as the system clock source. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 491 32.768 kHz reference is desired, set C4[DRST_DRS] bits to 2'b00 and set C4[DMX32] bit to 1. The resulting DCO output (MCGOUTCLK) frequency with the new multiplier of 732 will be 24 MHz. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 492: Using A 32.768 Khz Reference
In FEE and FBE modes, if using a 32.768 kHz external reference, at the default FLL multiplication factor of 640, the DCO output (MCGFLLCLK) frequency is 20.97 MHz at low-range. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 493: Mcg Mode Switching
31.25 kHz to 39.0625 kHz FBE (FLL bypassed external) OSCCLK OSCCLK / FLL_R must be in the range of 31.25 kHz to 39.0625 kHz Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 494 • C2[HGO0] set to 1 to configure the crystal oscillator for high gain operation. • C2[EREFS0] set to 1, because a crystal is being used. b. C1 = 0x90 • C1[CLKS] set to 2'b10 to select external reference clock as system clock source MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 495 PBE: Loop until S[PLLST] is set, indicating that the current source for the PLLS clock is the PLL. e. PBE: Then loop until S[LOCK0] is set, indicating that the PLL has acquired lock. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 496 Loop until S[CLKST] are 2'b11, indicating that the PLL output is selected to feed MCGOUTCLK in the current clock mode. • Now, with PRDIV of divide-by-2, and C6[VDIV] of multiply-by-24, MCGOUTCLK = [(4 MHz / 2) * 24] = 48 MHz. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 497 S[CLKST] = %11? ENTER BLPE MODE ? CONTINUE IN PEE MODE C2 = 0x1E (C2[LP] = 1) Figure 20-3. Flowchart of FEI to PEE mode transition using an 4 MHz crystal MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 498 PLLS clock is the FLL. 3. Next, FBE mode transitions into FBI mode: a. C1 = 0x54 • C1[CLKS] set to 2'b01 to switch the system clock to the internal reference clock. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 499 • C2[LP] is 1 • C2[RANGE0], C2[HGO0], C2[EREFS0], C1[IRCLKEN], and C1[IREFSTEN] bits are ignored when the C1[IREFS] bit is set. They can remain set, or be cleared at this point. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 500 BLPE MODE ? BLPE MODE ? (C2[LP]=1) CONTINUE IN BLPI MODE C2 = 0x1C (C2[LP] = 0) Figure 20-4. Flowchart of PEE to BLPI mode transition using an 4 MHz crystal MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 501 Initialization / Application information MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 502: Oscillator (Osc)
• Optionally external input bypass clock from EXTAL signal directly • One clock for MCU clock system • Two clocks for on-chip peripherals that can work in Stop modes Functional Description describes the module's operation in more detail. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 503: Block Diagram
) are required. The following table shows all possible connections. Table 21-2. External Caystal/Resonator Connections Oscillator Mode Connections Low-frequency (32 kHz), low-power Connection 1 Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 504 Crystal or Resonator Figure 21-3. Crystal/Ceramic Resonator Connections - Connection 2 NOTE Connection 1 and Connection 2 should use internal capacitors as the load of the oscillator by configuring the CR[SCxP] bits. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 505: External Clock Connections
XTAL EXTAL Clock Input Figure 21-5. External Clock Connections 21.7 Memory Map/Register Definitions Some oscillator module register bits are typically incorporated into other peripherals such as MCG or SIM. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 506: Osc Memory Map/Register Definition
External reference clock stays enabled in Stop mode if ERCLKEN is set before entering Stop mode. This field is reserved. Reserved This read-only field is reserved and always has the value 0. Oscillator 2 pF Capacitor Load Configure SC2P Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 507: Functional Description
Functional details of the module can be found here. 21.8.1 OSC module states The states of the OSC module are shown in the following figure. The states and their transitions between each other are described in this section. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 508 MCU, refer to the chip configuration details. The EXTAL and XTAL pins are also decoupled from all other oscillator circuitry in this state. The OSC module circuitry is configured to draw minimal current. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 509: Osc Module Modes
(MCG, Timer, and so on) is configured to use the oscillator output clock (OSC_CLK_OUT). Table 21-3. Oscillator modes Mode Frequency Range Low-frequency, high-gain (32.768 kHz) up to f (39.0625 kHz) osc_lo osc_lo Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 510 (not sensitive to the DC level of EXTAL). Also in this mode, all external components except for the resonator itself are integrated, which includes the load capacitors and feeback resistor that biases EXTAL. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 511: Counter
There is no reset state associated with the OSC module. The counter logic is reset when the OSC is not configured to generate clocks. There are no sources of reset requests for the OSC module. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 512: Low Power Modes Operation
OSC is still functional in these modes. After waking up from Very Low Leakage Stop (VLLSx) modes, all OSC register bits are reset and initialization is required through software. 21.11 Interrupts The OSC module does not generate any interrupts. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 513 Interrupts MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 514: Flash Memory Controller (Fmc)
• Interface between bus masters and the 32-bit program flash memory: • 8-bit, 16-bit, and 32-bit read operations to nonvolatile flash memory. • Acceleration of data transfer from the program flash memory to the device: MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 515: Modes Of Operation
(when enabled), the requested data is transferred within a single system clock. Upon system reset, the FMC is configured as follows: • Flash cache is enabled. • Instruction speculation and caching are enabled. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 516 When reconfiguring the FMC, do not program the control and configuration inputs to the FMC while the program flash memory is being accessed. Instead, change them with a routine executing from RAM in supervisor mode. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 517 Functional description MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 518: Flash Memory Module (Ftfa)
('1') states and/or programmed ('0') states. Therefore, it is recommended that each flash block or sector be re-erased immediately prior to factory programming to ensure that the full data retention capability is achieved. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 519: Features
• Supports MCU security mechanisms which prevent unauthorized access to the flash memory contents 23.1.2 Block Diagram The block diagram of the flash memory module is shown in the following figure. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 520: Glossary
The CPU or other bus masters initiate flash program and erase operations (or other flash commands) using writes to the FCCOB register group in the flash memory module. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 521: External Signal Description
This section describes the memory map and registers for the flash memory module. Data read from unimplemented memory space in the flash memory module is undefined. Writes to unimplemented or reserved memory space (registers) in the flash memory module are ignored. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 522: Program Flash Ifr Map
The program flash IFR is located within the program flash 0 memory block . Address Range Size (Bytes) Field Description 0x00 – 0xBF Reserved 0xC0 – 0xFF Program Once Field MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 523: Register Descriptions
Flash Common Command Object Registers 23.3.3.5/ 4002_0005 (FTFA_FCCOB2) Flash Common Command Object Registers 23.3.3.5/ 4002_0006 (FTFA_FCCOB1) Flash Common Command Object Registers 23.3.3.5/ 4002_0007 (FTFA_FCCOB0) Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 524 When set, the Access Error (ACCERR) and Flash Protection Violation (FPVIOL) bits in this register prevent the launch of any more commands until the flag is cleared (by writing a one to it). MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 525 As a status flag, this field cannot (and need not) be cleared by the user like the other error flags in this register. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 526 (no command is currently being executed). ERSAREQ is cleared by the flash memory module when the operation completes. No request or request complete Request to: 1. run the Erase All Blocks command, Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 527 Enables or disables backdoor key access to the flash memory module. Backdoor key access disabled Backdoor key access disabled (preferred KEYEN state to disable backdoor key access) Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 528 During the reset sequence, the register is loaded from the flash nonvolatile option byte in the Flash Configuration Field located in program flash memory. The flash basis for the values is signified by X in the reset value. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 529 This 8-bit value defines the command to be executed. The command code is followed by the parameters required for this specific flash command, typically an address and/or data values. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 530 KB of program flash memory or less, FPROT1 is not used. For configurations with 8 KB of program flash memory, FPROT2 is not used.For configurations with 24 KB of program flash memory or less, FPROT0 is not used. For configurations with 16 KB of MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 531 1 and protected regions use a 0, only writes changing 1s to 0s are accepted. This 1-to-0 transition check is performed on a bit-by-bit basis. Those FPROT bits with 1-to-0 transitions are accepted while all bits with 0-to-1 transitions are ignored. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 532: Functional Description
Protection is controlled by the following registers: • FPROTn — • For 2 program flash sizes, four registers typically protect 32 regions of the program flash memory as shown in the following figure MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 533: Interrupts
Interrupt Status Bit Enable Bit Flash Command Complete FSTAT[CCIF] FCNFG[CCIE] Flash Read Collision Error FSTAT[RDCOLERR] FCNFG[RDCOLLIE] Note Vector addresses and their relative interrupt priority are determined at the MCU level. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 534: Flash Operation In Low-Power Modes
Chip Configuration details of this device for how to activate each mode. 23.4.5 Flash Reads and Ignored Writes The flash memory module requires only the flash address to execute a flash memory read. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 535: Read While Write (Rww)
Flash commands are specified using a command write sequence illustrated in Figure 23-3. The flash memory module performs various checks on the command (FCCOB) content and continues with command execution if all requirements are fulfilled. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 536 Program and erase commands also check the address to determine if the operation is requested to execute on protected areas. If the protection check fails, FSTAT[FPVIOL] (protection error) flag is set. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 537 FCCOB and FSTAT registers. 4. The flash memory module sets FSTAT[CCIF] signifying that the command has completed. The flow for a generic command write sequence is illustrated in the following figure. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 538 Command Program flash Function 0x01 Read 1s Section × Verify that a given number of program flash locations from a starting address are erased. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 539 × — — 0x09 Erase Flash Sector × × × × — — 0x40 Read 1s All Blocks × × × × × — Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 540: Margin Read Commands
(or very soon) after completion of an erase or program command, early in the cycling life. 'Factory' margin levels can be used to check MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 541: Flash Command Description
The Read 1s Section command checks if a section of program flash memory is erased to the specified read margin level. The Read 1s Section command defines the starting address and the number of longwords to be verified. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 542 FSTAT[ACCERR] Read-1s fails. FSTAT[MGSTAT0] 23.4.10.2 Program Check Command The Program Check command tests a previously programmed program flash longword to see if it reads correctly at the specified margin level. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 543 Table 23-8. Program Check Command Error Handling Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] An invalid flash address is supplied FSTAT[ACCERR] Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 544 Description Resource Size Local Address Range Select Code 0x00 Program Flash 0 IFR 256 Bytes 0x00_0000–0x00_00FF 0x01 Version ID 8 Bytes 0x00_0000–0x00_0007 1. Located in program flash 0 reserved space. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 545 Flash address [15:8] Flash address [7:0] Byte 0 program value Byte 1 program value Byte 2 program value Byte 3 program value 1. Must be longword aligned (Flash address [1:0] = 00). MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 546 After clearing CCIF to launch the Erase Flash Sector command, the flash memory module erases the selected program flash sector and then verifies that it is erased. The Erase Flash Sector command aborts if the selected sector is protected (see the description MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 547 There is a minimum elapsed time limit of 4.3 msec between the request to resume the Erase Flash Sector operation (CCIF is cleared) and the request to suspend the operation again (ERSSUSP is set). This minimum time period is required to ensure that the Erase MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 548 Data in this sector is not reliable until a new erase command fully completes. The following figure shows how to suspend and resume the Erase Flash Sector operation. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 549 ERSSCR Suspended Resume Erase? ERSSUSP: Bit in FCNFG register No, Abort SUSPACK: Internal Suspend Acknowledge Clear ERSSUSP User Cmd Interrupt/Suspend Figure 23-4. Suspend and Resume of Erase Flash Sector Operation MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 550 Table 23-18. Read 1s All Blocks Command Error Handling Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] An invalid margin choice is specified FSTAT[ACCERR] Read-1s fails FSTAT[MGSTAT0] MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 551 These records can be read using the Read Once command (see Read Once Command) or using the Read Resource command (see Read Resource Command). These records can be programmed only once since the program flash 0 IFR cannot be erased. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 552 The Erase All Blocks operation erases all flash memory, verifies all memory contents, and releases MCU security. Table 23-23. Erase All Blocks Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0x44 (ERSALL) MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 553 Backdoor Access Key command is further qualified by the FSEC[KEYEN] bits. The Verify Backdoor Access Key command releases security if user-supplied keys in the FCCOB match those stored in the Backdoor Comparison Key bytes of the Flash MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 554 Backdoor key access has not been enabled (see the description of the FSEC register) FSTAT[ACCERR] This command is launched and the backdoor key has mismatched since the last power down FSTAT[ACCERR] reset MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 555: Security
Table 23-28. Flash Memory Access Summary Chip Security State Operating Mode Unsecure Secure NVM Normal Full command set Only the Erase All Blocks and Read 1s All NVM Special Full command set Blocks commands. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 556 FSEC register only. It does not alter the security byte or the keys stored in the Flash Configuration Field (Flash Configuration Field Description). After the next reset of the chip, the security state of the flash memory MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 557: Reset Sequence
If a reset occurs while any flash command is in progress, that command is immediately aborted. The state of the word being programmed or the sector/block being erased is not guaranteed. Commands and operations do not automatically resume after exiting reset. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 558: Analog-To-Digital Converter (Adc)
Following are the features of the ADC module. • Linear successive approximation algorithm with up to 16-bit resolution • Up to four pairs of differential and 24 single-ended external analog inputs MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 559: Block Diagram
• Temperature sensor • Hardware average function • Selectable voltage reference: external or alternate • Self-Calibration mode 24.2.2 Block diagram The following figure is the ADC module block diagram. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 560: Adc Signal Descriptions
The ADC module supports up to 4 pairs of differential inputs and up to 24 single-ended inputs. Each differential pair requires two inputs, DADPx and DADMx. The ADC also requires four supply/reference/ground connections. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 561: Analog Power (Vdda)
. The two pairs are external (V and V ) and alternate (V and V REFH REFL ALTH ALTL These voltage references are selected using SC2[REFSEL]. The alternate V ALTH MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 562: Analog Channel Inputs (Adx)
4003_B008 ADC Configuration Register 1 (ADC0_CFG1) 0000_0000h 24.4.2/436 4003_B00C ADC Configuration Register 2 (ADC0_CFG2) 0000_0000h 24.4.3/437 4003_B010 ADC Data Result Register (ADC0_RA) 0000_0000h 24.4.4/438 Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 563: Adc Status And Control Registers 1 (Adcx_Sc1N)
ADC Minus-Side General Calibration Value Register 4003_B06C 0000_0020h 24.4.24/453 (ADC0_CLM0) 24.4.1 ADC Status and Control Registers 1 (ADCx_SC1n) SC1A is used for both software and hardware trigger modes of operation. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 564 SC1B–SC1n registers do not initiate a new conversion. Address: 4003_B000h base + 0h offset + (4d × i), where i=0d to 1d Reset AIEN DIFF ADCH Reset MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 565 When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved. 00111 When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 566 Voltage reference selected is determined by SC2[REFSEL]. 11110 When DIFF=0,V is selected as input; when DIFF=1, it is reserved. Voltage reference REFSL selected is determined by SC2[REFSEL]. 11111 Module is disabled. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 567: Adc Configuration Register 1 (Adcx_Cfg1)
When ADLSMP=1, the long sample time select bits, (ADLSTS[1:0]), can select the extent of the long sample time. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 568: Adc Configuration Register 2 (Adcx_Cfg2)
Configuration Register 2 (CFG2) selects the special high-speed configuration for very high speed conversions and selects the long sample time duration during long sample mode. Address: 4003_B000h base + Ch offset = 4003_B00Ch Reset ADLSTS Reset MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 569: Adc Data Result Register (Adcx_Rn)
The data result registers (Rn) contain the result of an ADC conversion of the channel selected by the corresponding status and channel control register (SC1A:SC1n). For every status and channel control register, there is a corresponding data result register. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 570 Address: 4003_B000h base + 10h offset + (4d × i), where i=0d to 1d Reset ADCx_Rn field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Data result MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 571: Compare Value Registers (Adcx_Cvn)
Address: 4003_B000h base + 18h offset + (4d × i), where i=0d to 1d Reset ADCx_CVn field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Compare Value. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 572: Status And Control Register 2 (Adcx_Sc2)
Conversion not in progress. Conversion in progress. Conversion Trigger Select ADTRG Selects the type of trigger used for initiating a conversion. Two types of trigger are selectable: Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 573 . This pair may be additional external pins or ALTH ALTL internal sources depending on the MCU configuration. See the chip configuration information for details specific to this MCU Reserved Reserved MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 574: Status And Control Register 3 (Adcx_Sc3)
ADC register is written, or any stop mode is entered before the calibration sequence completes. Writing 1 to CALF clears it. Calibration completed normally. Calibration failed. ADC accuracy specifications are not guaranteed. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 575: Adc Offset Correction Register (Adcx_Ofs)
For more information regarding the calibration procedure, please refer to the Calibration function section. Address: 4003_B000h base + 28h offset = 4003_B028h Reset MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 576: Adc Plus-Side Gain Register (Adcx_Pg)
MG[15] and MG[14]. This register must be written by the user with the value described in the calibration procedure. Otherwise, the gain error specifications may not be met. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 577: Adc Plus-Side General Calibration Value Register (Adcx_Clpd)
Address: 4003_B000h base + 34h offset = 4003_B034h CLPD Reset ADCx_CLPD field descriptions Field Description 31–6 This field is reserved. Reserved This read-only field is reserved and always has the value 0. CLPD Calibration Value Calibration Value MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 578: Adc Plus-Side General Calibration Value Register (Adcx_Clps)
Address: 4003_B000h base + 3Ch offset = 4003_B03Ch CLP4 Reset ADCx_CLP4 field descriptions Field Description 31–10 This field is reserved. Reserved This read-only field is reserved and always has the value 0. CLP4 Calibration Value Calibration Value MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 579: Adc Plus-Side General Calibration Value Register (Adcx_Clp3)
Address: 4003_B000h base + 44h offset = 4003_B044h CLP2 Reset ADCx_CLP2 field descriptions Field Description 31–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. CLP2 Calibration Value Calibration Value MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 580: Adc Plus-Side General Calibration Value Register (Adcx_Clp1)
Address: 4003_B000h base + 4Ch offset = 4003_B04Ch CLP0 Reset ADCx_CLP0 field descriptions Field Description 31–6 This field is reserved. Reserved This read-only field is reserved and always has the value 0. CLP0 Calibration Value Calibration Value MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 581: Adc Minus-Side General Calibration Value Register (Adcx_Clmd)
CLMD Calibration Value Calibration Value 24.4.19 ADC Minus-Side General Calibration Value Register (ADCx_CLMS) For more information, see CLMD register description. Address: 4003_B000h base + 58h offset = 4003_B058h CLMS Reset MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 582: Adc Minus-Side General Calibration Value Register (Adcx_Clm4)
CLM3 Reset ADCx_CLM3 field descriptions Field Description 31–9 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 583: Adc Minus-Side General Calibration Value Register (Adcx_Clm2)
Address: 4003_B000h base + 68h offset = 4003_B068h CLM1 Reset ADCx_CLM1 field descriptions Field Description 31–7 This field is reserved. Reserved This read-only field is reserved and always has the value 0. CLM1 Calibration Value Calibration Value MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 584: Adc Minus-Side General Calibration Value Register (Adcx_Clm0)
The ADC module has the capability of automatically comparing the result of a conversion with the contents of the CV1 and CV2 registers. The compare function is enabled by setting SC2[ACFE] and operates in any of the conversion modes and configurations. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 585: Clock Select And Divide Control
If the available clocks are too fast, the clock must be divided to the appropriate frequency. This divider is specified by CFG1[ADIV] and can be divide-by 1, 2, 4, or 8. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 586: Voltage Reference Selection
ADHWT signal to trigger a new conversion. The channel and status fields selected for the conversion depend on the active trigger select signal: • ADHWTSA active selects SC1A. • ADHWTSn active selects SC1n. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 587: Conversion Control
SC2[ADTRG]=1, and a hardware trigger select event, ADHWTSn, has occurred. The channel and status fields selected depend on the active trigger select signal: • ADHWTSA active selects SC1A. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 588 SC1n[COCO] sets only if the last of the selected number of conversions is completed and the compare condition is true. An interrupt is generated if the respective SC1n[AIEN] is high at the time that the respective SC1n[COCO] is set. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 589 CFG2[ADACKEN]=1, it remains active regardless of the state of the ADC or the MCU power mode. Power consumption when the ADC is active can be reduced by setting CFG1[ADLPC]. This results in a lower maximum value for f ADCK MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 590 3. The result of the conversion is transferred to Rn upon completion of the conversion algorithm. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 591 9b differential 27 ADCK cycles 10b single-ended 20 ADCK cycles 11b differential 30 ADCK cycles 12b single-ended 20 ADCK cycles 13b differential 30 ADCK cycles Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 592 • 10-bit mode, with the bus clock selected as the input clock source • The input clock divide-by-1 ratio selected • Bus frequency of 8 MHz • Long sample time disabled • High-speed conversion disabled MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 593 Equation 1 on page 460. Table 24-9. Typical conversion time Variable Time SFCAdder 3 ADCK cycles + 5 bus clock cycles AverageNum 34 ADCK cycles LSTAdder 20 ADCK cycles HSCAdder MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 594 When hardware averaging is selected, the completion of a single conversion will not set SC1n[COCO]. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 595: Automatic Compare Function
CV2. Greater than Outside range, inclusive Compare true if the result is greater than or equal to CV1 Or the result is less than or equal to CV2. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 596: Calibration Function
Prior to calibration, the user must configure the ADC's clock source and frequency, low power configuration, voltage reference selection, sample time, and high speed configuration according to the application's clock source availability and needs. If the MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 597 7. Repeat the procedure for the minus-side gain calibration value. When calibration is complete, the user may reconfigure and use the ADC as desired. A second calibration may also be performed, if desired, by clearing and again setting SC3[CAL]. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 598: User-Defined Offset Function
ADC error specifications may not be met. Storing the value generated by the calibration function in memory before overwriting with a user- specified value is recommended. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 599: Temperature Sensor
• m is referred as temperature sensor slope in the device data sheet. It is the hot or cold voltage versus temperature slope in V/°C. For temperature calculations, use the V and temperature sensor slope values from TEMP25 the ADC Electricals table. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 600: Mcu Wait Mode Operation
24.5.10 MCU Normal Stop mode operation Stop mode is a low-power consumption Standby mode during which most or all clock sources on the MCU are disabled. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 601: Mcu Low-Power Stop Mode Operation
Therefore, the module must be re-enabled and re-configured following exit from Low-Power Stop mode. NOTE For the chip specific modes of operation, see the power management information for the device. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 602: Initialization Information
5. Update SC1:SC1n registers to select whether conversions will be single-ended or differential and to enable or disable conversion complete interrupts. Also, select the input channel which can be used to perform conversions. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 603 Bit 5 DIFF 0 Single-ended conversion selected. Bit 4:0 ADCH 00001 Input channel 1 selected as ADC input channel. RA = 0xxx Holds results of conversion. CV = 0xxx Holds compare value when compare function enabled. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 604: Application Information
24.7.1 External pins and routing 24.7.1.1 Analog supply pins Depending on the device, the analog power and ground supplies, V and V , of the ADC module are available as: MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 605 V and V loop. The REFH REFL best external component to meet this current demand is a 0.1 μF capacitor with good MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 606: Sources Of Error
RAS + RADIN =SC / (FMAX * NUMTAU * CADIN) Figure 24-3. Sampling equation Where: RAS = External analog source resistance SC = Number of ADCK cycles used during sample window MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 607 REFL plane. • Operate the MCU in Wait or Normal Stop mode before initiating (hardware-triggered conversions) or immediately after initiating (hardware- or software-triggered conversions) the ADC conversion. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 608 12-bit modes. As a consequence, however, the code width of the first (0x000) conversion is only 1/2 LSB and the code width of the last (0xFF or 0x3FF) is 1.5 LSB. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 609 However, even small amounts of system noise can cause the converter to be indeterminate, between two codes, for a range of input voltages around the transition voltage. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 610 • Missing codes: Missing codes are those values never converted for any input value. In 8-bit or 10-bit mode, the ADC is guaranteed to be monotonic and have no missing codes. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 611 Application information MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 612: Comparator (Cmp)
25.1.1 CMP features The CMP has the following features: • Operational over the entire supply range • Inputs may range from rail to rail • Programmable hysteresis control MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 613: 6-Bit Dac Key Features
• Power Down mode to conserve power when not in use • Option to route the output to internal comparator input 25.1.3 ANMUX key features The ANMUX has the following features: MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 614: Cmp, Dac And Anmux Diagram
• Two 8-to-1 channel mux • Operational over the entire supply range 25.1.4 CMP, DAC and ANMUX diagram The following figure shows the block diagram for the High-Speed Comparator, DAC, and ANMUX modules. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 615: Cmp Block Diagram
Window ANMUX and filter control CMPO MSEL[2:0] Figure 25-1. CMP, DAC and ANMUX block diagram 25.1.5 CMP block diagram The following figure shows the block diagram for the CMP module. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 616: Memory Map/Register Definitions
• If enabled, the Filter block will incur up to one bus clock additional latency penalty on COUT due to the fact that COUT, which is crossing clock domain boundaries, must be resynchronized to the bus clock. 25.2 Memory map/register definitions MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 617: Cmp Control Register 0 (Cmpx_Cr0)
Defines the programmable hysteresis level. The hysteresis values associated with each level are device- specific. See the Data Sheet of the device for the exact values. Level 0 Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 618: Cmp Control Register 1 (Cmpx_Cr1)
Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption. High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 619: Cmp Filter Period Register (Cmpx_Fpr)
Specifies the sampling period, in bus clock cycles, of the comparator output filter, when CR1[SE]=0. Setting FILT_PER to 0x0 disables the filter. Filter programming and latency details appear in the Functional description. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 620: Cmp Status And Control Register (Cmpx_Scr)
Detects a falling-edge on COUT, when set, during normal operation. CFF is cleared by writing 1 to it. During Stop modes, CFF is level sensitive . Falling-edge on COUT has not been detected. Falling-edge on COUT has occurred. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 621: Dac Control Register (Cmpx_Daccr)
Address: 4007_3000h base + 5h offset = 4007_3005h Read PSTM PSEL MSEL Write Reset CMPx_MUXCR field descriptions Field Description Pass Through Mode Enable PSTM Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 622: Functional Description
CMPO is high when the non-inverting input is greater than the inverting input, and is low when the non-inverting input is less than the inverting input. This signal can be selectively inverted by setting CR1[INV] = 1. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 623: Cmp Functional Modes
For cases where a comparator is used to drive a fault input, for example, for a , it must be configured to operate in Continuous mode so that an external fault can immediately pass through the comparator to the target fault circuitry. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 624 Clock COUTA CMPO to prescaler divided FILT_PER CGMUX clock Figure 25-3. Comparator operation in Continuous mode NOTE See the chip configuration section for the source of sample/ window input. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 625 CMPO COUT To other SOC functions WINDOW/SAMPLE bus clock Clock COUTA CMPO to divided bus clock prescaler FILT_PER CGMUX SE=0 Figure 25-4. Sampled, Non-Filtered (# 3B): sampling interval internally derived MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 626: Power Modes
Filtered (# 4B) is that now, CR0[FILTER_CNT]>1, which activates filter operation. 25.3.2 Power modes 25.3.2.1 Wait mode operation During Wait and VLPW modes, the CMP, if enabled, continues to operate normally and a CMP interrupt can wake the MCU. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 627: Startup And Operation
A typical startup sequence is listed here. • The time required to stabilize COUT will be the power-on delay of the comparators plus the largest propagation delay from a selected analog source through the analog MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 628: Low-Pass Filter
CR0[FILTER_CNT] samples agree that the output value has changed. In other words, SCR[COUT] will be 0 for some initial period, even when COUTA is at logic 1. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 629 + (CR0[FILTER_CNT] * FPR[FILT_PER] x T ) + T 1. T represents the intrinsic delay of the analog component plus the polarity select logic. T is the period of the bus clock. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 630: Cmp Interrupts
STOP modes. Refer to DMA chapters in the device reference manual for the asynchronous DMA function for details. 25.6 CMP Asynchronous DMA support The comparator can remain functional in STOP modes. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 631: Digital-To-Analog Converter
When in Disabled mode, DACO is connected to the analog ground. DACEN VOSEL[5:0] VRSEL DACO Figure 25-6. 6-bit DAC block diagram 25.8 DAC functional description This section provides DAC functional description information. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 632: Dac Resets
Upon setting TRIGM, the CMP and DAC are placed in a standby state until an external timer resource trigger is received. See the chip configuration chapter for details about the external timer resource. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 633 CMP Trigger Mode MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 634: 12-Bit Digital-To-Analog Converter (Dac)
• Static operation in Normal Stop mode • 2-word data buffer supported with multiple operation modes • DMA support 26.3 Block diagram The block diagram of the DAC module is as follows: MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 635: Memory Map/Register Definition
& DACBBIEN DACBFMD DACTRGSE Figure 26-1. DAC block diagram 26.4 Memory map/register definition The DAC has registers to control analog comparator and programmable voltage divider to perform the digital-to-analog functions. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 636: Dac Data Low Register (Dacx_Datnl)
DACx_DATnH field descriptions Field Description 7–4 This field is reserved. Reserved This read-only field is reserved and always has the value 0. DATA1 DATA1 Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 637: Dac Status Register (Dacx_Sr)
The DAC buffer read pointer is zero. DAC Buffer Read Pointer Bottom Position Flag DACBFRPBF The DAC buffer read pointer is not equal to C2[DACBFUP]. The DAC buffer read pointer is equal to C2[DACBFUP]. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 638: Dac Control Register (Dacx_C0)
This field is reserved. Reserved This read-only field is reserved and always has the value 0. DAC Buffer Read Pointer Top Flag Interrupt Enable DACBTIEN Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 639: Dac Control Register 1 (Dacx_C1)
Buffer read pointer is disabled. The converted data is always the first word of the buffer. Buffer read pointer is enabled. The converted data is the word that the read pointer points to. It means converted data can be from any word of the buffer. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 640: Dac Control Register 2 (Dacx_C2)
When both the DAC and the buffer are enabled, the DAC converts the data in the data buffer to analog output voltage. The data buffer read pointer advances to the next word whenever a hardware or software trigger event occurs. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 641: Dma Operation
When DMA is enabled, DMA requests are generated instead of interrupt requests. The DMA Done signal clears the DMA request. The status register flags are still set and are cleared automatically when the DMA completes. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 642: Resets
In low-power stop modes, the DAC is fully shut down. NOTE The assignment of module modes to core modes is chip- specific. For module-to-core mode assignments, see the chapter that describes how modules are configured. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 643 Functional description MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 644: Timer/Pwm Module (Tpm)
• Can increment on every edge of the asynchronous counter clock • Can increment on rising edge of an external clock input synchronized to the asynchronous counter clock • Prescaler divide-by 1, 2, 4, 8, 16, 32, 64, or 128 MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 645: Modes Of Operation
During stop mode, the TPM counter clock can remain functional and the TPM can generate an asynchronous interrupt to exit the MCU from stop mode. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 646: Block Diagram
Description TPM_EXTCLK External clock. TPM external clock can be selected to increment the TPM counter on every rising edge synchronized to the counter clock. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 647: Tpm_Extclk - Tpm External Clock
Channel (n) Status and Control (TPM0_C1SC) 0000_0000h 27.3.4/521 4003_8018 Channel (n) Value (TPM0_C1V) 0000_0000h 27.3.5/523 4003_801C Channel (n) Status and Control (TPM0_C2SC) 0000_0000h 27.3.4/521 Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 648 Channel (n) Status and Control (TPM2_C3SC) 0000_0000h 27.3.4/521 4003_A028 Channel (n) Value (TPM2_C3V) 0000_0000h 27.3.5/523 4003_A02C Channel (n) Status and Control (TPM2_C4SC) 0000_0000h 27.3.4/521 Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 649: Status And Control (Tpmx_Sc)
TPMx_SC field descriptions Field Description 31–9 This field is reserved. Reserved This read-only field is reserved and always has the value 0. DMA Enable Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 650 This field is write protected. It can be written only when the counter is disabled. Divide by 1 Divide by 2 Divide by 4 Divide by 8 Divide by 16 Divide by 32 Divide by 64 Divide by 128 MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 651: Counter (Tpmx_Cnt)
It is recommended to initialize the TPM counter (write to CNT) before writing to the MOD register to avoid confusion about when the first counter overflow will occur. Address: Base address + 8h offset Reset MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 652: Channel (N) Status And Control (Tpmx_Cnsc)
Output compare Pulse Output low on match Pulse Output high on match Center-aligned PWM High-true pulses (clear Output on match-up, set Output on match- down) Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 653 Used for further selections in the channel logic. Its functionality is dependent on the channel mode. When a channel is disabled, this field will not change state until acknowledged in the TPM counter clock domain. Edge or Level Select ELSB Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 654: Channel (N) Value (Tpmx_Cnv)
This read-only field is reserved and always has the value 0. Channel Value Captured TPM counter value of the input modes or the match value for the output modes. This field must be written with single 16-bit or 32-bit access. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 655: Capture And Compare Status (Tpmx_Status)
Description 31–9 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Timer Overflow Flag See register description Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 656 See the register description. No channel event has occurred. A channel event has occurred. Channel 0 Flag CH0F See the register description. No channel event has occurred. A channel event has occurred. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 657: Configuration (Tpmx_Conf)
CSOT set. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 658: Functional Description
Reserved This field is reserved. This read-only field is reserved and always has the value 0. 27.4 Functional description The following sections describe the TPM features. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 659: Clock Domains
Therefore, to meet Nyquist criteria considering also jitter, the frequency of the external clock source must be less than half of the counter clock frequency. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 660: Prescaler
The TPM period when using up counting is (MOD + 0x0001) × period of the TPM counter clock. The TOF bit is set when the TPM counter changes from MOD to zero. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 661 The TPM period when using up-down counting is 2 × MOD × period of the TPM counter clock. The TOF bit is set when the TPM counter changes from MOD to (MOD – 1). MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 662 • When (CROT= 1), the counter will reset to zero as if an overflow occurred whenever a rising edge is detected on the trigger input. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 663: Input Capture Mode
The CHnF bit is set on the third rising edge of the counter clock after a valid edge occurs on the channel input. 27.4.5 Output Compare Mode The output compare mode is selected when (CPWMS = 0), and (MSnB:MSnA = X:1). MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 664 (n) output previous value CHnF bit previous value TOF bit Figure 27-7. Example of the output compare mode when the match clears the channel output MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 665: Edge-Aligned Pwm (Epwm) Mode
If (ELSnB:ELSnA = 0:0) when the counter reaches the value in the CnV register, the CHnF bit is set and the channel (n) interrupt is generated (if CHnIE = 1), however the channel (n) output is not controlled by TPM. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 666: Center-Aligned Pwm (Cpwm) Mode
0x0001 to 0x7FFF because values outside this range can produce ambiguous results. In the CPWM mode, the TPM counter counts up until it reaches MOD and then counts down until it reaches zero. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 667 If (ELSnB:ELSnA = X:1), then the channel (n) output is forced low at the channel (n) match (TPM counter = CnV) when counting down, and it is forced high at the channel (n) match when counting up (see the following figure). MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 668: Registers Updated From Write Buffers
27.4.8.2 CnV Register Update If (CMOD[1:0] = 0:0) then CnV register is updated when CnV register is written. If (CMOD[1:0] ≠ 0:0), then CnV register is updated according to the selected mode, that MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 669: Dma
CHnF/TOF bit is cleared either when the DMA transfer is done or by writing a 1 to CHnF/TOF bit. 27.4.10 Output triggers The TPM generates output triggers for the counter and each channel that can be used to trigger events in other peripherals. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 670: Reset Overview
The timer overflow interrupt is generated when (TOIE = 1) and (TOF = 1). 27.4.12.2 Channel (n) Interrupt The channel (n) interrupt is generated when (CHnIE = 1) and (CHnF = 1). MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 671 Functional description MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 672: Periodic Interrupt Timer (Pit)
The PIT module is an array of timers that can be used to raise interrupts and trigger DMA channels. 28.1.1 Block diagram The following figure shows the block diagram of the PIT module. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 673: Features
• Ability of timers to generate DMA trigger pulses • Ability of timers to generate interrupts • Maskable interrupts • Independent timeout periods for each timer 28.2 Signal description The PIT module has no external pins. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 674: Memory Map/Register Description
This register enables or disables the PIT timer clocks and controls the timers when the PIT enters the Debug mode. Access: User read/write Address: 4003_7000h base + 0h offset = 4003_7000h Reset MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 675: Pit Upper Lifetime Timer Register (Pit_Ltmr64H)
This register is intended for applications that chain timer 0 and timer 1 to build a 64-bit lifetimer. Access: User read only Address: 4003_7000h base + E0h offset = 4003_70E0h Reset MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 676: Pit Lower Lifetime Timer Register (Pit_Ltmr64L)
28.3.4 Timer Load Value Register (PIT_LDVALn) These registers select the timeout period for the timer interrupts. Access: User read/write Address: 4003_7000h base + 100h offset + (16d × i), where i=0d to 1d Reset MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 677: Current Timer Value Register (Pit_Cvaln)
28.3.6 Timer Control Register (PIT_TCTRLn) These registers contain the control bits for each timer. Access: User read/write Address: 4003_7000h base + 108h offset + (16d × i), where i=0d to 1d Reset Reset MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 678: Timer Flag Register (Pit_Tflgn)
Reset Reset PIT_TFLGn field descriptions Field Description 31–1 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 679: Functional Description
If desired, the current counter value of the timer can be read via the CVAL registers. The counter period can be restarted, by first disabling, and then enabling the timer with TCTRLn[TEN]. See the following figure. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 680 In Debug mode, the timers will be frozen based on MCR[FRZ]. This is intended to aid software development, allowing the developer to halt the processor, investigate the current state of the system, for example, the timer values, and then continue the operation. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 681: Interrupts
Timer 3 shall be used only for triggering. Therefore, Timer 3 is started by writing a 1 to TCTRL3[TEN]. TCTRL3[TIE] stays at 0. The following example code matches the described setup: MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 682: Example Configuration For Chained Timers
PIT_LDVAL2 = 0x00000009; // setup Timer 2 for 10 counts PIT_TCTRL2 = TIE; // enable Timer 2 interrupt PIT_TCTRL2 |= CHN; // chain Timer 2 to Timer 1 PIT_TCTRL2 |= TEN; // start Timer 2 MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 683: Example Configuration For The Lifetime Timer
PIT_LDVAL0 = 0xFFFFFFFF; // setup timer 0 for maximum counting period PIT_TCTRL0 = TEN; // start timer 0 To access the lifetime, read first LTMR64H and then LTMR64L. current_uptime = PIT_LTMR64H<<32; current_uptime = current_uptime + PIT_LTMR64L; MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 684: Low-Power Timer (Lptmr)
• Configurable clock source for prescaler/glitch filter • Configurable input source for pulse counter • Rising-edge or falling-edge 29.1.2 Modes of operation The following table describes the operation of the LPTMR module in various modes. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 685: Lptmr Signal Descriptions
CNR to increment. Timing Assertion or deassertion may occur at any time; input may assert asynchronously to the bus clock. 29.3 Memory map and register definition MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 686: Low Power Timer Control Status Register (Lptmrx_Csr)
LPTMR is disabled. The input connections vary by device. See the chip configuration details for information on the connections to these inputs. Pulse counter input 0 is selected. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 687: Low Power Timer Prescale Register (Lptmrx_Psr)
LPTMR is disabled and internal logic is reset. LPTMR is enabled. 29.3.2 Low Power Timer Prescale Register (LPTMRx_PSR) Address: 4004_0000h base + 4h offset = 4004_0004h Reset PRESCALE PBYP Reset MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 688 Selects the clock to be used by the LPTMR prescaler/glitch filter. PCS must be altered only when the LPTMR is disabled. The clock connections vary by device. NOTE: See the chip configuration details for information on the connections to these inputs. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 689: Low Power Timer Compare Register (Lptmrx_Cmr)
COUNTER Reset LPTMRx_CNR field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 690: Functional Description
NOTE The clock source or pulse input source selected for the LPTMR should not exceed the frequency f defined in the device LPTMR datasheet. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 691 The selected input source remains asserted for at least 2 The glitch filter output will also assert. consecutive prescaler clock rising-edges NOTE The input is only sampled on the rising clock edge. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 692: Lptmr Compare
The CNR continues incrementing when the core is halted in Debug mode when configured for Pulse Counter mode, the CNR will stop incrementing when the core is halted in Debug mode when configured for Time Counter mode. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 693: Lptmr Hardware Trigger
The LPTMR interrupt is generated asynchronously to the system clock and can be used to generate a wakeup from any low-power mode, including the low-leakage modes, provided the LPTMR is enabled as a wakeup source. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 694: Real Time Clock (Rtc)
• 1 Hz square wave output with optional interrupt 30.1.2 Modes of operation The RTC remains functional in all low power modes and can generate an interrupt to exit any low power mode. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 695: Rtc Signal Descriptions
30.2.4/566 4003_D010 RTC Control Register (RTC_CR) 0000_0000h 30.2.5/567 4003_D014 RTC Status Register (RTC_SR) 0000_0001h 30.2.6/569 4003_D018 RTC Lock Register (RTC_LR) 0000_00FFh 30.2.7/570 4003_D01C RTC Interrupt Enable Register (RTC_IER) 0000_0007h 30.2.8/571 MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 696: Rtc Time Seconds Register (Rtc_Tsr)
SR[TOF] or SR[TIF] are set. When the time counter is disabled, the TPR can be read or written. The TSR[TSR] increments when bit 14 of the TPR transitions from a logic one to a logic zero. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 697: Rtc Time Alarm Register (Rtc_Tar)
Configures the number of 32.768 kHz clock cycles in each second. This register is double buffered and writes do not take affect until the end of the current compensation interval. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 698: Rtc Control Register (Rtc_Cr)
WPE SWR Reset RTC_CR field descriptions Field Description 31–24 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 699 Registers can be written when locked under limited conditions. Supervisor Access Non-supervisor mode write accesses are not supported and generate a bus error. Non-supervisor mode write accesses are supported. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 700: Rtc Status Register (Rtc_Sr)
Time alarm flag is set when the TAR[TAR] equals the TSR[TSR] and the TSR[TSR] increments. This bit is cleared by writing the TAR register. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 701: Rtc Lock Register (Rtc_Lr)
Lock Register is not locked and writes complete as normal. Status Register Lock After being cleared, this bit can be set only by POR or software reset. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 702: Rtc Interrupt Enable Register (Rtc_Ier)
The wakeup pin is optional and not available on all devices. Whenever the wakeup pin is enabled and this bit is set, the wakeup pin will assert. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 703: Functional Description
The time counter within the RTC is clocked by a 32.768 kHz clock sourced from an external crystal using the oscillator. The power-on-reset signal initializes all RTC registers to their default state. A software reset bit can also initialize all RTC registers. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 704: Time Counter
SR[TOF] is clear, and the 32.768 kHz clock source is present. After enabling the oscillator, wait the oscillator startup time before setting SR[TCE] to allow time for the oscillator clock output to stabilize. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 705: Compensation
When the compensation interval is set to other than once a second then the compensation is applied in the first second interval and the remaining second intervals receive no compensation. Compensation is disabled by configuring the time compensation register to zero. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 706: Time Alarm
RTC clock gate control bit. The RTC interrupt can be used to wakeup the chip from any low-power mode. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 707 RTC clock gate control bit. This interrupt is optional and may not be implemented on all devices. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 708: Serial Peripheral Interface (Spi)
DMA controller instead of through the CPU. This feature decreases CPU loading, allowing CPU time to be used for other work. 31.1.1 Features The SPI includes these distinctive features: • Master mode or slave mode operation MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 709: Modes Of Operation
Run mode. If the SPI is configured as a slave, reception and transmission of a byte continues, so that the slave stays synchronized to the master. • Stop mode MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 710: Block Diagrams
The slave device must be selected by a low level on the slave select input (SS pin). In this system, the master device has configured its SS pin as an optional slave select output. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 711 In the external SPI system, simply connect all SPSCK pins to each other, all MISO pins together, and all MOSI pins together. Peripheral devices often use slightly different names for these pins. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 712: External Signal Description
SPI control bits. When the SPI is disabled (SPE = 0), these four pins revert to other functions that are not controlled by the SPI (based on chip configuration). MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 713: Spsck - Spi Serial Clock
SPI is enabled as a master and MODFEN is 1, the slave select output enable bit determines whether this pin acts as the mode fault input (SSOE is 0) or as the slave select output (SSOE is 1). MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 714: Memory Map/Register Definition
When the FIFO is supported and enabled (FIFOMODE is 1): This register has four flags that provide mechanisms to support an 8-byte FIFO mode: RNFULLF, TNEARF, TXFULLF, and RFIFOEF. When the SPI is in 8-byte FIFO mode, the function of SPRF MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 715 (RXDMAE is 1), SPRF is automatically cleared when the first DMA transfer for the receive DMA request is completed (RX DMA Done is asserted). Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 716 MODF while it is 1 and then writing to the SPI Control Register 1 (C1). No mode fault error Mode fault error detected Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 717 FIFOMODE is 1, TNEAREF and RFIFOEF reset to 1. Read FIFO has data. Reads of the DH:DL registers in 16-bit mode or the DL register in 8-bit mode will empty the read FIFO. Read FIFO is empty. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 718: Spi Baud Rate Register (Spix_Br)
Baud rate divisor is 32. 0101 Baud rate divisor is 64. 0110 Baud rate divisor is 128. 0111 Baud rate divisor is 256. 1000 Baud rate divisor is 512. All others Reserved MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 719: Spi Control Register 2 (Spix_C2)
SPI data I/O pin. When SPC0 is 0, BIDIROE has no meaning or effect. Output driver disabled so SPI data I/O pin acts as an input SPI I/O pin enabled as an output Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 720: Spi Control Register 1 (Spix_C1)
When the FIFO is not supported or not enabled (FIFOMODE is not present or is 0): Enables the interrupt for SPI receive buffer full (SPRF) and mode fault (MODF) events. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 721 When C2[MODFEN] is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 722: Spi Match Register Low (Spix_Ml)
SPI match registers. Address: Base address + 4h offset Read Bits[7:0] Write Reset SPIx_ML field descriptions Field Description Bits[7:0] Hardware compare value (low byte) MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 723: Spi Match Register High (Spix_Mh)
In 8-bit mode, only the DL register is available. Reads of the DH register return all zeros. Writes to the DH register are ignored. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 724: Spi Data Register High (Spix_Dh)
Similarily, when the transmit FIFO is full and a write to the data register occurs, TXFOF is set. These flags are cleared when the CI register is read while the flags are set. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 725 Writing 1 to this bit clears the SPTEF interrupt provided that C3[3] is set. Receive FIFO full flag clear interrupt SPRFCI Writing 1 to this bit clears the SPRF interrupt provided that C3[3] is set. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 726: Spi Control Register 3 (Spix_C3)
TNEAREF is set when the transmit FIFO has 16 bits or less TNEAREF is set when the transmit FIFO has 32 bits or less Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 727: Functional Description
The SPI system is enabled by setting the SPI enable (SPE) bit in SPI Control Register 1. While C1[SPE] is set, the four associated SPI port pins are dedicated to the SPI function MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 728: Master Mode
The SPSCK pin is the SPI clock output. Through the SPSCK pin, the baud rate generator of the master controls the shift register of the slave peripheral. • MOSI, MISO pin MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 729: Slave Mode
The SPI operates in slave mode when the MSTR bit in SPI Control Register 1 is clear. • SPSCK In slave mode, SPSCK is the SPI clock input from the master. • MISO, MOSI pin MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 730 When C1[CPHA] is clear and the SS input is low (slave selected), the first bit of the SPI data is driven out of the serial data output pin. After the eighth (SPIMODE = MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 731: Spi Fifo Mode
Read Access SPI_REG_BLOCK spidh:l_rx_reg SPI Data Register FIFO depth = 8 bytes FIFO Ctrlr RX- FIFO SPI_CORE_SHFR Load Control shfr_rx_reg Figure 31-3. SPIH:L read side structural overview in FIFO mode MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 732: Spi Transmission By Dma
SPI for transmission in slave moe Wait for interrupt(s) of DMA Controller indicating end of SPI transmission Figure 31-5. Basic Flow of SPI Transmission by DMA MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 733 SPI data register into memory. After that, RX DMA DONE is asserted to clear SPRF automatically. This process repeats until all data to be MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 734: Data Transmission Length
SPIMODE, the SPIx_S register must be read with SPTEF = 1, and data must be written to SPIx_DH:SPIx_DL in 16-bit mode (SPIMODE = 1) or SPIx_DL in 8-bit mode (SPIMODE = 0). MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 735: Spi Clock Formats
The SS IN waveform applies to the slave select input of a slave. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 736 2. A new data byte is written to the transmit buffer before the in-progress transmission is complete. 3. When the in-progress transmission is complete, the new, ready data byte is transmitted immediately. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 737 BIT 1 BIT 0 BIT 1 BIT 5 BIT 7 LSB FIRST BIT 6 MISO (SLAVE OUT) SS OUT (MASTER) SS IN (SLAVE) Figure 31-7. SPI clock formats (CPHA = 0) MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 738: Spi Baud Rate Generation
1, 2, 3, 4, 5, 6, 7, or 8 BIT RATE 256, or 512 SPPR2:SPPR1:SPPR0 SPR3:SPR2:SPR1:SPR0 Figure 31-8. SPI baud rate generation 31.4.9 Special features The following section describes the special features of SPI module. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 739 The same pin is also the serial input to the shift register. The SPSCK is an output for the master mode and an input for the slave mode. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 740: Error Conditions
MOMI (MOSI in bidirectional mode) is cleared if it was set. No mode fault error occurs in the bidirectional mode for the SPI system configured in slave mode. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 741: Low-Power Mode Options
Otherwise, if the slave is currently sending the last data received byte from the master, it continues to send each previously received data from the master byte). MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 742: Reset
• If a data transmission occurs in slave mode after a reset without a write to SPIx_DH:SPIx_DL, the transmission consists of "garbage" or the data last received from the master before the reset. • Reading from SPIx_DH:SPIx_DL after reset always returns zeros. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 743: Interrupts
In 8-bit mode, SPRF is set only after all 8 bits have been shifted out of the shift register and into SPIx_DL. In 16-bit mode, SPRF is set only after all 16 bits have been shifted out of the shift register and into SPIx_DH:SPIx_DL. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 744 Clearing this interrupt depends on the state of C3[3] and the status of TNEAREF. Refer to the description of the SPI status (S) register. 31.4.13.6 RNFULLF The RNFULLF bit applies when the FIFO feature is supported. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 745: Initialization/Application Information
When operating the SPI at the maximum baud rate it must be configured for 16 bit operation. 31.5.1 Initialization sequence Before the SPI module can be used for communication, an initialization procedure must be carried out, as follows: MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 746: Pseudo-Code Example
SPI hardware match interrupt enabled Bit 6 SPIMODE Configures SPI for 16-bit mode Bit 5 TXDMAE DMA request disabled Bit 4 MODFEN Disables mode fault function Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 747 In 16-bit mode, this register holds bits 8–15 of the data to be transmitted by the transmit buffer and received by the receive buffer. SPIx_DL = 0xxx Holds bits 0–7 of the data to be transmitted by the transmit buffer and received by the receive buffer. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 748 READ SPMF WHILE SET TO CLEAR FLAG, THEN WRITE A 1 TO IT CONTINUE Figure 31-9. Initialization Flowchart Example for SPI Master Device in 16-bit Mode for FIFOMODE = 0 MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 749 TXFULLF = 1 RNFULLF = 1/ SPRF = 1 READ SPIxDH:SPIxDL RFIFOEF = 1 CONTINUE Figure 31-10. Initialization Flowchart Example for SPI Master Device in 16-bit Mode for FIFOMODE = 1 MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 750: Universal Asynchronous Receiver/Transmitter (Uart0)
• Programmable 1-bit or 2-bit stop bits • Receiver wakeup by idle-line, address-mark or address match • Optional 13-bit break character generation / 11-bit break character detection • Selectable transmitter output and receiver input polarity MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 751: Modes Of Operation
32.1.2.3 Debug mode The UART remains functional in debug mode. 32.1.3 Block diagram The following figure shows the transmitter portion of the UART. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 752 TO TxD Transmit Control Pin Logic TxD Direction TXDIR BRK13 TDRE Tx Interrupt Request TCIE Figure 32-1. UART transmitter block diagram The following figure shows the receiver portion of the UART. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 753: Register Definition
UART Status Register 1 (UART0_S1) 32.2.5/627 4006_A005 UART Status Register 2 (UART0_S2) 32.2.6/629 4006_A006 UART Control Register 3 (UART0_C3) 32.2.7/631 4006_A007 UART Data Register (UART0_D) 32.2.8/632 Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 754: Uart Baud Rate Register High (Uartx_Bdh)
The 13 bits in SBR[12:0] are referred to collectively as BR, and they set the modulo divide rate for the baud rate generator. When BR is 1 - 8191, the baud rate equals baud clock / ((OSR+1) × BR). MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 755: Uart Baud Rate Register Low (Uartx_Bdl)
Selects between loop back modes and normal 2-pin full-duplex modes. When LOOPS is set, the transmitter output is internally connected to the receiver input. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 756 1s in the data character, including the parity bit, is odd. Even parity means the total number of 1s in the data character, including the parity bit, is even. Even parity. Odd parity. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 757: Uart Control Register 2 (Uartx_C2)
When the UART receiver is off or LOOPS is set, the UART_RX pin is not used by the UART . When RE is written to 0, the receiver finishes receiving the current character (if any). Receiver disabled. Receiver enabled. Receiver Wakeup Control Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 758: Uart Status Register 1 (Uartx_S1)
• Queue a break character by writing 1 to UART_C2[SBK] Transmitter active (sending data, a preamble, or a break). Transmitter idle (transmission activity complete). Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 759 PF is set at the same time as RDRF when parity is enabled (PE = 1) and the parity bit in the received character does not agree with the expected parity value. To clear PF, write a logic one to the PF. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 760: Uart Status Register 2 (Uartx_S2)
This bit should only be changed when the transmitter and receiver are both disabled. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 761 RAF is set when the UART receiver detects the beginning of a valid start bit, and RAF is cleared automatically when the receiver detects an idle line. UART receiver idle waiting for a start bit. UART receiver active ( UART_RXD input not idle). MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 762: Uart Control Register 3 (Uartx_C3)
Transmit data not inverted. Transmit data inverted. Overrun Interrupt Enable ORIE This bit enables the overrun flag (OR) to generate hardware interrupt requests. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 763: Uart Data Register (Uartx_D)
Read receive data buffer 6 or write transmit data buffer 6. R6T6 Read receive data buffer 5 or write transmit data buffer 5. R5T5 Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 764: Uart Match Address Registers 1 (Uartx_Ma1)
Software should only write a MA register when the associated C4[MAEN] bit is clear. Address: Base address + 8h offset Read Write Reset UARTx_MA1 field descriptions Field Description Match Address MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 765: Uart Match Address Registers 2 (Uartx_Ma2)
MA2 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 766: Uart Control Register 5 (Uartx_C5)
This bit should only be changed when the receiver is disabled. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 767: Functional Description
Off If [SBR12:SBR0] =0 UART ASYNCH Module Clock Baud Rate = SBR[12:0] × (OSR+1) Figure 32-3. UART baud rate generation Baud rate generation is subject to two sources of error: MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 768: Transmitter Functional Description
A longer break of 13-bit times can be enabled by setting UART_S2[BRK13]. Normally, a program would wait for UART_S1[TDRE] to become set to indicate the last character of a message has moved to the transmit MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 769: Receiver Functional Description
In this section, the receiver block diagram is a guide for the overall receiver functional description. Next, the data sampling technique used to reconstruct receiver data is described in more detail. Finally, two variations of the receiver wakeup function are explained. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 770 (UART_S1[NF]) is set when the received character is transferred to the receive data buffer. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 771 UART_S1[IDLE] flag. The receiver wakes up and waits for the first data character of the next message that sets the UART_S1[RDRF] flag MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 772 UART_C4[MAEN2] bits are negated, the receiver operates normally and all data received is transferred to the receive data buffer. Match Address operation functions in the same way for both MA1 and MA2 registers. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 773: Additional Uart Functions
In custom protocols, the ninth and/or tenth bits can also serve as software-controlled markers. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 774: Interrupts And Status Flags
UART_D. If the transmit interrupt enable (UART_C2[TIE]) bit is set, a hardware interrupt is requested when UART_S1[TDRE] is set. Transmit complete (UART_S1[TC]) indicates that the MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 775 At any time, an active edge on the UART_RX serial data input pin causes the UART_S2[RXEDGIF] flag to set. The UART_S2[RXEDGIF] flag is cleared by writing a 1 to it. This function depends on the receiver being enabled (UART_C2[RE] = 1). MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 776: Universal Asynchronous Receiver/Transmitter (Uart1 And Uart2)
• Programmable 1-bit or 2-bit stop bits • Receiver wakeup by idle-line or address-mark • Optional 13-bit break character generation / 11-bit break character detection • Selectable transmitter output polarity • 5-channel DMA interface MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 777: Modes Of Operation
Tx Pin Logic TRANSMITTER CONTROL DMA done TDRE TXDIR TDRE INTERRUPT/DMA REQUEST TC INTERRUPT/DMA TCIE REQUEST Figure 33-1. UART transmitter block diagram The following figure shows the receiver portion of the UART. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 778 IDLE ILIE Interrupt/DMA Request LBKDIF LBKDIE From RxD Pin (ipp_ind_sci_rx) ACTIVE EDGE RXEDGIF DETECT RXEDGIE ORIE FEIE Error Interrupt Request NEIE PARITY CHECKING PEIE Figure 33-2. UART receiver block diagram MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 779: Uart Signal Descriptions
UART registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 780: Uart Baud Rate Register: High (Uartx_Bdh)
Address: Base address + 0h offset Read LBKDIE RXEDGIE SBNS Write Reset UARTx_BDH field descriptions Field Description LIN Break Detect Interrupt Enable (for LBKDIF) LBKDIE Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 781: Uart Baud Rate Register: Low (Uartx_Bdl)
UART baud rate generator. When BR is cleared, the UART baud rate generator is disabled to reduce supply current. When BR is 1 - 8191, the UART baud rate equals BUSCLK/(16×BR). MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 782: Uart Control Register 1 (Uartx_C1)
Receiver and transmitter use 9-bit data characters start + 8 data bits (lsb first) + 9th data bit + stop. Receiver Wakeup Method Select WAKE This field selects the receiver wakeup method. Idle-line wake-up. Address-mark wake-up. Idle Line Type Select Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 783: Uart Control Register 2 (Uartx_C2)
Receiver Interrupt Enable for RDRF Hardware interrupts from S1[RDRF] disabled; use polling. Hardware interrupt requested when S1[RDRF] flag is 1. Idle Line Interrupt Enable for IDLE ILIE Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 784 Depending on the timing of the set and clear of SBK relative to the information currently being transmitted, a second break character may be queued before software clears SBK. Normal transmitter operation. Queue break character(s) to be sent. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 785: Uart Status Register 1 (Uartx_S1)
Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 786: Uart Status Register 2 (Uartx_S2)
0x00 data character can appear to be 10.26 bit times long at a slave running 14% faster than the master. This would trigger normal break detection circuitry MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 787 Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1). Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 788: Uart Control Register 3 (Uartx_C3)
When the UART is configured for single-wire half-duplex operation (LOOPS = RSRC = 1), this field determines the direction of data at the TxD pin. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 789: Uart Data Register (Uartx_D)
UART status flags. Address: Base address + 7h offset Read R7T7 R6T6 R5T5 R4T4 R3T3 R2T2 R1T1 R0T0 Write Reset MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 790: Uart Control Register 4 (Uartx_C4)
If TIE is set and the TDRE flag is set, the TDRE DMA request signal is asserted to request a DMA transfer. This field is reserved. Reserved This read-only field is reserved and always has the value 0. Receiver Full DMA Select RDMAS Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 791: Functional Description
SBR[12:0] Rx Sampling Clock Baud Rate Generator (16 × Baud Rate) Off If [SBR12:SBR0] =0 UART Module Clock Baud Rate = SBR[12:0] × 16 Figure 33-3. UART baud rate generation MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 792: Transmitter Functional Description
If no new character is waiting in the transmit data buffer after a stop bit is shifted out the TxD pin, the transmitter sets the transmit complete flag and enters an idle mode, with TxD high, waiting for more characters to transmit. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 793 Table 33-3. Break character length BRK13 SBNS Break character length 10 bit times 11 bit times 11 bit times 12 bit times 13 bit times 14 bit times Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 794: Receiver Functional Description
RxD serial data input pin. A falling edge is defined as a logic 0 sample after three consecutive logic 1 samples. The 16× baud rate clock divides the bit time into 16 segments labeled UART_D[RT1] through UART_D[RT16]. When a MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 795 UART_C2[RWU] to 0, so all receivers wake up in time to look at the first character(s) of the next message. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 796: Interrupts And Status Flags
33.4.4 Interrupts and status flags The UART system has three separate interrupt vectors to reduce the amount of software needed to isolate the cause of the interrupt. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 797 (UART_S1[OR]) flag is set instead of the data along with any associated NF, FE, or PF condition is lost. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 798: Baud Rate Tolerance
The maximum percent difference between the receiver count and the transmitter count of a slow 8-bit data and 1 stop bit character with no errors is: ((154 - 147) / 154) x 100 = 4.54% MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 799 The maximum percent difference between the receiver count and the transmitter count of a fast 8-bit and 1 stop bit character with no errors is: ((154 - 160) / 154) x 100 = 3.90% MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 800: Dma Operation
When the RDRF or IDLE flag is configured as a DMA request, the clearing mechanism of reading UART_S1 followed by reading UART_D does not clear the associated flag.The DMA request remains asserted until an indication is received that MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 801: Additional Uart Functions
The receive input active edge detect circuit remains active in Stop3 mode. An active edge on the receive input brings the CPU out of stop and VLPS mode if the interrupt is not masked (UART_BDH[RXEDGIE] = 1). MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 802 In single-wire mode, the transmitter output is internally connected to the receiver input and the RxD pin is not used by the UART, so it reverts to a general-purpose port I/O pin. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 803 Functional description MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 804: General-Purpose Input/Output (Gpio)
• Port Data Output register with corresponding set/clear/toggle registers • Port Data Direction register • Zero wait state access to GPIO registers through IOPORT NOTE The GPIO module is clocked by system clock. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 805: Modes Of Operation
PORTD31–PORTD0 signal occurs on the rising- PORTE31–PORTE0 edge of the system clock. For input, it may occur at any time and input may be asserted asynchronously to the system clock. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 806: Memory Map And Register Definition
(always 0000_0000h 34.2.3/678 reads 0) 400F_F00C Port Toggle Output Register (GPIOA_PTOR) (always 0000_0000h 34.2.4/678 reads 0) 400F_F010 Port Data Input Register (GPIOA_PDIR) 0000_0000h 34.2.5/679 Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 807 0000_0000h 34.2.1/677 400F_F104 Port Set Output Register (GPIOE_PSOR) (always 0000_0000h 34.2.2/677 reads 0) 400F_F108 Port Clear Output Register (GPIOE_PCOR) (always 0000_0000h 34.2.3/678 reads 0) Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 808: Port Data Output Register (Gpiox_Pdor)
Logic level 1 is driven on pin, provided pin is configured for general-purpose output. 34.2.2 Port Set Output Register (GPIOx_PSOR) This register configures whether to set the fields of the PDOR. Address: Base address + 4h offset PTSO Reset MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 809: Port Clear Output Register (Gpiox_Pcor)
Address: Base address + Ch offset PTTO Reset GPIOx_PTOR field descriptions Field Description PTTO Port Toggle Output Writing to this register will update the contents of the corresponding bit in the PDOR as follows: MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 810: Port Data Input Register (Gpiox_Pdir)
Pin logic level is logic 1. 34.2.6 Port Data Direction Register (GPIOx_PDDR) The PDDR configures the individual port pins for input or output. Address: Base address + 14h offset Reset MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 811: Fgpio Memory Map And Register Definition
0) F800_0008 Port Clear Output Register (FGPIOA_PCOR) (always 0000_0000h 34.3.3/683 reads 0) F800_000C Port Toggle Output Register (FGPIOA_PTOR) (always 0000_0000h 34.3.4/683 reads 0) Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 812 F800_00D4 Port Data Direction Register (FGPIOD_PDDR) 0000_0000h 34.3.6/684 F800_0100 Port Data Output Register (FGPIOE_PDOR) 0000_0000h 34.3.1/682 F800_0104 Port Set Output Register (FGPIOE_PSOR) (always 0000_0000h 34.3.2/682 reads 0) Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 813: Port Data Output Register (Fgpiox_Pdor)
Logic level 1 is driven on pin, provided pin is configured for general-purpose output. 34.3.2 Port Set Output Register (FGPIOx_PSOR) This register configures whether to set the fields of the PDOR. Address: Base address + 4h offset PTSO Reset MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 814: Port Clear Output Register (Fgpiox_Pcor)
Address: Base address + Ch offset PTTO Reset FGPIOx_PTOR field descriptions Field Description PTTO Port Toggle Output Writing to this register will update the contents of the corresponding bit in the PDOR as follows: MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 815: Port Data Input Register (Fgpiox_Pdir)
Port Data Direction Configures individual port pins for input or output. Pin is configured as general-purpose input, for the GPIO function. Pin is configured as general-purpose output, for the GPIO function. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 816: Functional Description
If the DMA attempts to access the GPIO registers on the same cycle as an IOPORT access, then the DMA access will stall until any IOPORT accesses have completed. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 817 Since the clocks to the Port Control and Interrupt modules are disabled during Compute Operation, the Pin Data Input Registers do not update with the current state of the pins. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 818: Touch Sensing Input (Tsi)
• High sensitivity change with 16-bit resolution register • Configurable up to 4096 scan times. • Support DMA data transfer • The auxiliary noise detection mode supplies improved EMC immunity. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 819: Modes Of Operation
Electrode Oscillator Reference Clock TSI14 Reference TSI15 Oscillator Interrupt TSI_PENx TSICH Control Hardware Trigger SCNIP Logic Write SWTS “1” EXTCHRG REFCHRG CURSW EOSF TSIIEN Figure 35-1. TSI module block diagram MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 820: External Signal Description
0000_0000h 35.3.2/694 4004_5008 TSI Threshold Register (TSI0_TSHD) 0000_0000h 35.3.3/695 35.3.1 TSI General Control and Status Register (TSIx_GENCS) This control register provides various control and configuration information for the TSI module. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 821 End-of-scan or Out-of-Range Interrupt Selection ESOR This bit is used to select out-of-range or end-of-scan event to generate an interrupt. Out-of-range interrupt is allowed. End-of-scan interrupt is allowed. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 822 15–13 These bits indicate the prescaler of the output of electrode oscillator. Electrode Oscillator Frequency divided by 1 Electrode Oscillator Frequency divided by 2 Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 823 30 times per electrode 11110 31 times per electrode 11111 32 times per electrode Touch Sensing Input Module Enable TSIEN This bit enables TSI module. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 824 This bit specifies if the current sources of electrode oscillator and reference oscillator are swapped. The current source pair are not swapped. The current source pair are swapped. This field is reserved. Reserved This read-only field is reserved and always has the value 0. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 825: Tsi Data Register (Tsix_Data)
0110 Channel 6. 0111 Channel 7. 1000 Channel 8. 1001 Channel 9. 1010 Channel 10. 1011 Channel 11. 1100 Channel 12. 1101 Channel 13. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 826: Tsi Threshold Register (Tsix_Tshd)
TSI Wakeup Channel High-threshold THRESH This half-word specifies the high threshold of the wakeup channel. THRESL TSI Wakeup Channel Low-threshold This half-word specifies the low threshold of the wakeup channel. 35.4 Functional description MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 827: Capacitance Measurement
GENCS[EXTCHRG]. The hysteresis delta voltage is defined in the module electrical specifications present in the device Data Sheet. The figure below shows the voltage amplitude waveform of the electrode capacitance charging and discharging with a programmable current. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 828 The pin capacitance sampling time is given by the time the module counter takes to go from 0 to its maximum value, defined by NSCN. The electrode sample time is expressed by the following equation: PS * NSCN cap_samp elec MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 829 Equation 6. TSI reference oscillator frequency Where: : Internal reference capacitor : Reference oscillator current source ∆V : Hysteresis delta voltage Considering C = 1.0 pF, I = µA and ∆V = V, follows MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 830: Tsi Measurement Result
The TSI provides multi-scan function. The number of scans is indicated by TSI_GENCS[NSCN] that allow the scan number from 1 to 32. When TSI_GENCS[NSCN] is set to 0 (only once), the single scan is engaged. The 16-bit MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 831: Clock Setting
64 µA. TSI_GENCS[EXTCHRG] determines the current of electrode oscillator that charges and discharges external electrodes. The TSI_GENCS[REFCHRG] determines the current of reference oscillator on which the internal reference clock depends. The lower MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 832: End Of Scan
0xFFFF is treated as an extreme case the out- of-range will not happen. Also in noise detection mode, the out-of-range will not assert either. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 833: Wake Up Mcu From Low Power Modes
DVOLT register bits. Be noted There is no oscillation on external pad (just if it is caused by external noise) in this mode. Also the external voltage is biased by vmid voltage with a Rs series resistance. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 834 STAT<1:0> EXTCHRG NSCN REFCHRG (Count_noise) Cref 16-bit clk_ext TSI_CNTH counter1 TSI_CNTL Noise Mode DVOLT Filter prescaler counter2 clk_ref STAT<1:0> EXTCHRG NSCN Figure 35-5. TSI noise detection mode block diagram MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 835 32K/0.73V, 14K/0.73V, 14K/1.03V, 5K/1.03V To determine the noise level, the TSI noise detection algorithm shall be performed by scanning this table following the arrow direction starting at maximum Rs and minimum DVOLT. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 836 4. Start TSI scan with software trigger or hardware trigger just as does for normal function mode 5. Wait until TSI scan is complete (TSI_CS0[EOSF] = 1); 6. Read TSI counter value in TSI_CNTH:TSI_CNTL and then clear TSI_CS0[EOSF] flag; MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 837 Figure 35-7. Noise Capacitive Noise sense sense sense Figure 35-7. Noise detection/sense algorithm of typical application MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 838 • The Rs series resistance value is changed between 184 kΩ (TSI_CS2[EXTCHRG]=011b), 77 kΩ (TSI_CS2[EXTCHRG]=100) and 32 kΩ(TSI_CS2[EXTCHRG] = 101). Because of this Rs change the amplitude of noise waveform change also. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 839 DVOLT control bits are increased the DVOLT thresholds are increased as well. The four bits are counted until 1111 (=15) and the counter is stop with this maximum value. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 840 0—uses Rs=32 kΩ 1—uses Rs=187 kΩ Independent of this bit selection, the threshold 15 is done with Rs = 5.5 kΩ Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 841 1100 - DVpm = 1.026 V, Vp = 1.328 V, Vm = 0.302 V 1101 - DVpm = 1.350 V, Vp = 1.490 V, Vm = 0.140 V Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 842 In this operation mode this bits selects the series resistance. 0 - uses Rs = 32 kΩ. 1- uses Rs = 187 kΩ. Independent of this bit selection the threshold 15 is done with Rs = 5.5 kΩ. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 843 Functional description MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 844: Inter-Integrated Circuit (I2C)
• Software programmable for one of 64 different serial clock frequencies • Software-selectable acknowledge bit • Interrupt-driven byte-by-byte data transfer • Arbitration-lost interrupt with automatic mode switching from master to slave MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 845: Modes Of Operation
Stop mode. The STOP instruction does not affect the I2C module's register states. 36.1.3 Block diagram The following figure is a functional block diagram of the I2C module. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 846: I2C Signal Descriptions
C are shown in the table found here. Table 36-1. I C signal descriptions Signal Description Bidirectional serial clock line of the I C system. Bidirectional serial data line of the I C system. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 847: Memory Map/Register Definition
I2C SMBus Control and Status register (I2C1_SMB) 36.3.9/725 36.3.10/ 4006_7009 I2C Address Register 2 (I2C1_A2) 36.3.11/ 4006_700A I2C SCL Low Timeout Register High (I2C1_SLTH) 36.3.12/ 4006_700B I2C SCL Low Timeout Register Low (I2C1_SLTL) MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 848: I2C Address Register 1 (I2Cx_A1)
The SCL divider multiplied by multiplier factor (mul) determines the I2C baud rate. I2C baud rate = I2C module clock speed (Hz)/(mul × SCL divider) Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 849: I2C Control Register 1 (I2Cx_C1)
RSTA Reset I2Cx_C1 field descriptions Field Description I2C Enable IICEN Enables I2C module operation. Disabled Enabled I2C Interrupt Enable IICIE Enables I2C interrupt requests. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 850 • a data byte is received, and either address or data is transmitted. (ACK/NACK is automatic) • the first byte received matches the A1 register or is a general call address. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 851: I2C Status Register (I2Cx_S)
Indicates the status of the bus regardless of slave or master mode. This bit is set when a START signal is detected and cleared when a STOP signal is detected. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 852 IICIF bit. If this sequence is reversed, the IICIF bit is asserted again. No interrupt pending Interrupt pending Receive Acknowledge RXAK Acknowledge signal was received after the completion of one byte of data transmission on the bus No acknowledge signal detected MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 853: I2C Data I/O Register (I2Cx_D)
GCAEN ADEXT HDRS SBRC RMEN AD[10:8] Write Reset I2Cx_C2 field descriptions Field Description General Call Address Enable GCAEN Enables general call address. Disabled Enabled Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 854: I2C Programmable Input Glitch Filter Register (I2Cx_Flt)
Field Description Stop Hold Enable SHEN Set this bit to hold off entry to stop mode when any data transmission or reception is occurring. Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 855 No filter/bypass 01-1Fh Filter glitches up to width of n I2C module clock cycles, where n=1-31d MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 856: I2C Range Address Register (I2Cx_Ra)
SHTF1 bit because the bus speed is too high to match the protocol of SMBus. Address: Base address + 8h offset Read SLTF SHTF1 SHTF2 FACK ALERTEN SIICAEN TCKSEL SHTF2IE Write Reset MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 857 This bit sets when SCL is held high and SDA is held low more than clock × LoValue / 512. Software clears this bit by writing 1 to it. No SCL high and SDA low timeout occurs SCL high and SDA low timeout occurs Table continues on the next page... MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 858: I2C Address Register 2 (I2Cx_A2)
Address: Base address + Ah offset Read SSLT[15:8] Write Reset I2Cx_SLTH field descriptions Field Description SSLT[15:8] SSLT[15:8] Most significant byte of SCL low timeout value that determines the timeout period of SCL low. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 859: I2C Scl Low Timeout Register Low (I2Cx_Sltl)
2. Slave address transmission 3. Data transfer 4. STOP signal The STOP signal should not be confused with the CPU STOP instruction. The following figure illustrates I2C bus system communication. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 860 Only the slave with a calling address that matches the one transmitted by the master responds by sending an acknowledge bit. The slave sends the acknowledge bit by pulling SDA low at the ninth clock. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 861 A STOP signal is defined as a low-to-high transition of SDA while SCL is asserted. The master can generate a STOP signal even if the slave has generated an acknowledgement, at which point the slave must release the bus. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 862 Afterward there is no difference between the device clocks and the state of SCL, and all devices start counting their high periods. The first device to complete its high period pulls SCL low again. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 863 ±2 or ±4 when ICR's value ranges from 00h to 0Fh. These potentially varying SCL divider values are highlighted in the following table. For the actual SCL divider values for your device, see the chip-specific details about the I2C module. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 864: 10-Bit Address
(hex) (hex) value value (clocks) value value 1024 1152 1280 1536 1920 1280 1536 1792 2048 1022 1025 2304 1150 1153 2560 1278 1281 3072 1534 1537 3840 1918 1921 MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 865 A3. The slave-transmitter remains addressed until it receives a STOP condition (P) or a repeated START condition (Sr) followed by a different slave address. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 866: Address Matching
When the I2C module responds to one of these addresses, it acts as a slave-receiver and the IAAS bit is set after the address cycle. Software must read the Data register after the first byte transfer to determine that the address is matched. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 867: System Management Bus Specification
When the I2C module is a slave, if it detects the condition, it resets its communication and is then able to receive a new TIMEOUT,MIN START condition. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 868 START to the STOP. When CSMBCLK LOW:SEXT TIMEOUT SEXT occurs, SEXT rises and also triggers SLTF. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 869: Resets
NACK to the bus, so FACK must be switched off before the last byte transmits. 36.4.5 Resets The I2C module is disabled after a reset. The I2C module cannot cause a core reset. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 870: Interrupts
GCAEN bit is set and a general call is received, the IAAS bit in the Status Register is set. The CPU is interrupted, provided the IICIE bit is set. The CPU must check the SRW bit and set its Tx mode accordingly. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 871 SHTF2) upon detection of any of the mentioned timeout conditions, with one exception. The SCL high and SDA high TIMEOUT mechanism must not be used to influence the timeout interrupt output, because this timeout indicates an idle condition on the bus. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 872: Programmable Input Glitch Filter
After the system recovers and is in Run mode, restart the I2C module if it is needed to transfer packets. To avoid I2C transfer problems resulting from the situation, firmware should prevent MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 873: Dma Support
4. Initialize RAM variables (IICEN = 1 and IICIE = 1) for transmit data 5. Initialize RAM variables used to achieve the routine shown in the following figure Module Initialization (Master) MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 874 Data register. An example of an I2C driver which implements many of the steps described here is available in AN4342: Using the Inter-Integrated Circuit on ColdFire+ and Kinetis MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 875 2. When 10-bit addressing addresses a slave, the slave sees an interrupt following the first byte of the extended address. Ensure that for this interrupt, the contents of the Data register are ignored and not treated as a valid data transfer. Figure 36-6. Typical I2C interrupt routine MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 876 (in worst case) of the 9th SCL cycle. 3. This read is a dummy read in order to reset the SMBus receiver state machine. Figure 36-7. Typical I2C SMBus interrupt routine MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 877 Initialization/application information MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 878 Also updated input signal of AD13 and AD14 channels to Reserved. • Updated topic 1.7.3.3 12-bit DAC Analog Supply and Reference Connections. A.3 Memory Map chapter changes No substantial content changes A.4 Clock Distribution chapter changes No substantial content changes MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 879 • In Pin Control Register (PCRn), added additional details to Interrupt Configuration field (IRQC) description. A.9 SIM changes No substantial content changes A.10 SMC changes • No substantial content changes A.11 PMC changes • No substantial content changes MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 880 • No substantial content changes A.16 MTB configuration changes • No substantial content changes A.17 Crossbar switch module changes • No substantial content changes A.18 AIPS module changes • No substantial content changes MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 881 • No substantial content changes A.24 FTFA changes • No substantial content changes A.25 ADC changes • Editorial changes • Changed bitfield access of ADC_SC3[CALF] to w1c (write 1 to clear). MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 882 A.31 RTC changes • No substantial content changes A.32 SPI changes • Removed "Recommended startup of SPI transmit by DMA" flowchart and associated description from the Transmit by DMA topic. MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
Page 883 No substantial content changes A.34 UART chapter changes • No substantial content changes A.35 GPIO changes • Updated Features A.36 Touch sense input chapter changes • No substantial content changes MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016 Freescale Semiconductor, Inc.
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