NXP Semiconductors MKW01Z128 Manuals

Manuals and User Guides for NXP Semiconductors MKW01Z128. We have 1 NXP Semiconductors MKW01Z128 manual available for free PDF download: Reference Manual

NXP Semiconductors MKW01Z128 Reference Manual (884 pages)

Sub 1 GHz Low Power Transceiver plus Microcontroller

Brand: NXP Semiconductors | Category: Transceiver | Size: 5 MB

Mkw01Z128

2
- Table of Contents
  2
- References
  10
- Chapter 1 MKW01Z128 Introduction and Chip Configuration
  
  12
  - KW01 Family Introduction
    13
  - Ordering Information
    13
  - General Platform Features
    14
  - MCU Features
    14
  - RF Transceiver Features
    15
  - Software Solutions
    15
  - System Overview
    16
  - MCU Overview
    18
  - Module Functional Categories
    18
  - Transceiver Overview
    18
  - ARM Cortex-M0 Core Modules
    19
  - System Modules
    20
  - Clock Modules
    21
  - Memories and Memory Interfaces
    21
  - Security and Integrity Module
    21
  - Analog Modules
    22
  - Radio
    22
  - Timer Modules
    22
  - Communication Interfaces
    23
  - Human-Machine Interfaces
    23
  - System Device Identification Register
    23
- Chapter 2 MKW01Z128 Pins and Connections
  
  24
  - Device Pin Assignment
    24
  - Pin Definitions
    25
  - Internal Functional Interconnects
    29
- Chapter 3 Signal Multiplexing and Signal Descriptions
  
  32
- Chapter 4 System Considerations
  
  38
- Chapter 5 Sub 1 Ghz Transceiver Architecture Description
  
  56
  - Overview
    56
  - Simplified Block Diagram
    56
  - Low Battery Detector
    57
  - Transceiver Power Supply
    57
  - CLKOUT Output
    58
  - Frequency Synthesis
    58
  - Reference Oscillator
    58
  - Carrier Frequency and Resolution
    59
  - Lock Time
    59
  - PLL Architecture
    59
    
    Vco
    59
  - PLL Bandwidth
    59
  - Lock Detect Indicator
    60
  - Transmitter Description
    60
  - Bit Rate Setting
    61
  - FSK Modulation
    62
  - Modulation Shaping
    62
  - OOK Modulation
    62
  - Power Amplifiers
    62
  - LNA - Single to Differential Buffer
    64
  - Over Current Protection
    64
  - Receiver Description
    64
  - Automatic Gain Control
    65
  - AGC Reference
    67
  - Continuous-Time DAGC
    67
  - Quadrature Mixer - Adcs - Decimators
    67
  - Rssithreshold Setting
    67
  - Channel Filter
    68
  - DC Cancellation
    69
  - Complex Filter - OOK
    70
  - Rssi
    70
  - Cordic
    71
  - FSK Demodulator
    72
  - OOK Demodulator
    72
  - Optimizing the Floor Threshold
    73
  - Alternative OOK Demodulator Threshold Modes
    74
  - Bit Synchronizer
    74
  - Optimizing OOK Demodulator for Fast Fading Signals
    74
  - Frequency Error Indicator (FEI)
    76
  - Automatic Frequency Correction (AFC)
    77
  - Optimized Setup for Low Modulation Index Systems
    77
  - Temperature Sensor
    78
  - High Bit Rate Operations
    79
  - Kbps Operation
    79
- Chapter 6 Transceiver Operating Modes
  
  80
  - Timeout Function
    79
  - Automatic Sequencer and Wake-Up Times
    80
  - Basic Modes
    80
  - Transmitter Startup Time
    81
  - TX Start Procedure
    81
  - Receiver Startup Time
    82
  - Optimized Frequency Hopping Sequences
    83
  - RX Start Procedure
    83
  - Listen Mode
    84
  - Timing
    84
  - Criteria
    85
  - End of Cycle Actions
    85
  - Automodes
    86
- Chapter 7 Transceiver Digital Control and Communications
  
  88
  - RC Timer Accuracy
    86
  - Data Operation Modes
    88
  - Overview
    88
  - Control Block Description
    89
  - SPI Interface
    89
  - Fifo
    90
  - Overview and Shift Register (SR)
    90
    
    Size
    91
  - Interrupt Sources and Flags
    91
    
    FIFO Clearing
    92
  - Sync Word Recognition
    92
    
    Overview
    92
  - Configuration
    93
  - Control
    93
  - Digital IO Pins Mapping
    93
  - Packet Handler
    93
  - DIO Pins Mapping in Continuous Mode
    94
  - DIO Pins Mapping in Packet Mode
    94
  - Continuous Mode
    95
  - General Description
    95
  - TX Processing
    95
  - General Description
    96
  - Packet Mode
    96
  - RX Processing
    96
  - Fixed Length Packet Format
    97
  - Packet Format
    97
  - Variable Length Packet Format
    98
  - TX Processing (Without AES)
    99
  - Unlimited Length Packet Format
    99
  - RX Processing (Without AES)
    100
  - Aes
    101
  - RX Processing
    101
  - TX Processing
    101
  - Handling Large Packets
    102
  - Packet Filtering
    102
  - Sync Word Based
    102
    
    Address Based
    103
    
    Length Based
    103
    
    CRC Based
    103
  - DC-Free Data Mechanisms
    104
  - Manchester Encoding
    104
  - Data Whitening
    105
  - Register Summary
    105
  - Common Configuration Registers
    108
  - Transmitter Registers
    112
  - Receiver Registers
    113
  - IRQ and Pin Mapping Registers
    116
  - Packet Engine Registers
    119
  - Temperature Sensor Registers
    123
  - Test Registers
    123
- Chapter 8 MKW01Z128 Transceiver - MCU SPI Interface
  
  124
  - Sip Level SPI Pin Connections
    124
  - Features
    125
  - SPI System Block Diagram
    125
  - Master in / Slave out (MISO)
    126
  - Master out / Slave in (MOSI)
    126
  - Mkw0Xxx SPI Transaction Protocol
    126
  - Slave Select (SS or NSS)
    126
  - SPI Clock (SCK or SPSCK)
    126
  - SPI Signal Definitions
    126
  - Mkw0Xxx SPI Transaction Timing
    127
- Appendix A
  
  132
  - MKW01Z128 MCU Reference Manual
    132
Table of Contents

134
- Chip Configuration
  160
- Introduction
  160
- Module to Module Interconnects
  160
  - Interconnection Overview
    160
  - Analog Reference Options
    162
- Core Modules
  162
- System Modules
  170
  - SIM Configuration
    170
  - System Mode Controller (SMC) Configuration
    171
  - PMC Configuration
    171
  - Low-Leakage Wake-Up Unit (LLWU) Configuration
    172
  - MCM Configuration
    174
  - Crossbar-Light Switch Configuration
    175
  - Peripheral Bridge Configuration
    176
  - DMA Request Multiplexer Configuration
    177
  - DMA Controller Configuration
    180
  - Computer Operating Properly (COP) Watchdog Configuration
    180
- Clock Modules
  183
  - MCG Configuration
    183
  - OSC Configuration
    184
- Memories and Memory Interfaces
  185
  - Flash Memory Configuration
    185
  - Flash Memory Controller Configuration
    187
  - SRAM Configuration
    188
  - System Register File Configuration
    190
- Analog
  190
  - 16-Bit SAR ADC Configuration
    190
  - CMP Configuration
    193
  - 12-Bit DAC Configuration
    196
- Timers
  197
  - Timer/Pwm Module Configuration
    197
  - PIT Configuration
    200
  - Low-Power Timer Configuration
    201
  - RTC Configuration
    203
- Communication Interfaces
  205
  - SPI Configuration
    205
  - I2C Configuration
    206
  - UART Configuration
    207
- Human-Machine Interfaces (HMI)
  208
  - GPIO Configuration
    208
  - TSI Configuration
    210
- Introduction
  212
- System Memory Map
  212
- Flash Memory Map
  213
  - Alternate Non-Volatile IRC User Trim Description
    214
- Bit Manipulation Engine
  214
- SRAM Memory Map
  214
- Peripheral Bridge (AIPS-Lite) Memory Map
  215
- Private Peripheral Bus (PPB) Memory Map
  219
  - Clock Distribution
    222
- High-Level Device Clocking Diagram
  222
- Introduction
  222
- Programming Model
  222
- Clock Definitions
  223
  - Device Clock Summary
    224
- Internal Clocking Requirements
  226
  - Clock Divider Values after Reset
    227
  - VLPR Mode Clocking
    227
- Clock Gating
  228
- Module Clocks
  228
  - PMC 1-Khz LPO Clock
    229
  - COP Clocking
    229
  - RTC Clocking
    230
  - LPTMR Clocking
    230
  - TPM Clocking
    231
  - SPI Clocking
    231
  - I2C Clocking
    232
  - UART Clocking
    232
  - Reset and Boot
    234
- Introduction
  234
- Reset
  234
  - Power-On Reset (POR)
    235
  - System Reset Sources
    235
  - MCU Resets
    238
  - RESET Pin
    240
  - Debug Resets
    240
- Boot
  241
  - Boot Sources
    241
  - FOPT Boot Options
    241
  - Boot Sequence
    243
  - Power Management
    244
- Clocking Modes
  244
  - Partial Stop
    244
  - DMA Wakeup
    245
  - Compute Operation
    246
  - Peripheral Doze
    247
  - Clock Gating
    248
- Introduction
  244
- Power Modes
  248
- Entering and Exiting Power Modes
  250
- Module Operation in Low-Power Modes
  251
  - Debug
    256
- Debug Port Pin Descriptions
  256
- Introduction
  256
- SWD Status and Control Registers
  257
  - MDM-AP Control Register
    258
  - MDM-AP Status Register
    259
- Debug Resets
  261
- Debug in Low-Power Modes
  262
- Micro Trace Buffer (MTB)
  262
- Debug and Security
  263
- Introduction
  264
- Overview
  264
  - Features
    264
  - Modes of Operation
    265
- Port Control and Interrupts (PORT)
  264
- Detailed Signal Description
  266
- External Signal Description
  266
- Memory Map and Register Definition
  266
- Functional Description
  276
  - Pin Control
    276
  - Global Pin Control
    277
  - External Interrupts
    277
- Introduction
  280
  - Features
    280
- Memory Map and Register Definition
  280
- System Integration Module (SIM)
  280
- Functional Description
  304
- Chapter 9 System Mode Controller (SMC)
  
  306
  - Introduction
    306
  - Modes of Operation
    306
  - Memory Map and Register Descriptions
    308
    
    Power Mode Protection Register (SMC_PMPROT)
    309
    
    Power Mode Control Register (SMC_PMCTRL)
    310
    
    Stop Control Register (SMC_STOPCTRL)
    311
    
    Power Mode Status Register (SMC_PMSTAT)
    313
  - Functional Description
    313
    
    Power Mode Transitions
    313
    
    Power Mode Entry/Exit Sequencing
    316
    
    Run Modes
    318
    
    Wait Modes
    320
    
    Stop Modes
    321
    
    Debug in Low Power Modes
    324
  - Features
    326
  - Introduction
    326
  - Low-Voltage Detect (LVD) System
    326
    
    LVD Reset Operation
    327
    
    LVD Interrupt Operation
    327
    
    Low-Voltage Warning (LVW) Interrupt Operation
    327
  - Power Management Controller (PMC)
    326
  - I/O Retention
    328
  - Memory Map and Register Descriptions
    328
    
    Low Voltage Detect Status and Control 1 Register (PMC_LVDSC1)
    329
    
    Low Voltage Detect Status and Control 2 Register (PMC_LVDSC2)
    330
    
    Regulator Status and Control Register (PMC_REGSC)
    331
- Chapter 11 Low-Leakage Wakeup Unit (LLWU)
  
  334
  - Introduction
    334
    
    Features
    334
    
    Modes of Operation
    335
    
    Block Diagram
    336
  - Reserved Bits in LLWU_PE3 and LLWU_F2 Registers
    334
  - LLWU Signal Descriptions
    337
  - Memory Map/Register Definition
    338
    
    LLWU Pin Enable 1 Register (LLWU_PE1)
    339
    
    LLWU Pin Enable 2 Register (LLWU_PE2)
    340
    
    LLWU Pin Enable 3 Register (LLWU_PE3)
    341
    
    LLWU Pin Enable 4 Register (LLWU_PE4)
    342
    
    LLWU Module Enable Register (LLWU_ME)
    343
    
    LLWU Flag 1 Register (LLWU_F1)
    345
    
    LLWU Flag 2 Register (LLWU_F2)
    346
    
    LLWU Flag 3 Register (LLWU_F3)
    348
    
    LLWU Pin Filter 1 Register (LLWU_FILT1)
    350
    
    LLWU Pin Filter 2 Register (LLWU_FILT2)
    351
  - Functional Description
    352
    
    LLS Mode
    352
    
    VLLS Modes
    353
    
    Initialization
    353
- Chapter 12 Reset Control Module (RCM)
  
  354
  - Introduction
    354
  - Reset Memory Map and Register Descriptions
    354
    
    System Reset Status Register 0 (RCM_SRS0)
    355
    
    System Reset Status Register 1 (RCM_SRS1)
    356
    
    Reset Pin Filter Control Register (RCM_RPFC)
    357
    
    Reset Pin Filter Width Register (RCM_RPFW)
    358
- Chapter 13 Bit Manipulation Engine (BME)
  
  360
  - Introduction
    360
    
    Overview
    361
    
    Features
    361
    
    Modes of Operation
    362
  - Functional Description
    362
    
    BME Decorated Stores
    363
    
    BME Decorated Loads
    370
    
    Additional Details on Decorated Addresses and GPIO Accesses
    376
  - Memory Map and Register Definition
    362
  - Application Information
    377
- Chapter 14 Miscellaneous Control Module (MCM)
  
  380
  - Introduction
    380
    
    Features
    380
  - Memory Map/Register Descriptions
    380
    
    Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)
    381
    
    Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)
    382
    
    Platform Control Register (MCM_PLACR)
    382
    
    Compute Operation Control Register (MCM_CPO)
    385
- Chapter 15 Micro Trace Buffer (MTB)
  
  388
  - Introduction
    388
    
    Overview
    388
    
    Features
    391
    
    Modes of Operation
    392
  - External Signal Description
    392
  - Memory Map and Register Definition
    393
    
    MTB_RAM Memory Map
    393
    
    MTB_DWT Memory Map
    405
    
    System ROM Memory Map
    415
- Chapter 16 Crossbar Switch Lite (AXBS-Lite)
  
  420
  - Introduction
    420
    
    Features
    420
  - Functional Description
    421
    
    General Operation
    421
- Chapter 17 Peripheral Bridge (AIPS-Lite)
  
  422
  - Memory Map / Register Definition
    421
  - Introduction
    422
    
    Features
    422
    
    General Operation
    422
  - Memory Map/Register Definition
    423
    
    Master Privilege Register a (AIPS_MPRA)
    423
    
    Peripheral Access Control Register (Aips_Pacrn)
    425
    
    Peripheral Access Control Register (Aips_Pacrn)
    431
  - Functional Description
    435
    
    Access Support
    435
- Chapter 18 Direct Memory Access Multiplexer (DMAMUX)
  
  436
  - Introduction
    436
    
    Overview
    436
    
    Features
    437
    
    Modes of Operation
    437
  - External Signal Description
    438
  - Memory Map/Register Definition
    438
    
    Channel Configuration Register (Dmamuxx_Chcfgn)
    438
  - Functional Description
    439
    
    DMA Channels with Periodic Triggering Capability
    440
    
    DMA Channels with no Triggering Capability
    442
    
    Always-Enabled DMA Sources
    443
  - Initialization/Application Information
    444
    
    Reset
    444
    
    Enabling and Configuring Sources
    444
- Chapter 19 DMA Controller Module
  
  448
  - Introduction
    448
    
    Overview
    448
    
    Features
    449
  - DMA Transfer Overview
    450
  - Memory Map/Register Definition
    451
    
    Source Address Register (Dma_Sarn)
    452
    
    Destination Address Register (Dma_Darn)
    453
    
    DMA Status Register / Byte Count Register (Dma_Dsr_Bcrn)
    454
    
    DMA Control Register (Dma_Dcrn)
    456
  - Functional Description
    460
    
    Transfer Requests (Cycle-Steal and Continuous Modes)
    460
    
    Channel Initialization and Startup
    461
    
    Dual-Address Data Transfer Mode
    462
    
    Advanced Data Transfer Controls: Auto-Alignment
    463
    
    Termination
    464
- Chapter 20 Multipurpose Clock Generator (MCG)
  
  466
  - Introduction
    466
    
    Features
    466
    
    Modes of Operation
    468
  - External Signal Description
    468
  - Memory Map/Register Definition
    469
    
    MCG Control 1 Register (MCG_C1)
    469
    
    MCG Control 2 Register (MCG_C2)
    471
    
    MCG Control 3 Register (MCG_C3)
    472
    
    MCG Control 4 Register (MCG_C4)
    472
    
    MCG Control 5 Register (MCG_C5)
    474
    
    MCG Control 6 Register (MCG_C6)
    475
    
    MCG Status Register (MCG_S)
    476
    
    MCG Status and Control Register (MCG_SC)
    478
    
    MCG Auto Trim Compare Value High Register (MCG_ATCVH)
    479
    
    MCG Auto Trim Compare Value Low Register (MCG_ATCVL)
    479
    
    MCG Control 7 Register (MCG_C7)
    480
    
    MCG Control 8 Register (MCG_C8)
    480
    
    MCG Control 10 Register (MCG_C10)
    481
    
    MCG Control 12 Register (MCG_C12)
    481
    
    MCG Status 2 Register (MCG_S2)
    482
    
    MCG Test 3 Register (MCG_T3)
    482
  - Functional Description
    482
    
    MCG Mode State Diagram
    482
    
    Low-Power Bit Usage
    487
    
    MCG Internal Reference Clocks
    487
    
    External Reference Clock
    487
    
    MCG Fixed Frequency Clock
    488
    
    MCG PLL Clock
    488
    
    MCG Auto TRIM (ATM)
    489
  - Initialization / Application Information
    490
    
    MCG Module Initialization Sequence
    490
    
    Using a 32.768 Khz Reference
    492
    
    MCG Mode Switching
    493
- Chapter 21 Oscillator (OSC)
  
  502
  - Features and Modes
    502
  - Introduction
    502
  - Block Diagram
    503
  - External Crystal / Resonator Connections
    503
  - OSC Signal Descriptions
    503
  - External Clock Connections
    505
  - Memory Map/Register Definitions
    505
    
    OSC Memory Map/Register Definition
    506
  - Functional Description
    507
    
    OSC Module States
    507
    
    OSC Module Modes
    509
    
    Counter
    511
    
    Reference Clock Pin Requirements
    511
  - Reset
    511
  - Interrupts
    512
- Chapter 22 Flash Memory Controller (FMC)
  
  514
  - Low Power Modes Operation
    512
  - Introduction
    514
    
    Overview
    514
    
    Features
    514
  - External Signal Description
    515
  - Functional Description
    515
- Chapter 23 Flash Memory Module (FTFA)
  
  518
  - Memory Map and Register Descriptions
    515
  - Modes of Operation
    515
  - Introduction
    518
    
    Features
    519
    
    Block Diagram
    519
    
    Glossary
    520
  - External Signal Description
    521
  - Memory Map and Registers
    521
    
    Flash Configuration Field Description
    521
    
    Program Flash IFR Map
    522
    
    Register Descriptions
    523
  - Functional Description
    532
    
    Flash Protection
    532
    
    Interrupts
    533
    
    Flash Operation in Low-Power Modes
    534
    
    Functional Modes of Operation
    534
    
    Flash Reads and Ignored Writes
    534
    
    Read While Write (RWW)
    535
    
    Flash Program and Erase
    535
    
    Flash Command Operations
    535
    
    Margin Read Commands
    540
    
    Flash Command Description
    541
    
    Security
    555
    
    Reset Sequence
    557
- Chapter 24 Analog-To-Digital Converter (ADC)
  
  558
- Chapter 25 Comparator (CMP)
  
  612
  - Introduction
    612
    
    CMP Features
    612
    
    6-Bit DAC Key Features
    613
    
    ANMUX Key Features
    613
    
    CMP, DAC and ANMUX Diagram
    614
    
    CMP Block Diagram
    615
  - Memory Map/Register Definitions
    616
    
    CMP Control Register 0 (Cmpx_Cr0)
    617
    
    CMP Control Register 1 (Cmpx_Cr1)
    618
    
    CMP Filter Period Register (Cmpx_Fpr)
    619
    
    CMP Status and Control Register (Cmpx_Scr)
    620
    
    DAC Control Register (Cmpx_Daccr)
    621
    
    MUX Control Register (Cmpx_Muxcr)
    621
  - Functional Description
    622
    
    CMP Functional Modes
    623
    
    Power Modes
    626
    
    Startup and Operation
    627
    
    Low-Pass Filter
    628
  - CMP Asynchronous DMA Support
    630
  - CMP Interrupts
    630
  - DMA Support
    630
  - DAC Functional Description
    631
    
    Voltage Reference Source Select
    631
  - Digital-To-Analog Converter
    631
  - CMP Trigger Mode
    632
- Chapter 26 12-Bit Digital-To-Analog Converter (DAC)
  
  634
  - DAC Clocks
    632
  - DAC Interrupts
    632
  - DAC Resets
    632
  - Block Diagram
    634
  - Features
    634
  - Introduction
    634
  - Memory Map/Register Definition
    635
    
    DAC Data Low Register (Dacx_Datnl)
    636
    
    DAC Data High Register (Dacx_Datnh)
    636
    
    DAC Status Register (Dacx_Sr)
    637
    
    DAC Control Register (Dacx_C0)
    638
    
    DAC Control Register 1 (Dacx_C1)
    639
    
    DAC Control Register 2 (Dacx_C2)
    640
  - Functional Description
    640
    
    DAC Data Buffer Operation
    640
    
    DMA Operation
    641
    
    Resets
    642
    
    Low-Power Mode Operation
    642
- Chapter 27 Timer/Pwm Module (TPM)
  
  644
  - Introduction
    644
    
    TPM Philosophy
    644
    
    Features
    644
    
    Modes of Operation
    645
    
    Block Diagram
    646
  - TPM Signal Descriptions
    646
    
    TPM_EXTCLK - TPM External Clock
    647
    
    Tpm_Chn - TPM Channel (N) I/O Pin
    647
  - Memory Map and Register Definition
    647
    
    Status and Control (Tpmx_Sc)
    649
    
    Counter (Tpmx_Cnt)
    651
    
    Modulo (Tpmx_Mod)
    651
    
    Channel (N) Status and Control (Tpmx_Cnsc)
    652
    
    Channel (N) Value (Tpmx_Cnv)
    654
    
    Capture and Compare Status (Tpmx_Status)
    655
    
    Configuration (Tpmx_Conf)
    657
  - Functional Description
    658
    
    Clock Domains
    659
    
    Prescaler
    660
    
    Counter
    660
    
    Input Capture Mode
    663
    
    Output Compare Mode
    663
    
    Edge-Aligned PWM (EPWM) Mode
    665
    
    Center-Aligned PWM (CPWM) Mode
    666
    
    Registers Updated from Write Buffers
    668
    
    Dma
    669
    
    Output Triggers
    669
    
    Reset Overview
    670
    
    TPM Interrupts
    670
- Chapter 28 Periodic Interrupt Timer (PIT)
  
  672
  - Introduction
    672
    
    Block Diagram
    672
    
    Features
    673
  - Signal Description
    673
  - Memory Map/Register Description
    674
    
    PIT Module Control Register (PIT_MCR)
    674
    
    PIT Upper Lifetime Timer Register (PIT_LTMR64H)
    675
    
    PIT Lower Lifetime Timer Register (PIT_LTMR64L)
    676
    
    Timer Load Value Register (Pit_Ldvaln)
    676
    
    Current Timer Value Register (Pit_Cvaln)
    677
    
    Timer Control Register (Pit_Tctrln)
    677
    
    Timer Flag Register (Pit_Tflgn)
    678
  - Functional Description
    679
    
    General Operation
    679
    
    Interrupts
    681
    
    Chained Timers
    681
  - Initialization and Application Information
    681
  - Example Configuration for Chained Timers
    682
  - Example Configuration for the Lifetime Timer
    683
- Chapter 29 Low-Power Timer (LPTMR)
  
  684
  - Introduction
    684
    
    Features
    684
    
    Modes of Operation
    684
  - LPTMR Signal Descriptions
    685
    
    Detailed Signal Descriptions
    685
  - Memory Map and Register Definition
    685
    
    Low Power Timer Control Status Register (Lptmrx_Csr)
    686
    
    Low Power Timer Prescale Register (Lptmrx_Psr)
    687
    
    Low Power Timer Compare Register (Lptmrx_Cmr)
    689
    
    Low Power Timer Counter Register (Lptmrx_Cnr)
    689
  - Functional Description
    690
    
    LPTMR Power and Reset
    690
    
    LPTMR Clocking
    690
    
    LPTMR Prescaler/Glitch Filter
    690
    
    LPTMR Compare
    692
    
    LPTMR Counter
    692
    
    LPTMR Hardware Trigger
    693
    
    LPTMR Interrupt
    693
- Chapter 30 Real Time Clock (RTC)
  
  694
  - Introduction
    694
    
    Features
    694
    
    Modes of Operation
    694
    
    RTC Signal Descriptions
    695
  - Register Definition
    695
    
    RTC Time Seconds Register (RTC_TSR)
    696
    
    RTC Time Prescaler Register (RTC_TPR)
    696
    
    RTC Time Alarm Register (RTC_TAR)
    697
    
    RTC Time Compensation Register (RTC_TCR)
    697
    
    RTC Control Register (RTC_CR)
    698
    
    RTC Status Register (RTC_SR)
    700
    
    RTC Lock Register (RTC_LR)
    701
    
    RTC Interrupt Enable Register (RTC_IER)
    702
  - Functional Description
    703
    
    Power, Clocking, and Reset
    703
    
    Time Counter
    704
    
    Compensation
    705
    
    Time Alarm
    706
    
    Update Mode
    706
    
    Register Lock
    706
    
    Interrupt
    706
- Chapter 31 Serial Peripheral Interface (SPI)
  
  708
  - Introduction
    708
    
    Features
    708
    
    Modes of Operation
    709
    
    Block Diagrams
    710
  - External Signal Description
    712
    
    SPSCK - SPI Serial Clock
    713
    
    MOSI - Master Data Out, Slave Data in
    713
    
    MISO - Master Data In, Slave Data out
    713
    
    SS - Slave Select
    713
  - Memory Map/Register Definition
    714
    
    SPI Status Register (Spix_S)
    714
    
    SPI Baud Rate Register (Spix_Br)
    718
    
    SPI Control Register 2 (Spix_C2)
    719
    
    SPI Control Register 1 (Spix_C1)
    720
    
    SPI Match Register Low (Spix_Ml)
    722
    
    SPI Match Register High (Spix_Mh)
    723
    
    SPI Data Register Low (Spix_Dl)
    723
    
    SPI Data Register High (Spix_Dh)
    724
    
    SPI Clear Interrupt Register (Spix_Ci)
    724
    
    SPI Control Register 3 (Spix_C3)
    726
  - Functional Description
    727
    
    General
    727
    
    Master Mode
    728
    
    Slave Mode
    729
    
    SPI FIFO Mode
    731
    
    SPI Transmission by DMA
    732
    
    Data Transmission Length
    734
    
    SPI Clock Formats
    735
    
    SPI Baud Rate Generation
    738
    
    Special Features
    738
    
    Error Conditions
    740
    
    Low-Power Mode Options
    741
    
    Reset
    742
    
    Interrupts
    743
  - Initialization/Application Information
    745
    
    Initialization Sequence
    745
    
    Pseudo-Code Example
    746
- Chapter 32 Universal Asynchronous Receiver/Transmitter (UART0)
  
  750
  - Introduction
    750
    
    Features
    750
    
    Modes of Operation
    751
    
    Block Diagram
    751
  - Register Definition
    753
    
    UART Baud Rate Register High (Uartx_Bdh)
    754
    
    UART Baud Rate Register Low (Uartx_Bdl)
    755
    
    UART Control Register 1 (Uartx_C1)
    755
    
    UART Control Register 2 (Uartx_C2)
    757
    
    UART Status Register 1 (Uartx_S1)
    758
    
    UART Status Register 2 (Uartx_S2)
    760
    
    UART Control Register 3 (Uartx_C3)
    762
    
    UART Data Register (Uartx_D)
    763
    
    UART Match Address Registers 1 (Uartx_Ma1)
    764
    
    UART Match Address Registers 2 (Uartx_Ma2)
    765
    
    UART Control Register 4 (Uartx_C4)
    765
    
    UART Control Register 5 (Uartx_C5)
    766
  - Functional Description
    767
    
    Baud Rate Generation
    767
    
    Transmitter Functional Description
    768
    
    Receiver Functional Description
    769
    
    Additional UART Functions
    773
    
    Interrupts and Status Flags
    774
- Chapter 33 Universal Asynchronous Receiver/Transmitter (UART1 and UART2)
  
  776
  - Introduction
    776
    
    Features
    776
    
    Modes of Operation
    777
    
    Block Diagram
    777
  - Register Definition
    779
    
    UART Baud Rate Register: High (Uartx_Bdh)
    780
    
    UART Baud Rate Register: Low (Uartx_Bdl)
    781
    
    UART Control Register 1 (Uartx_C1)
    782
    
    UART Control Register 2 (Uartx_C2)
    783
    
    UART Status Register 1 (Uartx_S1)
    785
    
    UART Status Register 2 (Uartx_S2)
    786
    
    UART Control Register 3 (Uartx_C3)
    788
    
    UART Data Register (Uartx_D)
    789
    
    UART Control Register 4 (Uartx_C4)
    790
  - UART Signal Descriptions
    779
    
    Detailed Signal Descriptions
    779
  - Functional Description
    791
    
    Baud Rate Generation
    791
    
    Transmitter Functional Description
    792
    
    Receiver Functional Description
    794
    
    Interrupts and Status Flags
    796
    
    Baud Rate Tolerance
    798
    
    DMA Operation
    800
    
    Additional UART Functions
    801
- Chapter 34 General-Purpose Input/Output (GPIO)
  
  804
  - Introduction
    804
    
    Features
    804
    
    Modes of Operation
    805
    
    GPIO Signal Descriptions
    805
  - Memory Map and Register Definition
    806
    
    Port Data Output Register (Gpiox_Pdor)
    808
    
    Port Set Output Register (Gpiox_Psor)
    808
    
    Port Clear Output Register (Gpiox_Pcor)
    809
    
    Port Toggle Output Register (Gpiox_Ptor)
    809
    
    Port Data Input Register (Gpiox_Pdir)
    810
    
    Port Data Direction Register (Gpiox_Pddr)
    810
  - FGPIO Memory Map and Register Definition
    811
    
    Port Data Output Register (Fgpiox_Pdor)
    813
    
    Port Set Output Register (Fgpiox_Psor)
    813
    
    Port Clear Output Register (Fgpiox_Pcor)
    814
    
    Port Toggle Output Register (Fgpiox_Ptor)
    814
    
    Port Data Input Register (Fgpiox_Pdir)
    815
    
    Port Data Direction Register (Fgpiox_Pddr)
    815
  - Functional Description
    816
    
    General-Purpose Input
    816
    
    General-Purpose Output
    816
    
    Ioport
    816
    
    Touch Sensing Input (TSI)
    818
  - Introduction
    818
    
    Features
    818
    
    Modes of Operation
    819
    
    Block Diagram
    819
  - External Signal Description
    820
    
    Tsi[15:0]
    820
  - Register Definition
    820
    
    TSI General Control and Status Register (Tsix_Gencs)
    820
    
    TSI DATA Register (Tsix_Data)
    825
    
    TSI Threshold Register (Tsix_Tshd)
    826
  - Functional Description
    826
    
    Capacitance Measurement
    827
    
    TSI Measurement Result
    830
    
    Enable TSI Module
    830
    
    Software and Hardware Trigger
    830
    
    Scan Times
    830
    
    Clock Setting
    831
    
    Reference Voltage
    831
    
    Current Source
    831
    
    End of Scan
    832
    
    Out-Of-Range Interrupt
    832
    
    Wake up MCU from Low Power Modes
    833
    
    DMA Function Support
    833
    
    Noise Detection Mode
    833
- Chapter 36 Inter-Integrated Circuit (I2C)
  
  844
  - Introduction
    844
    
    Features
    844
    
    Modes of Operation
    845
    
    Block Diagram
    845
  - I2C Signal Descriptions
    846
  - Memory Map/Register Definition
    847
    
    I2C Address Register 1 (I2Cx_A1)
    848
    
    I2C Frequency Divider Register (I2Cx_F)
    848
    
    I2C Control Register 1 (I2Cx_C1)
    849
    
    I2C Status Register (I2Cx_S)
    851
    
    I2C Data I/O Register (I2Cx_D)
    853
    
    I2C Control Register 2 (I2Cx_C2)
    853
    
    I2C Programmable Input Glitch Filter Register (I2Cx_Flt)
    854
    
    I2C Range Address Register (I2Cx_Ra)
    856
    
    I2C Smbus Control and Status Register (I2Cx_Smb)
    856
    
    I2C Address Register 2 (I2Cx_A2)
    858
    
    I2C SCL Low Timeout Register High (I2Cx_Slth)
    858
    
    I2C SCL Low Timeout Register Low (I2Cx_Sltl)
    859
  - Functional Description
    859
    
    I2C Protocol
    859
    
    10-Bit Address
    864
    
    Address Matching
    866
    
    System Management Bus Specification
    867
    
    Resets
    869
    
    Interrupts
    870
    
    Programmable Input Glitch Filter
    872
    
    Address Matching Wake-Up
    872
    
    DMA Support
    873
  - Initialization/Application Information
    873

NXP Semiconductors Categories

Motherboard Microcontrollers Computer Hardware Control Unit Controller

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NXP Semiconductors MKW01Z128 Manuals

NXP Semiconductors MKW01Z128 Reference Manual (884 pages)

Table of Contents

Mkw01Z128

Chapter 1 MKW01Z128 Introduction and Chip Configuration

Chapter 2 MKW01Z128 Pins and Connections

Chapter 3 Signal Multiplexing and Signal Descriptions

Chapter 4 System Considerations

Chapter 5 Sub 1 Ghz Transceiver Architecture Description

Chapter 6 Transceiver Operating Modes

Chapter 7 Transceiver Digital Control and Communications

Chapter 8 MKW01Z128 Transceiver - MCU SPI Interface

Appendix A

Table of Contents

Chapter 9 System Mode Controller (SMC)

Chapter 11 Low-Leakage Wakeup Unit (LLWU)

Chapter 12 Reset Control Module (RCM)

Chapter 13 Bit Manipulation Engine (BME)

Chapter 14 Miscellaneous Control Module (MCM)

Chapter 15 Micro Trace Buffer (MTB)

Chapter 16 Crossbar Switch Lite (AXBS-Lite)

Chapter 17 Peripheral Bridge (AIPS-Lite)

Chapter 18 Direct Memory Access Multiplexer (DMAMUX)

Chapter 19 DMA Controller Module

Chapter 20 Multipurpose Clock Generator (MCG)

Chapter 21 Oscillator (OSC)

Chapter 22 Flash Memory Controller (FMC)

Chapter 23 Flash Memory Module (FTFA)

Chapter 24 Analog-To-Digital Converter (ADC)

Chapter 25 Comparator (CMP)

Chapter 26 12-Bit Digital-To-Analog Converter (DAC)

Chapter 27 Timer/Pwm Module (TPM)

Chapter 28 Periodic Interrupt Timer (PIT)

Chapter 29 Low-Power Timer (LPTMR)

Chapter 30 Real Time Clock (RTC)

Chapter 31 Serial Peripheral Interface (SPI)

Chapter 32 Universal Asynchronous Receiver/Transmitter (UART0)

Chapter 33 Universal Asynchronous Receiver/Transmitter (UART1 and UART2)

Chapter 34 General-Purpose Input/Output (GPIO)

Chapter 36 Inter-Integrated Circuit (I2C)

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