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Summary of Contents for Aaeon BOXER-6951-A01-1010
- Page 1 BOXER-6951-A01-1010 32.1840.921-00 Fanless Embedded Box PC User’s Manual 1 Last Updated: March 17, 2016...
- Page 2 The material in this document is for product information only and is subject to change without notice. While reasonable efforts have been made in the preparation of this document to assure its accuracy, AAEON assumes no liabilities resulting from errors or omissions in this document, or from the use of the information contained herein.
- Page 3 Acknowledgement All other products’ name or trademarks are properties of their respective owners. Microsoft Windows is a registered trademark of Microsoft Corp. Intel, Pentium, Celeron, and Xeon are registered trademarks of Intel Corporation Core, Atom are trademarks of Intel Corporation ...
- Page 4 Packing List Before setting up your product, please make sure the following items have been shipped: Item Quantity BOXER-6951-A01-1010/ 32.1840.921-00 Wallmount bracket Screw Package RAM Thermal Pad Phoenix power connector Product DVD with User’s Manual (in pdf) and drivers ...
- Page 5 (if any), its specifications, dimensions, jumper/connector settings/definitions, and driver installation instructions (if any), to facilitate users in setting up their product. Users may refer to the AAEON.com for the latest version of this document. Preface...
- Page 6 All cautions and warnings on the device should be noted. All cables and adapters supplied by AAEON are certified and in accordance with the material safety laws and regulations of the country of sale. Do not use any cables or adapters not supplied by AAEON to prevent system malfunction or fires.
- Page 7 As most electronic components are sensitive to static electrical charge, be sure to ground yourself to prevent static charge when installing the internal components. Use a grounding wrist strap and contain all electronic components in any static-shielded containers. If any of the following situations arises, please the contact our service personnel: Damaged power cord or plug Liquid intrusion to the device iii.
- Page 8 FCC Statement This device complies with Part 15 FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received including interference that may cause undesired operation. Caution: There is a danger of explosion if the battery is incorrectly replaced.
- Page 9 China RoHS Requirements (CN) 产品中有毒有害物质或元素名称及含量 AAEON Embedded Box PC/ Industrial System 有毒有害物质或元素 部件名称 铅 汞 镉 六价铬 多溴联苯 多溴二苯醚 (Pb) (Hg) (Cd) (Cr(VI)) (PBB) (PBDE) 印刷电路板 ○ ○ ○ ○ ○ ○ 及其电子组件 外部信号 ○ ○ ○ ○ ○ ○...
- Page 10 China RoHS Requirement (EN) Poisonous or Hazardous Substances or Elements in Products AAEON Embedded Box PC/ Industrial System Poisonous or Hazardous Substances or Elements Hexavalent Polybrominated Polybrominated Component Lead Mercury Cadmium Chromium Biphenyls Diphenyl Ethers (Pb) (Hg) (Cd) (Cr(VI)) (PBB) (PBDE) PCB &...
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Page 11: Table Of Contents
Table of Contents Chapter 1 - Product Specifications ..................1 Specifications ......................2 Chapter 2 – Hardware Information ..................4 Dimensions and I/O Ports ..................5 Jumper Settings ....................... 8 List of Jumpers ....................... 11 2.3.1 Clear CMOS (JP1) ................. 12 2.3.2 Auto Power Button (JP3) ............. - Page 12 Wallmount Kit Installation ..................30 Chapter 3 - AMI BIOS Setup ....................31 System Test and Initialization ................32 AMI BIOS Setup ..................... 33 Setup Submenu: Main ..................34 Setup Submenu: Advanced ................35 3.4.1 Advanced: ACPI Settings ............. 36 3.4.2 Advanced: RTC Wake Settings ...........
- Page 13 Appendix A - Watchdog Timer Programming..............62 Watchdog Timer Initial Program ................ 63 Appendix B - I/O Information ....................68 I/O Address Map ....................69 Memory Address Map ..................71 IRQ Mapping Chart ....................72 DMA Channel Assignments ................75 Appendix C –...
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Page 14: Chapter 1 - Product Specifications
Chapter 1 Chapter 1 - Product Specifications... -
Page 15: Specifications
Specifications System ® ® Intel Celeron 1020E Processor DDR3 SO-DIMM x 2, up to 16 GB (4 GB System Memory preinstalled) ® Intel QM77 Express Chipset 2.5" SATA HDD/SSD drive bay x 1 Storage DB-9 x 1 for RS-232/422/485 Rear I/O Panel ... - Page 16 Linux 13.1 (32/64-bit, Linux kernel 3.11.x) Mechanical Rugged aluminum chassis Construction Wall-mounted Mounting Desktop-mounted 214 x 104.3 x 237.8 mm (8.43 x 4.11 x 9.36”) Dimension (W x H x D) 4.2 kg (9.26 lb) Net Weight ...
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Page 17: Chapter 2 - Hardware Information
Chapter 2 Chapter 2 – Hardware Information... -
Page 18: Dimensions And I/O Ports
Dimensions and I/O Ports Chassis Label A : Label B Label B : Unit: mm Label B Label A Label B Label B Label B Label A Label A Label A Chapter 2 – Hardware Information... - Page 19 Label B : Unit: mm PCI1 PCI2 Label A I/O Port List Label Port DC-Out (24V) DC-In (24V) LAN Port 1 COM2 Port (RS-232/422/485) COM3 Port (RS-232) Video Out (VGA) Chapter 2 – Hardware Information...
- Page 20 LAN Port 2 COM1 Port (RS-232) COM4 Port (RS-232) USB 2.0 connector for keyboard/ mouse Chapter 2 – Hardware Information...
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Page 21: Jumper Settings
Jumper Settings Chapter 2 – Hardware Information... - Page 22 Normal (Default) Clear CMOS Disable Enable (Default) Chapter 2 – Hardware Information...
- Page 23 RS232 (Default) RS422 PS485 Chapter 2 – Hardware Information...
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Page 24: List Of Jumpers
List of Jumpers Please refer to the table below for all of the system’s jumpers that you can configure for your application Label Function Clear CMOS AT/ATX mode select RS-232/ 422/ 485 selection Chapter 2 – Hardware Information... -
Page 25: Clear Cmos (Jp1)
2.3.1 Clear CMOS (JP1) 1 2 3 1 2 3 Normal (Default) Clear CMOS 2.3.2 Auto Power Button (JP3) 1 2 3 1 2 3 VR Mode (Default) PWM Mode 2.3.3 COM2 RS232/ RS422/ RS485 selection (JP8) Function 1-2/ 3-4/ 5-6 RS232 (Default) RS422 PS485... -
Page 26: List Of Connectors
List of Connectors Please refer to the table below for all of the system’s connectors that you can configure for your application Label Function SPI ROM Connector (for debug) CN23 LPC Debug port CN29 PCIe slot connector CN34A COM1 connector (RS232) CN34B COM2 connector (RS232/422/485) CN35... -
Page 27: Spi Rom Connector (For Debug) (Cn3)
2.4.1 SPI ROM connector (for debug) (CN3) Signal Signal +3.3V SPI_CS0 SPI_CLK SPI_SO SPI_SI 2.4.2 LPC Port (CN23) LAD0 LAD1 LAD2 LAD3 +3.3V LFRAME# LRESET# LCLK LDRQ0 LDRQ1 SERIRQ Pin Name Signal Type Signal Level LAD0 +3.3V LAD1 +3.3V LAD2 +3.3V LAD3 +3.3V... -
Page 28: Pcie Slot Connector (Cn29)
SERIRQ +3.3V 2.4.3 PCIe Slot Connector (CN29) Signal Signal +12V +12V +12V +12V +12V SMB_CLK SMB_DATA +3.3V +3.3V +3.3V +3.3VAUX RESET PCIE_WAKE CLK_PCIE_SLOT_P1 CLK_PCIE_SLOT_N1 PCIE_TXP4 PCIE_TXN4 PCIE_RXP4 PCIE_RXN4 PRSNT Chapter 2 – Hardware Information... -
Page 29: Com2 Connector (Rs232/422/485) (Cn34B)
2.4.4 COM2 connector (RS232/422/485) (CN34B) RS-232 Signal Signal RS-422 Signal Signal TXD- RXD+ TXD+ RXD- RS-485 Signal Signal Chapter 2 – Hardware Information... -
Page 30: Dual Stack Usb Connector (3.0/ 2.0) (Cn35)
2.4.5 Dual stack USB Connector (3.0/ 2.0) (CN35) Signal Signal VCC_USB VCC_USB USB_PN2 (2.0) USB_PN3 (2.0) USB_PP2 (2.0) USB_PP3 (2.0) USB_SSRX2N (3.0) USB_SSRX3N (3.0) USB_SSRX2P (3.0) USB_SSRX3P (3.0) USB_SSTX2N (3.0) USB_SSTX3N (3.0) USB_SSTX2P (3.0) USB_SSTX3P (3.0) 2.4.6 Dual stack USB Connector (3.0/ 2.0) (CN36) Signal Signal VCC_USB... -
Page 31: Lan1 Connector (Cn42)
USB_SSTX0N (3.0) USB_SSTX1N (3.0) USB_SSTX0P (3.0) USB_SSTX1P (3.0) 2.4.7 LAN1 Connector (CN42) Signal Signal MDI0+ MDI0- MDI1+ MDI1- MDI2+ MDI2- MDI3+ MDI3- 2.4.8 LAN2 Connector (CN43) Signal Signal MDI0+ MDI0- MDI1+ MDI1- MDI2+ MDI2- MDI3+ MDI3- Chapter 2 – Hardware Information... -
Page 32: Usb 2.0 Connector (Cn44)
MDI0+ MDI0- 2.4.9 USB 2.0 connector (CN44) Signal Signal VCC_USB USB_PN5 USB_PP5 2.4.10 DC-in (CN45) Signal Signal 24 V 2.4.11 MiniCard Connector w/ onboard SIM (CN46) Signal Signal PCIE_WAKE# +V3.3A +1.5V PCIE_CLK_REQ# UIM_PWR UIM_DATA PCIE_REF_CLK- UIM_CLK PCIE_REF_CLK+ UIM_RST UIM_VPP W_DISABLE# PCIE_RST# Chapter 2 –... -
Page 33: Vga Connector (Cn47)
PCIE_RX- +V3.3A PCIE_RX+ +1.5V SMB_CLK PCIE_TX- SMB_DATA PCIE_TX+ USB_D- USB_D+ +V3.3A +V3.3A +1.5V +V3.3A 2.4.12 VGA Connector (CN47) Signal Signal CRT_RED CRT_GREEN CRT_BLUE Chapter 2 – Hardware Information... -
Page 34: Sata Power Connector (+12V/ +5V) (Pwr1)
CRT_PLUG DDC_DATA CRT_HSYNC CRT_VSYNC DDC_CLK 2.4.13 SATA Power connector (+12V/ +5V) (PWR1) Pin Name Signal Type Signal Level +12V 2.4.14 SATA Connector (SATA1) Pin 1 Pin 7 Pin Name Signal Type Signal Level SATA_TX+ DIFF SATA_TX- DIFF SATA_RX- DIFF SATA_RX+ DIFF Chapter 2 –... -
Page 35: Hard Disk Drive Installation
Hard Disk Drive Installation Remove the highlighted screws to access the device’s interior PCI1 PCI2 Chapter 2 – Hardware Information... - Page 36 Attach 4 screws onto the HDD with dampers Black Damper Black Damper Chapter 2 – Hardware Information...
- Page 37 Place the assembled HDD onto the base of the device and attach the damper brackets with screws. Attach the SATA cables. HDD DISK SATA Power W/LOCK I/O Board Side Chapter 2 – Hardware Information...
- Page 38 Re-secure the highlighted screws to close the device PCI1 PCI2 Chapter 2 – Hardware Information...
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Page 39: Pci Card Installation
PCI Card Installation Remove the highlighted screw to access the device’s interior PCI1 PCI2 Chapter 2 – Hardware Information... - Page 40 Remove the PCI card cover and keep the removed screw for use later Slot the card into the PCI slot and secure with the screw removed in step 2 Chapter 2 – Hardware Information...
- Page 41 Slide the mortise to secure the card into position Chapter 2 – Hardware Information...
- Page 42 Re-secure the highlighted screws to close the device PCI1 PCI2 Chapter 2 – Hardware Information...
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Page 43: Wallmount Kit Installation
Wallmount Kit Installation To install the wallmount kit, simple secure two brackets to the bottom of the device as shown in the diagram below. Chapter 2 – Hardware Information... -
Page 44: Chapter 3 - Ami Bios Setup
Chapter 3 Chapter 3 - AMI BIOS Setup... -
Page 45: System Test And Initialization
System Test and Initialization The system uses certain routines to perform testing and initialization. If an error, fatal or non-fatal, is encountered, a few short beeps or an error message will be outputted. The board can usually continue the boot up sequence with non-fatal errors. The system configuration verification routines check the current system configuration against the values stored in the CMOS memory. -
Page 46: Ami Bios Setup
AMI BIOS Setup The AMI BIOS ROM has a pre-installed Setup program that allows users to modify basic system configurations, which is stored in the battery-backed CMOS RAM and BIOS NVRAM so that the information is retained when the power is turned off. To enter BIOS Setup, press <Del>... -
Page 47: Setup Submenu: Main
Setup Submenu: Main Chapter 3 – AMI BIOS Setup... -
Page 48: Setup Submenu: Advanced
Setup Submenu: Advanced Chapter 3 – AMI BIOS Setup... -
Page 49: Advanced: Acpi Settings
3.4.1 Advanced: ACPI Settings Options summary: ACPI Sleep State Suspend Disable S1 only(CPU Stop Clock) Optimal Default, Failsafe Default S3 only(Suspend to RAM) Select ACPI sleep state the system will enter when the SUSPEND button is pressed. Chapter 3 – AMI BIOS Setup... -
Page 50: Advanced: Rtc Wake Settings
3.4.2 Advanced: RTC Wake Settings Options summary: Wake system with Disabled Optimal Default, Failsafe Default Fixed Time Enable Enable or disable System wake on alarm event. When enabled, System will wake on the hr::min::sec specified Wake system with Disabled Optimal Default, Failsafe Default Dynamic Time Enable Enable or disable System wake on alarm event. -
Page 51: Advanced: Cpu Configuration
3.4.3 Advanced: CPU Configuration Options summary: Hyper-Threading Disabled Optimal Default, Failsafe Default When enabled, a VMM can utilize the additional hardware capabilities provided be Vanderpool Technology Chapter 3 – AMI BIOS Setup... -
Page 52: Advanced: Cpu Configuration
3.4.4 Advanced: CPU Configuration Options summary: Hyper-Threading Disabled Optimal Default, Failsafe Default When enabled, a VMM can utilize the additional hardware capabilities provided be Vanderpool Technology Chapter 3 – AMI BIOS Setup... -
Page 53: Advanced: Amt Configuration
3.4.5 Advanced: AMT Configuration Options summary: Enable Optimal Default, Failsafe Default SATA Controllers Disable En/Disable SATA Controller Optimal Default, Failsafe Default SATA Mode Selection AHCI Determines how SATA controller(s) operate. Chapter 3 – AMI BIOS Setup... -
Page 54: Advanced: Intel Txt (Lt) Configuration
3.4.6 Advanced: Intel TXT (LT) Configuration Options summary: Secure Mode Extensions Disable Optimal Default, Failsafe Default (SMX) Intel TXT(LT) Support Disable Optimal Default, Failsafe Default Chapter 3 – AMI BIOS Setup... -
Page 55: Advanced: Usb Configuration
3.4.7 Advanced: USB Configuration Options summary: Enable Optimal Default, Failsafe Default Legacy USB Support Disable Auto Enables Legacy USB support. AUTO option disables legacy support if no USB devices are connected. DISABLE option will keep USB devices available only for EFI applications. Auto Optimal Default, Failsafe Default xHCI Mode... -
Page 56: Advanced: Super Io Configuration
3.4.8 Advanced: Super IO Configuration Chapter 3 – AMI BIOS Setup... -
Page 57: Super Io Configuration: Serial Port 1 Configuration
3.4.8.1 Super IO Configuration: Serial Port 1 Configuration Options summary: Disabled Serial Port Enabled Optimal Default, Failsafe Default Enable or Disable Serial Port (COM) Auto Optimal Default, Failsafe Default IO=3F8h; IRQ=4 IO=3F8h; IRQ=3,4 Change Settings IO=2F8h; IRQ=3,4 IO=3E8h; IRQ=3,4 IO=2E8h; IRQ=3,4 Select an optimal setting for Super IO device. -
Page 58: Super Io Configuration: Serial Port 2 Configuration
3.4.8.2 Super IO Configuration: Serial Port 2 Configuration Options summary: Disabled Serial Port Enabled Optimal Default, Failsafe Default Enable or Disable Serial Port (COM) Auto Optimal Default, Failsafe Default IO=2F8h; IRQ=3 IO=3F8h; IRQ=3,4 Change Settings IO=2F8h; IRQ=3,4 IO=3E8h; IRQ=3,4 IO=2E8h; IRQ=3,4 Select an optimal setting for Super IO device. -
Page 59: Super Io Configuration: Serial Port 3 Configuration
3.4.8.3 Super IO Configuration: Serial Port 3 Configuration Options summary: Disabled Serial Port Enabled Optimal Default, Failsafe Default Enable or Disable Serial Port (COM) Auto Optimal Default, Failsafe Default IO=2E8h; IRQ=5 Change Settings IO=3E8h; IRQ=5 IO=2D0h; IRQ=5 IO=2D8h; IRQ=5 Select an optimal setting for Super IO device. Chapter 3 –... -
Page 60: Super Io Configuration: Serial Port 4 Configuration
3.4.8.4 Super IO Configuration: Serial Port 4 Configuration Options summary: Disabled Serial Port Enabled Optimal Default, Failsafe Default Enable or Disable Serial Port (COM) Auto Optimal Default, Failsafe Default IO=3E8h; IRQ=5 Change Settings IO=2E8h; IRQ=5 IO=2D0h; IRQ=5 IO=2D8h; IRQ=5 Select an optimal setting for Super IO device. Chapter 3 –... -
Page 61: Super Io Configuration: Power Saving Function
3.4.8.5 Super IO Configuration: Power Saving Function Options summary: Disabled Optimal Default, Failsafe Default Power Saving Function Enabled Enable to reduce power consumption in system off state When Enabled, only power button can power-up system. Chapter 3 – AMI BIOS Setup... -
Page 62: Advanced: Hardware Monitor
3.4.9 Advanced: Hardware Monitor Chapter 3 – AMI BIOS Setup... -
Page 63: Setup Submenu: Chipset
Setup submenu: Chipset Chapter 3 – AMI BIOS Setup... -
Page 64: Chipset: Pch-Io Configuration
3.5.1 Chipset: PCH-IO Configuration Options summary: Power Mode ATX Type Optimal Default, Failsafe Default AT Type Select Power Supply Mode. Restore AC power Power Off Loss Power On Optimal Default, Failsafe Default Last State Select AC power state when power is re-applied after a power failure. Wake on LAN Enabled Optimal Default, Failsafe Default... - Page 65 Gen2 Optimal Default, Failsafe Default Select Mini PCI Express port speed. PCIe Speed Gen1 Optimal Default, Failsafe Default Gen2 Select PCI Express port speed. Chapter 3 – AMI BIOS Setup...
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Page 66: Chipset: System Agent (Sa) Configuration
3.5.2 Chipset: System Agent (SA) Configuration Chapter 3 – AMI BIOS Setup... -
Page 67: Setup Submenu: Boot
Setup submenu: Boot Options summary: Quiet Boot Disabled Enabled Default Enables or disables Quiet Boot option Launch I211 PXE OpROM Disabled Default Enabled Enable or Disable Legacy Boot Option for I211 Chapter 3 – AMI BIOS Setup... -
Page 68: Setup Submenu: Security
Setup submenu: Security Change User/Administrator Password You can set a User Password once an Administrator Password is set. The password will be required during boot up, or when the user enters the Setup utility. Please Note that a User Password does not provide access to many of the features in the Setup utility. Select the password you wish to set, press Enter to open a dialog box to enter your password (you can enter no more than six letters or numbers). -
Page 69: Setup Submenu: Save & Exit
Setup submenu: Save & Exit Chapter 3 – AMI BIOS Setup... -
Page 70: Chapter 4 - Drivers Installation
Chapter 4 Chapter 4 – Drivers Installation... -
Page 71: Product Cd/Dvd
Product CD/DVD The BOXER-6951 comes with a product DVD that contains all the drivers and utilities you need to setup your product. Insert the DVD and follow the steps in the autorun program to install the drivers. In case the program does not start, follow the sequence below to install the drivers. Step 1 –... - Page 72 For Windows XP Open Device Manager In the device tree, locate the device with an exclamation mark and right click to open properties Under the Drivers tab, select update driver Navigate to the directory where is drivers are stored and confirm Follow the instructions Drivers will be installed automatically Step 4 –...
- Page 73 Step 7 – Install UART Drivers (Optional) For Windows 7: Change User Account Control settings to Never notify Reboot and log in as administrator Chapter 4 – Driver Installation...
- Page 74 Run patch.bat as administrator Chapter 4 – Driver Installation...
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Page 75: Appendix A - Watchdog Timer Programming
Appendix A Appendix A - Watchdog Timer Programming... -
Page 76: Watchdog Timer Initial Program
A.1 Watchdog Timer Initial Program Table 1 : SuperIO relative register table Default Value Note SIO MB PnP Mode Index Register Index 0x2E(Note1) 0x2E or 0x4E SIO MB PnP Mode Data Register Data 0x2F(Note2) 0x2F or 0x4F Table 2 : Watchdog relative register table Register BitNum Value... - Page 77 ************************************************************************************ // SuperIO relative definition (Please reference to Table 1) #define byte SIOIndex //This parameter is represented from Note1 #define byte SIOData //This parameter is represented from Note2 #define void IOWriteByte(byte IOPort, byte Value); #define byte IOReadByte(byte IOPort); // Watch Dog relative definition (Please reference to Table 2) #define byte TimerLDN //This parameter is represented from Note3 #define byte TimerReg //This parameter is represented from Note4 #define byte TimerVal // This parameter is represented from Note24...
- Page 78 ************************************************************************************ VOID Main(){ // Procedure : AaeonWDTConfig // (byte)Timer : Time of WDT timer.(0x00~0xFF) // (boolean)Unit : Select time unit(0: second, 1: minute). AaeonWDTConfig(); // Procedure : AaeonWDTEnable // This procudure will enable the WDT counting. AaeonWDTEnable(); ************************************************************************************ Appendix A – Watchdog Timer Programming...
- Page 79 ************************************************************************************ // Procedure : AaeonWDTEnable VOID AaeonWDTEnable (){ WDTEnableDisable(EnableLDN, EnableReg, EnableBit, 1); // Procedure : AaeonWDTConfig VOID AaeonWDTConfig (){ // Disable WDT counting WDTEnableDisable(EnableLDN, EnableReg, EnableBit, 0); // Clear Watchdog Timeout Status WDTClearTimeoutStatus(); // WDT relative parameter setting WDTParameterSetting(); VOID WDTEnableDisable(byte LDN, byte Register, byte BitNum, byte Value){ SIOBitSet(LDN, Register, BitNum, Value);...
- Page 80 ************************************************************************************ VOID SIOEnterMBPnPMode(){ IOWriteByte(SIOIndex, 0x87); IOWriteByte(SIOIndex, 0x87); VOID SIOExitMBPnPMode(){ IOWriteByte(SIOIndex, 0xAA); VOID SIOSelectLDN(byte LDN){ IOWriteByte(SIOIndex, 0x07); // SIO LDN Register Offset = 0x07 IOWriteByte(SIOData, LDN); VOID SIOBitSet(byte LDN, byte Register, byte BitNum, byte Value){ Byte TmpValue; SIOEnterMBPnPMode(); SIOSelectLDN(byte LDN); IOWriteByte(SIOIndex, Register); TmpValue = IOReadByte(SIOData);...
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Page 81: Appendix B - I/O Information
Appendix B Appendix B - I/O Information... -
Page 82: I/O Address Map
I/O Address Map Appendix B – I/O Information... - Page 83 Appendix B – I/O Information...
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Page 84: Memory Address Map
Memory Address Map Appendix B – I/O Information... -
Page 85: Irq Mapping Chart
IRQ Mapping Chart Appendix B – I/O Information... - Page 86 Appendix B – I/O Information...
- Page 87 Appendix B – I/O Information...
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Page 88: Dma Channel Assignments
DMA Channel Assignments Appendix B – I/O Information... -
Page 89: Appendix C - Digital I/O Ports
Appendix C Appendix C – Digital I/O Ports... -
Page 90: Di/O Programming
DI/O Programming BOXER-6951 utilizes FINTEK F81866 chipset as its Digital I/O controller. Below are the procedures to complete its configuration. AAEON initial DI/O program is also attached for developing customized program for your application. There are three steps to complete the configuration setup:... -
Page 91: Digital I/O Register
Digital I/O Register Table 1 : SuperIO relative register table Default Value Note SIO MB PnP Mode Index Register Index 0x2E(Note1) 0x2E or 0x4E SIO MB PnP Mode Data Register Data 0x2F(Note2) 0x2F or 0x4F Table 2 : Digital Input relative register table Register BitNum Value... -
Page 92: Digital I/O Sample Program
Digital I/O Sample Program ************************************************************************************ // SuperIO relative definition (Please reference to Table 1) #define byte SIOIndex //This parameter is represented from Note1 #define byte SIOData //This parameter is represented from Note2 #define void IOWriteByte(byte IOPort, byte Value); #define byte IOReadByte(byte IOPort); // Digital Input Status relative definition (Please reference to Table 2) #define byte DInput1LDN // This parameter is represented from Note3 #define byte DInput1Reg // This parameter is represented from Note4... - Page 93 ************************************************************************************ // Digital Output control relative definition (Please reference to Table 3) #define byte DOutput1LDN // This parameter is represented from Note27 #define byte DOutput1Reg // This parameter is represented from Note28 #define byte DOutput1Bit // This parameter is represented from Note29 #define byte DOutput1Val // This parameter is represented from Note30 #define byte DOutput2LDN // This parameter is represented from Note31 #define byte DOutput2Reg // This parameter is represented from Note32...
- Page 94 ************************************************************************************ VOID Main(){ Boolean PinStatus ; // Procedure : AaeonReadPinStatus // Input : Example, Read Digital I/O Pin 3 status // Output : InputStatus : 0: Digital I/O Pin level is low 1: Digital I/O Pin level is High PinStatus = AaeonReadPinStatus(DInput3LDN, DInput3Reg, DInput3Bit); // Procedure : AaeonSetOutputLevel // Input : Example, Set Digital I/O Pin 6 level...
- Page 95 ************************************************************************************ Boolean AaeonReadPinStatus(byte LDN, byte Register, byte BitNum){ Boolean PinStatus ; PinStatus = SIOBitRead(LDN, Register, BitNum); Return PinStatus ; VOID AaeonSetOutputLevel(byte LDN, byte Register, byte BitNum, byte Value){ ConfigToOutputMode(LDN, Register, BitNum); SIOBitSet(LDN, Register, BitNum, Value); ************************************************************************************ Appendix C – Digital I/O Ports...
- Page 96 ************************************************************************************ VOID SIOEnterMBPnPMode(){ IOWriteByte(SIOIndex, 0x87); IOWriteByte(SIOIndex, 0x87); VOID SIOExitMBPnPMode(){ IOWriteByte(SIOIndex, 0xAA); VOID SIOSelectLDN(byte LDN){ IOWriteByte(SIOIndex, 0x07); // SIO LDN Register Offset = 0x07 IOWriteByte(SIOData, LDN); VOID SIOBitSet(byte LDN, byte Register, byte BitNum, byte Value){ Byte TmpValue; SIOEnterMBPnPMode(); SIOSelectLDN(byte LDN); IOWriteByte(SIOIndex, Register); TmpValue = IOReadByte(SIOData);...
- Page 97 ************************************************************************************ Boolean SIOBitRead(byte LDN, byte Register, byte BitNum){ Byte TmpValue; SIOEnterMBPnPMode(); SIOSelectLDN(LDN); IOWriteByte(SIOIndex, Register); TmpValue = IOReadByte(SIOData); TmpValue &= (1 << BitNum); SIOExitMBPnPMode(); If(TmpValue == 0) Return 0; Return 1; VOID ConfigToOutputMode(byte LDN, byte Register, byte BitNum){ Byte TmpValue, OutputEnableReg; OutputEnableReg = Register-1;...
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