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2
Basic Operating Information
2.1
Power Supply
PAN1322-SPP is supplied from a single supply voltage VSUPPLY. This supply voltage must always be present.
The PAN1322-SPP chip is supplied from an internally generated 2.5 V supply voltage. This voltage can be
accessed from the VREG pin. This voltage may not be used for supplying other components in the host system
but can be used for referencing the host interfaces.
The GPIO's and the UART interface are supplied with dedicated, independent, reference levels via the VDD1 and
VDDUART pins. All other digital I/O pins are supplied internally by either 2.5 V (Internal2) or 1.5 V (Internal1).
Section 1.4
provides a mapping between pins and supply voltages.
The I/O power domains (VDD1 and VDDUART) are completely separated from the other power domains and can
stay present also in low power modes.
2.2
Clocking
PAN1322-SPP contains a crystal from which the internal 26 MHz system clock is generated. Also, the low power
mode clock of 32,768 kHz is generated internally, which means that no external clock is needed.
2.3
Low Power Modes
To minimize current consumption, eUniStone automatically switches between different low power modes. The
major modes are described below.
2.3.1
Low Power Mode
In Low Power Mode (LPM) most parts of eUniStone are powered down. This is done automatically in idle mode
or if the link is in Sniff mode and the host allows LPM with the pin P0.14.
2.3.2
Complete Power Down
If Bluetooth functionality is not needed at all, VSUPPLY should be grounded to minimize power consumption. In
this state there is no activity in eUniStone and the Bluetooth state (native clock, etc.) is not updated.
2.3.3
ON/OFF
PAN1322-SPP provides an alternative way to power down using the ONOFF logic input. When the ONOFF is low,
the internal regulator on the module is turned OFF. The intention with the signal is to have the possibility to turn
off the module without having to turn off the supply voltage. In the OFF state, the module will consume less than
1mA excluding the interface currents that is mainly set by the external load.
If this signal isn't used then it should be connected to VSUPPLY on the host PCB.
User's Manual
Hardware Description
15
PAN1322-SPP
ENW89841A3KF
Basic Operating Information
Revision 1.3, 2013-08-14
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