Denon AVR-X6400H Service Manual page 177

fig.10a
AVR-X6400H/SR8012 DIGITAL AUDIO/NETWORK BLOCK DIRAGRAM
DIGITAL AUDIO BLOCK
Wireless Network
Input
Wired Network
Input
NET_VideoSignal(Clock/HS/VS/DE)
Netowrk Module
NET_VBUSdata(R:8bit/B:8bit/G:8bit)
AVR-X6400
SR8012
USB-A
Input (FRONT) Z2NET_I2S
USB-A AVR-X7200
Input (REAR) AV8802
AVR-X7200
AV8802
iPod
Coprocessor
I2S/DSD_eARC
SPDIF_eARC
INPUT
SPDIF_eARC
INPUT
I2S/DSD_HDMIRX
SPDIF_HDMIRX
INPUT
SPDIF_HDMIRX
INPUT
I2S_HDMITX
OUTPUT
SPDIF_Z2HDMI
INPUT
NET_VideoSignal(Clock/HS/VS/DE)
OUTPUT
NET_VBUSdata(R:8bit/B:8bit/G:8bit)
OUTPUT
OPT1
OPT2
COAX1
COAX2
DENONLinkHD
AVR-X6400H only
Jitter Reducer PLL
CS2100
FCXO-05 FCXO-05 FCXO-05
22.5792MHz 24.576MHz 25.0MHz
DSP_CLK
Ref clock Sel.
fs Assign Sel.
DENON Link HD
Generator Module
1/2 1/4
Div. Div.
I2S_NET DSP1 INPUT MUX
DSD_NET I2S_HDMIRX
1 2
DSD_HDMIRX
1 2
I2S_eARC
1 2
DSD_eARC
1 2
I2S_NET
1 2
DSD_NET
1 2
DIR_I2S
1 2
Z2NETADC I2S_HDMITX
Clock Generator
I2S_NET
HDMI SPDIF
SELECTOR
SPDIF_eARC
SPDIF_HDMIRX
ADCCLK
Main DIR
PCM9211
SDATA
I2S/DSD_eARC
SPDIF_HDMIRX
COAX1
I2S/DSD_HDMIRX COAX2
OPT1 Z2NET_ADCINL
I2S_HDMITX OPT2
SPDIF_Z2HDMI Z2NET_ADCINR
SPDIF_Z2HDMI
OPT1
OPT2
COAX1
CLK
COAX2
Z2_SPDIF Z2DIR_I2S
ZONE2 DIR
DLHD LC89091JA
CLK
Z3_SPDIF Z3DIR_I2S
ZONE3 DIR
LC89091JA
SDRAM FLASH SDRAM FLASH SDRAM FLASH SDRAM FLASH
1st DSP 2nd DSP 3rd DSP 4th DSP
ADSP-21487 ADSP-21487 ADSP-21487 ADSP-21487
DSP_CLK
DSP3 INPUT MUX
1
3
2
DAC INPUT MUX
1
2
ZONE2 I2S MUX
ZONE2
Z2DAC_I2S
1 Mute Logic
3
2
ZONE3 I2S MUX
ZONE3
Z3DAC_I2S
1
Mute Logic
3
2
177
6
7
5
3
1
2
6
7
5
3
MAIN DAC1
1
2
6
AK4458
7
5
3
1
2
6
7
5
3
Main ZONE
1
Mute Logic 2
6
7
3 5
3
1
2
6
7
5
3
MAIN DAC2
1
2
6
AK4458
7
5
3
1
2
Audio PLD
5M570ZF256C5N
ADC_CLK
MAIN ADC
SDATA
AK5358B
ZONE2 DAC
Z2DAC_I2S
PCM5100
ZONE3 DAC
Z3DAC_I2S
PCM5100
Z2NET_ADCINL
Z2NET_ADCINR
I2S_NET
NET DAC
PCM5100
DA_FL
OUTPUT
DA_FR
OUTPUT
DA_C
OUTPUT
DA_SW1
OUTPUT
DA_SW2
OUTPUT
DA_RSV
OUTPUT
DA_SL
OUTPUT
DA_SR
OUTPUT
DA_SBL
OUTPUT
DA_SBR
OUTPUT
DA_H1L
OUTPUT
DA_H1R
OUTPUT
DA_H2L
OUTPUT
DA_H2R
OUTPUT
ADIN_FL
INPUT
ADIN_FR
INPUT
Z2DA_L
OUTPUT
Z2DA_R
OUTPUT
Z3DA_L
OUTPUT
Z3DA_R
OUTPUT
Z2NET_ADCINL
INPUT
Z2NET_ADCINR
INPUT
NET_L
OUTPUT
NET_R
OUTPUT