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MS11-BC
Maintenance manual
Digital Equipment MS11-BC Maintenance Manual
Pdp 11/45 ms11 semiconductor memory systems
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Contents
Table of Contents
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Table of Contents
Table of Contents
Chapter 1 System Description
Introduction
M8111 Bipolar Memory Matrix Module
G401 Mas Memory Matrix Module
Memory Address Multiplexing
Write and Read Data Registers
Timing and Control
Refresh Logic
Parity Control
Diagnostic Logic
System Specifications
Semiconductor Memory System Configurations
Bipolar Memory System Configuration
Chapter 2 Memory System Interface Operations
Introduction
Basic Memory Access Operations
Data in (DATI) Cycle
Data In, Pause (DATIP) Cycle
Data out (Data) Operation
Data Out, Byte (DATOB) Cycle
Fastbus Interface
Fastbus/M8110 Interface and Control Signals
Fastbus Data Cycle
Fastbus and Unibus Control Bit States
Fastbus DATI Cycle
Unibus Interface
Unibus/M8110 Interface Information and Control Signals
Unibus Data Cycle
Unibus DATI Cycle
Memory Bus
Semiconductor Memory Addressing
Address Decoding at the M8Ll 0 Control
Address Mapping at the M8Ll 0 Control
Mas Memory Matrix Module Address Decoding
Bipolar Memory Matrix Module Address Decoding
Chapter 3 Logic Description
Introduction
Mas Memory Writing
MOS Matrix Selected Address Configuration (4 of 16K)
MOS :Memorj Reading
Memory Matrix Control
Address Buffer
Data Inversion and Write Pulse Fanout Logic
Address Examination Logic
Address Bit to MAD Bit Translation
Bipolar Matrix
M8110 Semiconductor Memory Control Module
Address Decoding for Memory Circuit Enabling
Memory Selection Logic
Mos/Bipolar Memory Addressing
Unibus Interface (Smeh)
Address Multiplexing (SMCC)
Unibus Address Multiplexing
Fastbus Address Multiplexing
Multiplexed Address Inputs to MAD (SMCC)
Refresh Address Multiplexing
Data Multiplexing (SMCD)
Data Output (SMCE)
Diagnostic Logic
Diagnostic Address Decoding
Diagnostic Parity Registers
Diagnostic Parity Register Functions
Diagnostic Parity Register a and B Control States
Parity Diagnostic Register Bit Identity and Function
Refresh Logic
Normal Refresh Cycle
Refresh Cycle During Power-Down Periods
Chapter 4 Calibration and Maintenance
Introduction
Semiconductor Memory System Precalibration Procedures
Memory Cycling Program
Test Equipment Required
Calibration Setup
Memory System Calibration
MOS Memory System Calibration
Semiconductor Memory Adjustments
Address Set Up, Precharge, CENABLE, and Access Ready Timing Adjustments
Bipolar Memory System Calibration
Address Set Up, Precharge, and Access Ready Timing Adjustments
Semiconductor Memory System Diagnostics
Memory Matrix Module Structure
Isolation of Malfunctions to Module Component
Appendix A Application of Mosfets in IC Random Access Memories
The MOSFET A-I
The MOSFET as a Memory
Drain Characteristics of a MOSFET
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PDP-11/45
MS11 semiconductor
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This manual is also suitable for:
Ms11-bd
Ms11-bm
Ms11-bp
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