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Handbook
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Manual
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User manual
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Contents
Table of Contents
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Table of Contents
Table of Contents
Preface
Chapter 1 • Introduction
PDP-Ll/84 System
Software
Networks
Peripherals
Service
Documentation
Chapter 2 • PDP
Introduction
Features
System Architecture
Central Processor
General Registers
Processor Status Word
Program Interrupt Request Register
Pipeline Processing
CPU Error Register
Stack Limit Protection
Kernel Protection
Trap and Interrupt Priorities
Hardware Detected Errors
Private Memory Interconnect
Memory System
Memory Management
Error Correction Code
Battery Backup Unit
UNIBUS Adapter (UBA)
Dmacache
UNIBUS Mapping
Boot ROM Facility
Cache Memory
Cache Registers
Console Functions
Console Serial Line Unit Registers
Line-Time Clock
Clock Status Register
Console
Setup Mode
Program Mode
Console ODT Mode
Specifications
Chapter 3' PDP
System Architecture
Central Processor
General Registers
Processor Status Word
CPU Registers
CPU Error Register
Processor Traps
Program Interrupt Request Register
CPU and I/O Device Registers and Addresses
Memory Systems
Memory Management
UNIBUS Map
Cache Memory
General System Architecture
CPU Bypass of the Cache
Cache Memory Organization
Cache-Control Registers
Floating-Point Processor
Backplane Configuration
Serial Line Unit Registers
Serial Line Unit Timing Considerations
Terminal Serial Line Unit Control Registers
Second Serial Line Unit Registers (SLU 2)
Line Clock
Line Clock Status Register
Address and Vector Assignment
Specifications
Chapter 4 ·PDP
System Architecture
Central Processor
Registers
Processor Status Word
CPU Error Register
Processor Traps
CPU and I/O Device Registers and Addresses
Memory System
Memory Management
Console
Console ODT Mode
Address Specification
Processor I/O Addresses
Stack Pointer Selection
Entering Octal Digits
Terminal Serial Line Unit Control Registers
Second Serial Line Unit Registers
Line Clock
Clock Status Register
Address and Vector Assignments
Specifications
Chapter 5 • UNIBUS Technical Description
Characteristics of the UNIBUS
Nonmultiplexed Bus
Strict Master/Slave Relationship
Partially Distributed Arbitration
Overlapped Arbitration and Data Transfer
Asynchronous Operation
Address Bits
Word or Byte Operations
Parity Error Information from Slaves
UNIBUS Block Diagram
UNIBUS Data and Address Organization
Types of UNIBUS Data Transfers
Read Word
Write Word
Write Byte
Read Word with Write Intent
Write Vector
UNIBUS Signal Details
Initialization and Shutdown Signals
Powerup Timing
Powerdown Timing
Initialization Timing
Arbitration Signals
UNIBUS Arbitration Timing
Abnormal Cycles
Data Transfer Signals
DATI Timing
Datip
Write Vector Timing
Abnormal Bus Cycles
Multiple Bus Cycles
Miscellaneous Signals
UNIBUS Electrical Characteristics
Electrically Bidirectional High-Speed Lines
Electrically Unidirectional High-Speed Lines
BUS AC lo L and BUS DC lo L
Design Suggestions
Watch the DC Voltage Levels
Maintain 120-Ohm Impedance and Watch Ac Signals
Minimize Crosstalk
Consider All Timing Cases
Be a Good Bus Citizen
Appendix A • PDP-Ll Family Differences Table
Appendix B· Console Commands
Appendix C • Instruction Times
Index
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