Digital Equipment MF11-U Manuals

Manuals and User Guides for Digital Equipment MF11-U. We have 1 Digital Equipment MF11-U manual available for free PDF download: Maintenance Manual

Digital Equipment MF11-U Maintenance Manual

Digital Equipment MF11-U Maintenance Manual (120 pages)

PDP11 core memory system

Brand: Digital Equipment | Category: Computer Hardware | Size: 12 MB

Table of Contents

Table of Contents
5
MATB CLK MDR 0 L, MATB CLK MDR 1 L Signals
38
MATB PAUSE H Signal
38
MATC READ EARLY L Signal
38
MATC END STROBEL Signal
39
MATC READ LATE L Signal
39
MATC OUTPUT ENABLE H Signal
39
BUS SSYN L Signal
39
MATC 300 NS DLY H Signal
39
MATD WRITE EARLY L Signal
39
MATD STACK CHG H Signal
39
MATD WRITE LATE L Signal
39
MATD INH TIME H Signal
39
WRITE LOCKOUT H Signal
40
MATD END of WRITE L Signal
40
Chapter3 Driver, Sense and Stack Modules

42
- Introduction
  42
- Core Array
  42
- Memory Operation
  42
  - Andy Decoding
    45
- Drivers and Switches
  45
  - Word Address Decoding and Selection Sequence
    49
- Read/Write Current Generation and Sensing
  50
  - Introduction
    50
  - Read/Write Operations
    50
  - And y Current Generators
    53
  - Inhibit Driver
    55
  - Sense Amplifier
    57
  - Memory Data Register
    57
- Stack Charge Circuit
  57
CHAPTER 4 Mfll-UP CORE MEMORY with PARITY

60
- Introduction
  60
- Description
  60
- Specifications
  61
- Functional Description
  62
  - DATI or DATIP Cycle
    62
  - DATO Cycle
    63
  - DATOB Cycle
    63
  - Jumper Terminals
    63
- Programming
  64
- Bus Loading
  64
- Internal Bus
  65
- Possible Interlea Ying Configurations
  65
- Address Selection
  65
Chapter 5 Installation and Maintenance

70
- Introduction
  70
- Installation
  70
- Mounting Box and Power System
  70
- Jumper Configuration
  73
- Installation Procedure
  74
- Preventive Maintenance
  76
- Visual Inspection
  76
- Voltage Measurements
  76
- Sense Strobe Delay Check
  76
- Drive Current F:hecks
  76
- PCL SSYN DLY Check (for Parity Memories Only)
  77
- Strobe and Drive Current Margins
  77
- MAINDEC Testing
  77
- Corrective Maintenance
  77
- Voltage Adjustment Procedure
  77
- Sense Strobe Delay and Drive Current Adjustments
  77
- PCL SSYN DLY L Adjustment Procedure
  78
- Corrective Maintenance Aids
  78
- Maindec Testing
  78
- L 0-124K Memory Exerciser (MAINDEC-11-DZQMB)
  79
- Combined Parity Memory Tests (MAINDEC-11-DCMFA)
  79
Appendix A IC Descriptions

97
- 741 High Performance Operational Amplifier
  97
- 7442 4 Line to 1 Line Decoder
  98
- 7475 4-Bit Bistable Latch
  100
- 7483 4-Bit Binary Adder
  102
- 7485 4-Bit Comparator
  105
- 7528 Sense Amplifier
  107
- 82S62 9-Bit Parity Generator and Checker
  109
- 74121 Monostable Multivibrator
  110
- 74154 4-Line to 16-Line Demultiplexer
  112
- A.io 75325 Memory Drivers
  115

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