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MS11-BC
User Manuals: Digital Equipment MS11-BC Memory System
Manuals and User Guides for Digital Equipment MS11-BC Memory System. We have
1
Digital Equipment MS11-BC Memory System manual available for free PDF download: Maintenance Manual
Digital Equipment MS11-BC Maintenance Manual (109 pages)
PDP 11/45 MS11 semiconductor memory systems
Brand:
Digital Equipment
| Category:
Computer Hardware
| Size: 6 MB
Table of Contents
Table of Contents
4
Chapter 1 System Description
10
Introduction
10
M8111 Bipolar Memory Matrix Module
11
G401 Mas Memory Matrix Module
11
Memory Address Multiplexing
12
Write and Read Data Registers
12
Timing and Control
13
Refresh Logic
13
Parity Control
13
Diagnostic Logic
14
System Specifications
14
Semiconductor Memory System Configurations
15
Bipolar Memory System Configuration
15
Chapter 2 Memory System Interface Operations
18
Introduction
18
Basic Memory Access Operations
18
Data in (DATI) Cycle
19
Data In, Pause (DATIP) Cycle
19
Data out (Data) Operation
21
Data Out, Byte (DATOB) Cycle
21
Fastbus Interface
21
Fastbus/M8110 Interface and Control Signals
21
Fastbus Data Cycle
22
Fastbus and Unibus Control Bit States
22
Fastbus DATI Cycle
24
Unibus Interface
24
Unibus/M8110 Interface Information and Control Signals
24
Unibus Data Cycle
25
Unibus DATI Cycle
25
Memory Bus
25
Semiconductor Memory Addressing
27
Address Decoding at the M8Ll 0 Control
28
Address Mapping at the M8Ll 0 Control
28
Mas Memory Matrix Module Address Decoding
29
Bipolar Memory Matrix Module Address Decoding
29
Chapter 3 Logic Description
32
Introduction
32
Mas Memory Writing
33
MOS Matrix Selected Address Configuration (4 of 16K)
33
MOS :Memorj Reading
35
Memory Matrix Control
35
Address Buffer
35
Data Inversion and Write Pulse Fanout Logic
37
Address Examination Logic
37
Address Bit to MAD Bit Translation
37
Bipolar Matrix
38
M8110 Semiconductor Memory Control Module
39
Address Decoding for Memory Circuit Enabling
39
Memory Selection Logic
41
Mos/Bipolar Memory Addressing
43
Unibus Interface (Smeh)
44
Address Multiplexing (SMCC)
46
Unibus Address Multiplexing
47
Fastbus Address Multiplexing
47
Multiplexed Address Inputs to MAD (SMCC)
47
Refresh Address Multiplexing
48
Data Multiplexing (SMCD)
48
Data Output (SMCE)
48
Diagnostic Logic
49
Diagnostic Address Decoding
74
Diagnostic Parity Registers
74
Diagnostic Parity Register Functions
75
Diagnostic Parity Register a and B Control States
75
Parity Diagnostic Register Bit Identity and Function
75
Refresh Logic
77
Normal Refresh Cycle
77
Refresh Cycle During Power-Down Periods
77
Chapter 4 Calibration and Maintenance
81
Introduction
81
Semiconductor Memory System Precalibration Procedures
81
Memory Cycling Program
81
Test Equipment Required
82
Calibration Setup
82
Memory System Calibration
82
MOS Memory System Calibration
82
Semiconductor Memory Adjustments
82
Address Set Up, Precharge, CENABLE, and Access Ready Timing Adjustments
83
Bipolar Memory System Calibration
84
Address Set Up, Precharge, and Access Ready Timing Adjustments
84
Semiconductor Memory System Diagnostics
84
Memory Matrix Module Structure
85
Isolation of Malfunctions to Module Component
85
Appendix A Application of Mosfets in IC Random Access Memories
89
The MOSFET A-I
89
The MOSFET as a Memory
90
Drain Characteristics of a MOSFET
90
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