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PIN No.
Signal name
96
/FAXCS
IN
97
/ESPRD
IN
98
GND
Power
99
/ESREQ
OUT
100
/ESACK
IN
101
/ESCS
IN
102
PARAD0
IN/OUT
103
PARAD1
IN/OUT
104
PARAD2
IN/OUT
105
PARAD3
IN/OUT
106
PARAD4
IN/OUT
107
PARAD5
IN/OUT
108
5V
Power
109
PARAD6
IN/OUT
110
PARAD7
IN/OUT
111
GND
Power
112
/REV
OUT
113
INIT
IN
114
/SLCTIN
IN
115
/AUTOFD
IN
116
/STB
IN
117
/ACK
OUT
118
BUSY
OUT
119
PE
OUT
120
/FAULT
OUT
121
5V
Power
122
SLCT
OUT
123
/TESTPIN0
IN
124
GND
Power
125
PFCLK
IN
126
/TESTPIN1
IN
127
/SYNCEN
OUT
128
SD10
IN/OUT
129
SD11
IN/OUT
130
SD12
IN/OUT
131
SD13
IN/OUT
132
SD14
IN/OUT
133
5V
Power
134
SD15
IN/OUT
135
SD16
IN/OUT
136
GND
Power
137
SD17
IN/OUT
138
SOE1
OUT
139
SWE1
OUT
140
SCS1
OUT
IN/OUT
Connected to
FAX board
Electric sort board
(Reserved)
Electric sort board
(Reserved)
Electric sort board
(Reserved)
Electric sort board
(Reserved)
1284 board connector DATA bus (IEEE1284 communication port)
1284 board connector DATA bus (IEEE1284 communication port)
1284 board connector DATA bus (IEEE1284 communication port)
1284 board connector DATA bus (IEEE1284 communication port)
1284 board connector DATA bus (IEEE1284 communication port)
1284 board connector DATA bus (IEEE1284 communication port)
1284 board connector DATA bus (IEEE1284 communication port)
1284 board connector DATA bus (IEEE1284 communication port)
1284 board connector ECP mode I/O select (LOW:P → H)
1284 board connector INIT signal (IEEE1284 communication port)
1284 board connector /SLCTIN signal (IEEE1284 communication port)
1284 board connector /AUTOFD signal (IEEE1284 communication port)
1284 board connector /STB signal (IEEE1284 communication port)
1284 board connector /ACK signal (IEEE1284 communication port)
1284 board connector BUSY signal (IEEE1284 communication port)
1284 board connector PE signal (IEEE1284 communication port)
1284 board connector /FAULT signal (IEEE1284 communication port)
1284 board connector /SLCTIN signal (IEEE1284 communication port)
TEST PIN
Transmitter
TEST PIN
JITTER
ADJUSTMENT IC
SRAM (separation)
SRAM (separation)
SRAM (separation)
SRAM (separation)
SRAM (separation)
SRAM (separation)
SRAM (separation)
SRAM (separation)
SRAM (separation)
SRAM (separation)
SRAM (separation)
OUTD bus enable signal H bus impedance HIGH state
∗
(Reserved)
∗
(Reserved)
∗
(Reserved)
∗
(Reserved)
High: Normal Low: Test
Write clock
High: Normal Low: Test
Jitter adjustment IC trigger signal
Data line to SRAM before are separation
Data line to SRAM before are separation
Data line to SRAM before are separation
Data line to SRAM before are separation
Data line to SRAM before are separation
Data line to SRAM before are separation
Data line to SRAM before are separation
Data line to SRAM before are separation
Read enable line to SRAM before area separation
Write enable line to SRAM before area separation
Chip select line to SRAM before area separation
13 – 7
DP1200/1500
Description
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