List Of Figures - Siemens 7SR224 Description & Operation

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IST OF IGURES
Figure 1.5-1 Functional Diagram of 7SR224 Relay Showing Possible External
Connections .........................................................................................................................9
Figure 2.5-1 7SR224 with 12 Function Keys and 3 + 8 LEDs in E10 Case...........................................11
Figure 2.8-1 Binary Input Logic .............................................................................................................14
Figure 2.9-1 Binary Output Logic ..........................................................................................................16
Figure 3.1-1 Logic Diagram: Directional Overcurrent Element (67).......................................................19
Figure 3.1-2 Logic Diagram: Instantaneous Over-current Element .......................................................20
Figure 3.1-3 Logic Diagram: Time Delayed Overcurrent Element .................................................22
Figure 3.2-1 Logic Diagram: Voltage Controlled Overcurrent Protection...............................................23
Figure 3.3-1 Logic Diagram: Measured Directional Earth Fault Protection ...........................................25
Figure 3.3-2 Logic Diagram: Measured Instantaneous Earth-fault Element..........................................25
Figure 3.3-3 Logic Diagram: Measured Time Delayed Earth Fault Element (51G) ...............................26
Figure 3.4-1 Logic Diagram: SEF Directional Element (67SEF)............................................................27
Figure 3.4-2 Logic Diagram: SEF Instantaneous Element.....................................................................28
Figure 3.4-3 Logic Diagram: SEF Time Delayed Element (51SEF).......................................................29
Figure 3.5-1 Logic Diagram: High Impedance REF (64H) .....................................................................30
Figure 3.6-1 Logic Diagram: Cold Load Settings (51c) ..........................................................................31
Figure 3.7-1 Logic Diagram: Negative Phase Sequence Overcurrent (46NPS)....................................32
Figure 3.8-1 Logic Diagram: Undercurrent Detector (37) ......................................................................33
Figure 3.9-1 Logic Diagram: Thermal Overload Protection (49S)..........................................................35
Figure 3.10-1 Logic Diagram: Under/Over Voltage Elements (27/59) .............................................36
Figure 3.11-1 Logic Diagram: NPS Overvoltage Protection (47) .....................................................37
Figure 3.12-1 Logic Diagram: Neutral Overvoltage Element............................................................38
Figure 3.13-1 Logic Diagram: Under/Over Frequency Detector (81) ...............................................39
Figure 4.1-1 Typical Auto Reclose Sequence with 3 Instantaneous and 1 Delayed trip .......................42
Figure 4.1-2 Basic Auto-Reclose Sequence Diagram ...........................................................................47
Figure 4.3-1 Logic Diagram: Circuit Breaker Status...............................................................................49
Figure 4.4-1 Sequence Diagram: Quick Logic PU/DO Timers (Counter Reset Mode Off) ....................51
Figure 5.1-1 Logic Diagram: Circuit Breaker Fail Protection (50BF).....................................................52
Figure 5.2-1 Logic Diagram: VT Supervision Function (60VTS)............................................................54
Figure 5.3-1 Logic Diagram: CT Supervision Function (60CTS) ..........................................................55
Figure 5.4-1 Logic Diagram: Broken Conductor Function (46BC) .........................................................56
Figure 5.5-1 Logic Diagram: Trip Circuit Supervision Feature (74TCS) ................................................56
Figure 5.6-1 Logic Diagram: Harmonic Block Feature (81HBL2) ..........................................................57
Figure 5.7-1 Battery Test timing diagram...............................................................................................58
Figure 5.8-1 Capacitor Test timing diagram ...................................................................................59
Figure 5.9-1 Sag and Swell Indices - IEEE 1159 ...................................................................................60
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(1) Description of Operation 7SR224
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