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IC11 : SII9185ACTU [HDMI]
System Switching Pins
Pin Name
Pin #
Type
DSDA0,
30,
LVTTL,
DSDA1,
50,
Schmitt Trigger,
DSDA2
70
5V tolerant
DSCL0,
31,
LVTTL,
DSCL1,
51,
Schmitt Trigger,
DSCL2
71
5V tolerant
RPWR0,
32,
LVTTL,
5V Tolerant
RPWR1,
52,
RPWR2
72
LVTTL, 2mA,
HPD0,
16,
5V Tolerant
HDP1,
36,
HPD2
56
LVTTL,
HPDIN
76
5V Tolerant
TSCL
78
LVTTL,
Schmitt Trigger.
Open Drain
5V tolerant
LVTTL,
TSDA
77
Schmitt Trigger,
5V tolerant
Note:
1. These signals are true open drain, and do not pull to ground when power is not applied to the device. These signals
require an external pull-up.
Configuration Pins
Pin Name
Pin #
Type
I2CADDR/
79
LVTTL, 4mA,
TPWR
5V Tolerant
I2CSEL/INT#
35
Schmitt Trigger,
Open Drain, 4mA,
5V Tolerant
RSVDL
75
Control Pins
Pin Name
Pin #
Type
RESET#
13
LVTTL,
Schmitt Trigger.
5V tolerant
LSCL/EPSEL1
15
Schmitt
5V tolerant
LSDA/EPSEL0
14
LVTTL,
Schmitt Trigger.
Open Drain
5V tolerant
CEC Pins
Pin Name
Pin #
Type
CEC_A
54
CEC Compliant,
5V tolerant.
CEC_D
53
LVTTL,
Schmitt Trigger
5V tolerant.
Dir
Description
2
Input/
DDC I
C Data for respective port. Note 1.
Output
2
Input
DDC I
C Clock for respective port. Note 1.
Input
5V Port detection input for respective port.
Connect to 5V signal from HDMI input connector.
Output
Hot Plug Detect Output for respective port.
Connect to HOTPLUG of HDMI input connector.
Input
Hot Plug Detect Input.
2
Output
Master DDC I
C Clock (Open Drain Output) to HDMI receiver.
2
I
C transactions required for HDCP operation are performed
2
over this I
C bus. Note 1.
Input/
Master DDC Data (Open drain output.) to HDMI receiver. I
transactions required for HDCP operation are performed over
Output
2
this I
C bus. Note 1.
Dir
Description
2
Input/
I
C Slave Address input / Transmit Power Sense output pin.
Output
When RESET# is low, this pin is used as an input to latch the
2
I
C sub-address. The level on this pin is latched when the
RESET# pin transitions from low to high.
When RESET# is high, this pin is used as the TPWR output,
indicating that the selected Rx-port is has 5V present. When
none of the Rx ports are selected, this signal is low.
See page 15 for more information.
2
Input/
I
C Selection input / Interrupt output pin.
Output
When RESET# is low, this pin is used as an input to latch the
External Port Detection signal. The level on this pin is latched
when the RESET# pin transitions from low to high.
When this pin is high during reset, the external pins
EPSEL1/LSCL and EPSEL0/LSDA are used to select the Rx-
port as EPSEL[1:0].
When this pin is low during reset, the internal local I
is used to select the Rx-port.
After reset, this pin becomes the Interrupt output.
This is an open-drain output and requires an external pull-up.
See page 14 for more information.
Input
Reserved for use by Silicon Image and must be tied low.
Dir
Description
Input
Reset Pin (Active LOW). Certain configuration inputs are
latched when RESET# transitions from low to high. See page
14 for more information.
2
Input
Local I
C Clock / External Port Select 1. When I2CSEL is high,
2
this becomes the Local I
C bus clock pin, LSCL. When I2CSEL
is low, this becomes the external port select pin, EPSEL1. True
open drain, so does not pull to ground if power not applied. An
external pull-up is required.
See page 14 for more information.
2
Input/
Local I
C Data / External Port Select 0. When I2CSEL is high,
2
this becomes the Local I
C bus data pin, LSDA. When I2CSEL
Output
is low, this becomes the external port select pin, EPSEL0. True
open drain, so does not pull to ground if power not applied. An
external pull-up is required.
See page 14 for more information.
Direction
Description
Input/
HDMI compliant CEC I/O used to interface to CEC devices.
Output
CEC electrically compliant signal. This pin connects to the CEC
signal of all HDMI connectors in the system.
As an input, the pad acts as a LVTTL Schmitt triggered input
and is 5V tolerant. As an output, the pad acts as an NMOS
driver with resistive pull-up. This pin has an internal pull-up
resistor.
Input/
CEC interface to local system. True open-drain. An external
Output
pull-up is required. This pin typically connects to the local CPU.
Differential Signal Data Pins
Pin Name
Pin #
R0X0+
22
R0X0-
21
R0X1+
25
R0X1-
24
R0X2+
28
R0X2-
27
R0C+
19
R0C-
18
R1X0+
42
R1X0-
41
R1X1+
45
R1X1-
44
R1X2+
48
R1X2-
47
R1C+
39
2
R1C-
38
C
R2X0+
62
R2X0-
61
R2X1+
65
R2X1-
64
R2X2+
68
R2X2-
67
R2C+
59
R2C-
58
TX0+
7
TX0-
8
TX1+
4
TX1-
5
TX2+
1
TX2-
2
TXC+
10
TXC-
11
EXT_SWING
12
2
C register
Power and Ground Pins
Pin Name
Pin #
AVCC33
23, 43, 55, 63
AVCC18
6, 17, 29, 37, 49, 57, 69
AGND
3, 9, 20, 26, 40,
46, 60, 66, 80
DVCC18
33, 73
DGND
34, 74
147
Type
Dir
Description
TMDS
Input
TMDS input Port 0 data pairs.
TMDS
Input
TMDS
Input
TMDS
Input
TMDS
Input
TMDS
Input
TMDS
Input
TMDS input Port 0 clock pair.
TMDS
Input
TMDS
Input
TMDS input port 1 data pairs.
TMDS
Input
TMDS
Input
TMDS
Input
TMDS
Input
TMDS
Input
TMDS
Input
TMDS input Port 1 clock pair.
TMDS
Input
TMDS
Input
TMDS input port 2 data pairs.
TMDS
Input
TMDS
Input
TMDS
Input
TMDS
Input
TMDS
Input
TMDS
Input
TMDS input Port 2 clock pair.
TMDS
Input
TMDS
Output
TMDS output data pairs.
TMDS
Output
TMDS
Output
TMDS
Output
TMDS
Output
TMDS
Output
TMDS
Output
TMDS output clock pair.
TMDS
Output
Analog
Input
Voltage Swing Adjust. A resistor tied from this pin to
AVCC18 determines the amplitude of the voltage swing.
The recommended value is 500 .
Type
Description
Power
Analog VCC. Connect to 3.3V supply.
Power
Analog VCC. Connect to 1.8V supply.
Ground
Analog GND.
Power
Digital VCC. Connect to 1.8V supply.
Ground
Digital GND.
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