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TCC8600 Pin Description
Signal Name
SD_CLK
SD_CKE / GPIO_B[0]
SD_nCS / GPIO_B[1]
XA[21] / DQM[0]
XA[20] / DQM[1]
XA[19] / DQM[1]
XA[18] / DQM[0]
XA[17] / ND_CLE
XA[16] / SD_nRAS / ND_ALE
XA[15] / SD_nCAS
XA[14] / SD_BA[1]
XA[13] / SD_BA[0]
XA[12]
XA[11]
XA[10]
XA[9]
XA[8]
XA[7]
XA[6]
XA[5]
XA[4]
XA[3]
XA[2]
XA[1]
XA[0]
XD[15]
XD[14]
XD[13]
XD[12]
XD[11]
XD[10]
XD[9]
XD[8]
XD[7]
XD[6]
XD[5]
XD[4]
XD[3]
XD[2]
XD[1]
XD[0]
nWE
nOE
ND_nWE / GPIO_B[7]
nCS[3] / ND_nOE[3] / GPIO_B[5]
nCS[2] / ND_nOE[2] / GPIO_B[4]
nCS[1] / ND_nOE[1] / GPIO_B[3]
nCS[0] / ND_nOE[0] / GPIO_B[2]
READY / MODE0
USBH1_DP / GPIO_B[26]
USBH1_DN / GPIO_B[27]
USBH0_DP / GPIO_B[28]
USBH0_DN / GPIO_B[29]
Pin# Type Description – TCC8600
44
I/O
SDRAM Clock
46
I/O
SDRAM Clock Enable signal. Active high. / GPIO_B[0]
47
I/O
Chip select signal for SDRAM, Active low / GPIO_B[1]
42
I/O
External Bus Address Bit [21] / Data I/O Mask 0
41
I/O
External Bus Address Bit [20] / Data I/O Mask 1
39
I/O
External Bus Address Bit [19] / Data I/O Mask 1
38
I/O
External Bus Address Bit [18] / Data I/O Mask 0
37
I/O
External Bus Address Bit [17] / CLE for NAND Flash
36
I/O
External Bus Address Bit [16] / SDRAM RAS signal / ALE for NAND Flash
35
I/O
External Bus Address Bit [15] / SDRAM CAS signal
34
I/O
External Bus Address Bit [14] / SDRAM Bank Address 1
33
I/O
External Bus Address Bit [13] / SDRAM Bank Address 0.
32
I/O
External Bus Address Bit [12]
31
I/O
External Bus Address Bit [11]
30
I/O
External Bus Address Bit [10]
29
I/O
External Bus Address Bit [9]
28
I/O
External Bus Address Bit [8]
27
I/O
External Bus Address Bit [7]
23
I/O
External Bus Address Bit [6]
22
I/O
External Bus Address Bit [5]
21
I/O
External Bus Address Bit [4]
20
I/O
External Bus Address Bit [3]
19
I/O
External Bus Address Bit [2]
18
I/O
External Bus Address Bit [1]
17
I/O
External Bus Address Bit [0]
16
I/O
External Bus Data Bit [15]. Internal pull-up resistor enabled at reset.
15
I/O
External Bus Data Bit [14]. Internal pull-up resistor enabled at reset.
14
I/O
External Bus Data Bit [13]. Internal pull-up resistor enabled at reset.
13
I/O
External Bus Data Bit [12]. Internal pull-up resistor enabled at reset.
12
I/O
External Bus Data Bit [11]. Internal pull-up resistor enabled at reset.
11
I/O
External Bus Data Bit [10]. Internal pull-up resistor enabled at reset.
10
I/O
External Bus Data Bit [9]. Internal pull-up resistor enabled at reset.
6
I/O
External Bus Data Bit [8]. Internal pull-up resistor enabled at reset.
5
I/O
External Bus Data Bit [7]. Internal pull-up resistor enabled at reset.
4
I/O
External Bus Data Bit [6]. Internal pull-up resistor enabled at reset.
3
I/O
External Bus Data Bit [5]. Internal pull-up resistor enabled at reset.
2
I/O
External Bus Data Bit [4]. Internal pull-up resistor enabled at reset.
128
I/O
External Bus Data Bit [3]. Internal pull-up resistor enabled at reset.
127
I/O
External Bus Data Bit [2]. Internal pull-up resistor enabled at reset.
126
I/O
External Bus Data Bit [1]. Internal pull-up resistor enabled at reset.
125
I/O
External Bus Data Bit [0]. Internal pull-up resistor enabled at reset.
48
I/O
Static Memory Write Enable signal. Active low.
49
I/O
Static Memory Output Enable signal. Active low.
61
I/O
NAND flash WE. Active low. / GPIO_B[7]
53
I/O
External Bus Chip Select [3] / NAND Flash Output Enable [3] / GPIO_B[5]
52
I/O
External Bus Chip Select [2] / NAND Flash Output Enable [2] / GPIO_B[4]
51
I/O
External Bus Chip Select [1] / NAND Flash Output Enable [1] / GPIO_B[3]
50
I/O
External Bus Chip Select [0] / NAND Flash Output Enable [0] / GPIO_B[2]
64
I
Ready information from external device.
83
I/O
USB Host Port 1 D+ signal / GPIO_B[26]
82
I/O
USB Host Port 1 D- signal / GPIO_B[27]
80
I/O
USB Host Port 0 D+ signal / GPIO_B[28]
79
I/O
USB Host Port 0 D- signal / GPIO_B[29]
151
p
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