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Theory
of
Operation-DM
505
Upon completion of the 2048 clock pulse auto-zero
interval,
the
measurement interval commences. The
measure-zero logic switches the analog input voltage t o
the buffer input and disconnects the integrator output
from the auto-zero amplifier input. The additional current
resulting at the summing junction of theintegrator causes
the integrator output voltage to move away from the
equilibrium voltage obtained during auto-zero interval
and maintained during the measurement interval by
C1102. The comparator senses and transmits this devia-
tion to
the
control logic.
The
control logic changes the
duty cycle of
the
reference voltage in
an attempt
to re-
establish equilibrium at the integrator summing junctfon.
The
up-down logic
is
"up" (integrator output voltage is
also
up)
for
one
clock
cycle
and
"down" for seven cycles
when the comparator output was high during the
preceding set of eight clock cycles.
This is
shown as duty
cycle
A
i n Fig. 3-3. When the comparator output is low in
clock cycle seven, the up-down logic i s up for seven cycles
and down for one cycle during the following eight clock
cycles. This is shown
as
duty cycle B. Figure3-3 showsthe
result of these actions on the integrator output.
A counter in U1303, synchronous with the up-down
logic, increments by each clock pulse when the up-down
logic is "up" and decrements by each clock pulse when
the up-down Iogic is "down". The net count increases
by
six counts for each B duty cycle and decreases by six
counts for each Aduty cycle, t o a maximum count of about
3100.
This counting procedure is reversed for negative
input voltages.
The
polarity of the input voltage is determined by the
state of the updown logic when the bcd counter state is
zero. This information is stored i n a flip-llop and loaded
into the static latch Once each measurezero cycle.
The bcd counter accumulates
a
number of counts
proportional to the input voltage during the measure
interval while
the
control logic works to maintain
equijibrium. Equilibrium is achieved in steps and usual1 y a
residual voltage remains at the end of the measurement
cycle. This residual voltage is Compensated for by a short
override interval at
the
beginning of the auto-zero period.
The counter continues until the integrator output equals
the auto-zeroequilibrium voltageand the up-down logic is
"down". The
bcd
counter is now
put
on hold and its
contents Zoaded into the latches. The counter is then
cleared and the multiplexer sends the measurement
result, digit by digit, to the output data buffers.
Display Driver Circuitry
@
Integrated circuit
U1301,
pins 13, 14, 15, and 16,
provides bcd output of digits in parallel form, multi;plexed
by digit. The bcd digit signals are decoded by
U1501
and
applied to the cathodes of seven-segment LED
Uf
002,
U1101,
and U1102. The segments of these LED are
connected i n parallel to U1501. Digit strobesfrom U1303,
pins
7,2,3,
and
4
are inverted by U 1302 A, B, C, and D and
applied t o the anodesof the LED by Q1402, Q1403, Q1404,
CLOCK
INPUT
C Y C L E T O
r
2
3
4
5
s
7
0
1
2
3
4
5
s
7 1
9
Z
~
~
S
B
~
O
1
2
3
4
s
e t o
M I ' u/a
4 -
MEASURE INTERvM
c"Y"CyE
L
d
A
A
&
B - 1
COMPARATOR
I
I
I
INTEGRATOR
OUTPUT
V S ~ R G
2 6 9 M
Fig.
3-3.
Measurement Interval timing.
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