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CS4397
Block Diagram
SCLK
LRCK
SDATA
CLOCK
MCLK
DIVIDER
M4
M3
(AD0/CS)
(AD1/CDIN) (SCL/CCLK)
Pin Configuration
+5 to +3 V
Digital
+
M ode
S elect
(Contro l P o rt)
A u dio
D ata
P ro cessor
E xternal C lo ck
Typical Connection Diagram - Hardware Mode (Control Port Mode)
Circuit Descriptions and List of Abbreviations
SERIAL INTERFACE
AND FORMAT SELECT
MULTI-BIT
INTERPOLATION
FILTER
MODULATOR
MULTI-BIT
INTERPOLATION
FILTER
MODULATOR
HARDWARE MODE CONTROL
(CONTROL PORT)
M2
M1
M0
RESET
(SDA/CDOUT)
7
8
V D
V D
5
M 0 (S D A /C DO U T )
14
M 1 (G N D)
4
M 2 (S CL/C C LK )
3
M 3 (A D1/C DIN)
2
M 4 (AD 0/CS )
16
C /H
CS 4397
12
LR CK
11
S C L K
13
S D AT A
15
M U T E
1
R S T
10
M CL K
D G ND
9
6
DE-EMPHASIS
SOFT MUTE
FILTER
DYNAMIC
ELEMENT
DS
MATCHING
LOGIC
DYNAMIC
ELEMENT
DS
MATCHING
LOGIC
VOLTAGE REFERENCE
MUTEC MUTE
FILT+
+
22
V A
28
V RE F
27
F ILT +
26
FILT -
25
CM O U T
24
A O UT L -
An alog
C ond itio nin g
23
A O UT L+
17
M U T E C
19
A O UT R-
An alog
C ond itio nin g
20
A O U T R+
A G ND
21
18
SACD 900
9.
SWITCHED
AOUTL+
CAPACITOR-DAC
AOUTL-
AND FILTER
SWITCHED
AOUTR+
CAPACITOR-DAC
AOUTR-
AND FILTER
VREF
FILT-
CMOUT
+5 V
A na lo g
+5V
An alog
+
+
CL 06532152_099.eps
131200
EN 143
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