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This IC decodes EFM or EFM+HF signals directly from the
laser pre-amplifier, including analogue front-end, PLL data
recovery, demodulation, and error correction.
The analogue front-end input converts the HF input to the
digital domain via an 8-bit ADC, proceeded by an AGC circuit
to obtain the optimum performance from the converter. An
external resonator clocks this block. This subsystem recovers
the data from the channel stream. It corrects asymmetry,
performs noise filtering and equalisation, and finally recovers
the bit clock and data from the channel using a digital PLL.
The demodulator part detects the frame synchronisation
signals and decodes the EFM (14 bit) and EFM+ (16 bit) data
and sub-code words into 8-bit symbols. Via the serial output
2
interface, the I
S data (audio and video) go to the DVD decoder
STi5505.
The spindle-motor interface provides both motor control signals
from the demodulator and, in addition, contains a tachometer
loop that accepts tachometer pulses from the motor unit. They
drive the motor IC (item 7304).
The SAA7335 has two independent microcontroller interfaces.
2
The first is a serial I
C-bus and the second is a
standard 8-bit multiplexed parallel interface. Both of these
interfaces provide access to 32 8-bit registers for control and
status.
9.3.2
The Digital Part
The Host Processor STi5505
The STi5505 host processor works on 3.3 V (VDD_STI). It
comprises the following functions:
•
video decoder which supports MPEG1 and MPEG2
•
audio decoder which supports AC-3, MPEG1, MPEG2,
PCM, 6-channel, virtual surround
•
PAL/NTSC video encoder with simultaneously Y/C, CVBS
and RGB/YUV outputs
•
the video encoder supports Closed Captioning (CC) and
MacroVision 7.0/6.1
•
full screen On Screen Display (OSD) generator
•
on-chip PLLs to generate all necessary clocks (as
reference the 27 MHz video clock is used).
Input
Input data comes from the I
this device, accepts DVD, CD and CD-DA information.
Signal Processing
For video, the input data stream is decoded to the appropriate
MPEG, Sub Picture, and OSD data streams, after which they
are fed to the PAL/NTSC encoder. This cell will convert the
digital MPEG/Sub Picture/OSD stream into a standard base
band signal and into RGB components. It handles interlaced
and non-interlaced data, can perform CC/TXT encoding, and
allows MacroVision copy protection.
For audio, the processing cell is a fully compatible Dolby AC-3,
MPEG1, MPEG2, PCM decoder, capable of decoding 5.1 and
2 channel streams.
Output
For video, six analogue output pins are available on which
CVBS, S-VHS (Y/C), and RGB/YUV signals are present. They
go directly to the A/V board.
For audio, the STi5505 has three PCM digital outputs (for 6-
channel analogue audio):
•
PCM_OUT0: left and right (to pin 60 of FURORE IC7800).
•
PCM_OUT1: centre and LFE (to pin 61 of FURORE
IC7800).
•
PCM_OUT2: left and right surround (to pin 62 of FURORE
IC7800).
Circuit Descriptions and List of Abbreviations
2
S-bus. The front-end interface of
SACD 900
The FURORE SACD processor
General
The FURORE-IC is a one-chip design, containing all the
hardware that is required for SACD processing. It is intended to
interface with the STi-family (STi5505/STi5508) DVD video-
decoders.
The FURORE-IC contains a memory interface to support an
external 16 or 64 Mbit SDRAM.
During SACD application, the STi5505 serves as a host,
whereby the FURORE is controlled via the EMI interface. The
FURORE processing part is not used during all other play
modes. In these modes, the PCM audio signals are fed through
the FURORE to the appropriate DAC.
Block Diagram
FURORE
To Host processor
(STi 5505)
3
1
4
Regis er
Host interface
Host
8 b ts
interface
HF
AGC
AD
2
Memory
PSP key
manager
decoder
Key
Control
PI bus
Decrypt on
I 2 S
/
Sector
Processor
Demux
PI Bus
Control
SACD
2 5 6 ch
Audio
LossLess
interface
decoder
SDRAM
in erface
to 16 Mb t
384 * fs
SDRAM
Figure 9-4
We can divide the FURORE-IC in four main parts (see block
diagram):
1. Host interface. This is the link between the host bus and
the internal registers and memory bus. It also supplies the
general reset signal (HW and SW) and the interrupt
signals.
2. Data processing. All modules and peripherals in this part
are connected to a so-called PI-bus. It is beyond the scope
of this manual to go more in detail on this subject.
3. Copy protection. On every SACD disc, a PSP-signal is
recorded. The player can only play a disc if a valid PSP-
signal is detected. This PSP-key is recorded, via a special
mechanism, in the EFM-signal on the disc. To detect this
key, the analogue HF-signal from the optical pick-up unit is
fed directly to the FURORE-IC. Via an AGC, the signal is
fed to an ADC. The digitised HF signal is then fed to a block
where key is encrypted. Control of this process is done via
the host interface (sector processor).
4. DSD decoding and post processing. In this part, all
processing is done to generate a DSD and/or an I
(from the de-multiplexed stream coming from the data
processing block), in such a way that it can directly be
connected to a DA-converter. All processing is done on
384 * f
.
S
Interfaces
•
Basic Engine Interface:
–
Data input interface. The Basic Engine Interface
2
(I
S), is connected to the output of the SAA7335
(HD61) high speed CD decoder.
–
Analogue HF input. The analogue HF input, coming
from the optical pickup unit (OPU), is also fed to the
FURORE-IC, to extract the copy-protection information
PSP (Pit Signal Processing = invisible data is stored on
to disc, which is required to decrypt the encrypted
content).
9.
EN 105
From Host processor
(STi 5505)
PCM
IEC 958
PCM CLK
DSD CLK
IEC 958
IEC 958
gen
DSD >PCM
I 2 S
(stereo)
PCM
DSD
mix
6 channel
DSD/PCM
fade
MUTE
CL 16532136 043 eps
261101
2
S stream
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