Pp_Dma_Size; 10Pp_Wr_Mailbox; 11Pp_Event - Cypress EX-USB FX3 Programmer's Manual

10.2.9

PP_DMA_SIZE

P-Port DMA Transfer Size Register. This register indicates the (remaining) size of the transfer. This
register is initialized to the number of bytes available in the buffer for egress transfers and the size of
the buffer for ingress transfers. This register can be modified by the AP for shorter ingress transfers.
The value read from this register is not valid unless DMA_XFER.SIZE_VALID is true.
Bits
15:0
10.2.10 PP_WR_MAILBOX
P-Port Write (Ingress) Mailbox Registers. These registers contain a message of up to 8 bytes from
the Application Processor to firmware. The semantics of the possible messages is defined as part of
the software specification. These registers also appear in the P-Port MMIO space as
PIB_WR_MAILBOX. When the Application Processor writes data into the high word of
PP_WR_MAILBOX the interrupt PIB_INTR.WR_MB_FULL is set. The expected action is that firm-
ware reads
PP_EVENT.WR_MB_EMPTY to signal AP for the next message (if needed).
Bits
63:0
10.2.11 PP_EVENT
P-Port Event Register. This register indicates all types of events that can cause INTR or DRQ to
assert.
Bits
0 SOCK_AGG_AL
1 SOCK_AGG_AH
2 SOCK_AGG_BL
3 SOCK_AGG_BH
4
5
6
7
FX3 Programmers Manual, Doc. # 001-64707 Rev. *C
Name HW
DMA_SIZE RW
the message and then
Name HW
WR_MAILBOX R
Name HW
RW
RW
RW
RW
GPIF_INT W1S RW1C
PIB_ERR W1S RW1C
MMC_ERR W1S RW1C
GPIF_ERR W1S RW1C
SW Default
Size of DMA transfer. Number of bytes
available for read/write when read, num-
RW 0
ber of bytes to be read/written when writ-
ten.
clears PIB_INTR.WR_MB_FULL,
SW Default
RW 0 Write mailbox message from AP
SW Default
0 : SOCK_STAT_A[7:0] is all zeroes
R 0
1: At least one bit set in SOCK_STAT_A[7:0]
0 : SOCK_STAT_A[15:8] is all zeroes
R 0
1: At least one bit set in SOCK_STAT_A[15:8]
0 : SOCK_STAT_B[7:0] is all zeroes
R 0
1: At least one bit set in SOCK_STAT_B[7:0]
0 : SOCK_STAT_B[15:8] is all zeroes
R 0
1: At least one bit set in SOCK_STAT_B[15:8]
0 1: State machine raised host interrupt
The socket based link controller encountered
an error and needs attention. FW clears this bit
0
after handling the error. The error code is indi-
cated in PP_ERROR.PIB_ERR_CODE
An unrecoverable error occurred in the PMMC
controller. FW clears this bit after handling the
0
eror. The error code is indicated in
PP_ERROR.MMC_ERR_CODE
An error occurred in the GPIF. FW clears this
0 bit after handling the error. The error code is
indicated in PP_ERROR.GPIF_ERR_CODE
FX3 P-Port Register Access
Description
which will set
Description
Description
137