Gpio_Invalue1 Register; Gpio_Intr0 Register; Gpio_Intr1 Register; Complex Gpio (Pin) Registers - Cypress EX-USB FX3 Programmer's Manual

9.2.4

Gpio_invalue1 Register

Input state of the GPIO 32-60. Each bit indicates the state of GPIO. The upper three bits are
reserved.
Bits
28:0 INVALUE1
9.2.5

GPIO_INTR0 Register

This register holds the interrupt state of each GPIO 0 -31. These bits are valid only for those GPIOs
configured as simple GPIO.3.
Bits
31:0
9.2.6

GPIO_INTR1 Register

This register holds the interrupt state of each GPIO 32 -60. The upper three bits are reserved. These
bits are valid only for those GPIOs configured as simple GPIO.
Bits Name
28:0 INTR1
9.3

Complex GPIO (PIN) Registers

The following table lists key registers of the complex GPIO interface.
Table 9-2. Complex GPIO Registers
Address
0xE0001000 +
(GPIO_ID MOD
8) * 0x10
0xE00013E8
a. See table 3 for further break up of each 128 bit register.
The following table lists the pins registers for complex GPIO interface.
FX3 Programmers Manual, Doc. # 001-64707 Rev. *C
Name HW SW
W R
Name HW SW
INTR0 W R
HW SW
W R
Qty Width
8 128
1 32 GPIO_PIN_INTR
FX3 Serial Peripheral Register Access
Default
0 If bit <x> is set, state of GPIO <x + 32>is high.
Default
0 If bit <x> is set, interrupt for GPIO <x> is active.
Default
0 If bit <x> is set, interrupt for GPIO <x + 32>is active.
Name
PIN
General purpose I/O registers (one pin)
GPIO interrupt vector for PINs
Description
Description
Description
Description
a
127