Cypress EX-USB FX3 Programmer's Manual
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Cypress EX-USB FX3 Programmer's Manual

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FX3 Programmers Manual
Doc. # 001-64707 Rev. *C
Cypress Semiconductor
198 Champion Court
San Jose, CA 95134-1709
Phone (USA): 800.858.1810
Phone (Intnl): 408.943.2600
http://www.cypress.com

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Summary of Contents for Cypress EX-USB FX3

  • Page 1 FX3 Programmers Manual Doc. # 001-64707 Rev. *C Cypress Semiconductor 198 Champion Court San Jose, CA 95134-1709 Phone (USA): 800.858.1810 Phone (Intnl): 408.943.2600 http://www.cypress.com...
  • Page 2 Cypress Source Code and derivative works for the sole purpose of creating custom soft- ware and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as speci- fied in the applicable agreement.

  • Page 3: Table Of Contents

    Contents 1. Introduction Chapter Overview ......................10 Document Revision History ..................10 Documentation Conventions ..................11 2. Introduction to USB USB 2.0 System Basics.....................13 2.1.1 Host, Devices, and Hubs................13 2.1.2 Signaling Rates ....................13 2.1.3 Layers of Communication Flow..............13 2.1.4 Device Detection and Enumeration..............17 2.1.5 Power Distribution and Management .............18 2.1.6 Device Classes ....................18 USB 3.0: Differences and Enhancements over USB 2.0 ...........18...
  • Page 4 4.3.1 Firmware Framework ..................50 4.3.2 Firmware API Library ..................50 4.3.3 FX3 Firmware Examples................51 FX3 Host Software ....................51 4.4.1 Cypress Generic USB 3.0 Driver ..............51 4.4.2 Convenience APIs ..................51 4.4.3 USB Control Center ..................51 4.4.4 Bulkloop ......................51 4.4.5 Streamer ......................
  • Page 5 Contents 7.2.2 cyfxbulksrcsink – Bulk Source and Sink............79 7.2.3 cyfxbulkstreams – Bulk Streams ..............79 7.2.4 cyfxisolpauto – ISO loopback using AUTOchannel........79 7.2.5 cyfxisolpmaninout – ISO loopback using MANUAL_IN and MANUAL_OUT Channels80 7.2.6 cyfxisosrcsink – ISO Source Sink ..............80 7.2.7 cyfxflashprog – Boot Flash Programmer............80 7.2.8 cyfxusbdebug –...
  • Page 6 12.2.3 Attaching Debugger to a Running Process..........179 12.2.4 Using Makefiles....................184 12.2.5 Eclipse IDE settings ..................184 13. FX3 Host Software 13.1 FX3 Host Software ....................189 13.1.1 Cypress Generic Driver................189 13.1.2 CYAPI Programmer’s reference..............189 FX3 Programmers Manual, Doc. # 001-64707 Rev. *C...
  • Page 7 Contents 13.1.3 CYUSB.NET Programmer’s reference............189 13.1.4 Cy Control Center ..................190 14. GPIF™ II Designer FX3 Programmers Manual, Doc. # 001-64707 Rev. *C...
  • Page 8 Contents FX3 Programmers Manual, Doc. # 001-64707 Rev. *C...

  • Page 9: Introduction

    I C interface is typically connected to an EEPROM. GPIF II is an enhanced version of the GPIF in FX2LP™, Cypress’s flagship USB 2.0 product. It provides easy and glueless connectivity to popular industry interfaces such as asynchronous and synchronous Slave FIFO, asynchronous SRAM, asynchronous and synchronous Address Data Multiplexed interface, parallel ATA, and so on.

  • Page 10: Chapter Overview

    JTAG based debugging. FX3 Host Software on page 189 describes the Cypress generic USB 3.0 WDF driver, the convenience APIs, and the USB control center. GPIF™ II Designer on page 191 provides a guide to the GPIF II Designer tool.

  • Page 11: Documentation Conventions

    Introduction Documentation Conventions Table 1-2. Document Conventions for Guides Convention Usage Displays file locations, user entered text, and source code: Courier New C:\ ...cd\icc\ Displays file names and reference documentation: Italics Read about the sourcefile.hex file in the PSoC Designer User Guide. Displays keyboard commands in procedures: [Bracketed, Bold] [Enter] or [Ctrl] [C]...
  • Page 12 Introduction FX3 Programmers Manual, Doc. # 001-64707 Rev. *C...

  • Page 13: Introduction To Usb

    Introduction to USB The universal serial bus (USB) has gained wide acceptance as the connection method of choice for PC peripherals. Equally successful in the Windows and Macintosh worlds, USB has delivered on its promises of easy attachment, an end to configuration hassles, and true plug-and-play operation. The USB is the most successful PC peripheral interconnect ever.
  • Page 14 Introduction to USB 2.1.3.1 Pipes, Endpoints USB data transfer can occur between the host software and a logical entity on the device called an endpoint through a logical channel called pipe. A USB device can have up to 32 active pipes, 16 for data transfers to the host, and 16 from it.
  • Page 15 Introduction to USB Isochronous data is time-critical and used to stream data similar to audio and video. An isochronous packet may contain up to 1023 bytes at full-speed, or up to 1024 bytes at high-speed. Time of delivery is the most important requirement for isochronous data. In every USB frame, a certain amount of USB bandwidth is allocated to isochronous transfers.
  • Page 16 Introduction to USB STALL means that something is wrong (probably as a result of miscommunication or lack of cooperation between the host and device software). A device sends the STALL handshake to indicate that it does not understand a device request, that something went wrong on the peripheral end, or that the host tried to access a resource that was not there.

  • Page 17: Device Detection And Enumeration

    Introduction to USB Figure 2-5. Control Transfer 2.1.3.5 Link/Physical Layer The link layer performs additional tasks to increase the reliability of the data transfer. This includes byte ordering, line level framing, and so on. More commonly known as the electrical interface of USB 2.0, this layer consists of circuits to serialize and de-serialize data, pre and post equalization circuits and circuits to drive and detect differential signals on the D+ and D–...

  • Page 18: Power Distribution And Management

    Introduction to USB 2.1.5 Power Distribution and Management Power management refers to the part of the USB Specification that spell out how power is allocated to the devices connected downstream and how different communication layers operate to make best use of the available bus power under different circumstances. USB 2.0 supports both self and bus powered devices.

  • Page 19: Protocol Layer

    Introduction to USB Inspired by the PCI Express and the OSI 7-layer architecture, the USB 3.0 protocol is also abstracted into different layers as illustrated in the following sections. In this document, USB 3.0 implicitly refers to the SuperSpeed portion of USB 3.0. Figure 2-6.
  • Page 20 Introduction to USB Figure 2-8. ACK Transaction Packet Data packets actually carry data. These are made up of two parts: a data header and the actual data. The structure of a data packet is shown on the right. Isochronous Time Stamp packets contain timestamps and are broadcast by the host to all active devices.

  • Page 21: Link Layer

    Introduction to USB Another significant modification introduced in USB 3.0 relates to interrupt transfers. In USB 2.0, Interrupt transfers were issued by the host every service interval regardless of whether or not the device was ready for transfers. However, SuperSpeed interrupt endpoints may send an ERDY/ NRDY in return for an interrupt transfer/request from the host.

  • Page 22: Power Management

    Introduction to USB 2.2.5 Power Management USB 3.0 provides enhanced power management capabilities to address the needs of battery-powered portable applications. Two "Idle" modes (denoted as U1 and U2) are defined in addition to the "Suspend" mode (denoted as U3) of the USB 2.0 standard. The U2 state provides higher power savings than U1 by allowing more analog circuitry (such as clock generation circuits) to be quiesced.

  • Page 23: Fx3 Overview

    FX3 Overview FX3 is a full-feature, general purpose integrated USB 3.0 Super-Speed controller with built-in flexible interface (GPIF II), which is designed to interface to any processor thus enabling customers to add USB 3.0 to any system. The logic block diagram shows the basic block diagram of FX3. The integrated USB 3.0 Phy and controller along with a 32-bit processor make FX3 powerful for data processing and building custom applications.

  • Page 24: Interconnect Fabric

    FX3 Overview the core to facilitate low latency access to frequently used areas of code and data memory. In addition, the two tightly coupled memories (TCM) (one each for data and instruction) associated with the core provide a guaranteed low latency memory (without cache hit or miss uncertainties). The ARM926 CPU contains a full Memory Management Unit (MMU) with virtual to physical address translation.

  • Page 25: Memory

    128-bit wide SRAM banks, which run at full CPU clock frequency. Each bank may be built up from narrow SRAM instances for implementation specific reasons. A Cypress-proprietary high- performance memory controller translates a stream of AHB read and writes requests into SRAM accesses to the SRAM memory array.

  • Page 26: Interrupts

    FX3 Overview Figure 3-3. Internal Memory Unit 512 KB SRAM Memory controller for System memory (AHB to SRAM protocol converter + clocking+power management) (Bus Slave) Slave Interface System Bus The 512 KB system memory can be broadly divided into three. The first few entries of this area is used to store DMA instructions (also known as descriptors).

  • Page 27: Jtag Debugger Interface

    FX3 Overview Figure 3-4. Vector Interrupt Controller PL 192 VIC (Simplified) Other FIQ int lines nFIQ Int_endis[n] INT_ENABLE/DISABLE[31:0] INT_SELECT_FIQ_IRQ#[31:0] Int_fiqirq#[n] INT_PRIORITY[4:0][0:31] Masking and Int_priority[4:0][n] nIRQ Priority logic Int_priority_mask INT_PRIORITY_MASK[15:0] [Int_priority[4:0][n]] INT_ADDRESS[31:0][0:31] IRQ_STATUS[31:0] Interface FIQ_STATUS[31:0] CUR_INT_ADDRESS[31:0] When both FIQ and IRQ interrupt inputs assert, the CPU jumps to the FIQ entry of the exception table.

  • Page 28: Peripherals

    FX3 Overview The ARM debugging environment has three components: A debug-host resident program (Real View debugger), a debug communication channel (JTAG) and a target (Embedded ICE-RT). The two JTAG-style scan chains (Scan1 and Scan2) enable debugging and 'EmbeddedICE-RT-block' programming. Scan Chain 1 is used to debug the ARM9EJ-S core when it has entered the debug state. The scan chain can be used to inject instructions into ARM pipeline and also read or write core registers without having to use the external data bus.
  • Page 29 FX3 Overview Figure 3-6. I2S Blocks DMA/SGL TRANSMIT SGL_LEFT_DATA SGL_RIGHT_DATA FX3: I2S External Device: DMA_LEFT_DATA Master Tx Slave Receiver DMA_RIGHT_DATA PAUSE MUTE ENABLE The I2S block can be configured to support different audio bus widths, endianess, number of channels, and data rate. By default, the interface is protocol standard big endian (most significant bit first);...

  • Page 30: I2C

    FX3 Overview 3.6.2 Figure 3-7. I2C Block Diagram I2C Slave2 FX3_I2C I2C Slave1 Master Other I2C Master FX3 is capable of functioning as a master transceiver and supports 100 KHz, 400 KHz, and 1 MHz operation. The I C block operates in big endian mode (Most significant bit first) and supports both 7-bit and 10-bit slave addressing.

  • Page 31: Uart

    FX3 Overview 3.6.3 UART Figure 3-8. UART Block Diagram SW_RTS CTS_STAT DMA/SGL TRANSFER FX3:DataCarrier Equipment(DCE) SGL_TX_DATA SGL_RX_DATA DMA_TX_DATA DMA_RX_DATA FX3's UART block provides standard asynchronous full-duplex transfer using the TX and RX pins. Flow control mechanism, RTS (request to send) and CTS (clear to send) pins are supported. The UART block can operate at numerous baud rates ranging from 300 bps to 4608 Kbps and supports both one and two stop bits mode of operation.

  • Page 32: Spi

    FX3 Overview 3.6.4 Figure 3-9. SPI Block Diagram FX3 SPI SPI SLAVE MASTER MOSI ENDIAN DMA/SGL TRANSFER RX - SHIFT REGISTER SGL_TX_DATA SGL_RX_DATA DMA_TX_DATA DMA_RX_DATA TX_BYTE_COUNT RX_BYTE_COUNT TX - SHIFT REGISTER ENDIAN MISO SCLK CONTROL FX3's SPI block operates in master mode and facilitates standard full-duplex synchronous transfers using the MOSI (Master out Slave In), MISO (Master In Slave Out), SCLK (Serial Clock), and SS (Slave select) pins.

  • Page 33: Gpio/Pins

    FX3 Overview capture data on the asserting edge of the clock and transmit at the de-asserting edge. When Idle, the SCLK pin remains de-asserted. Hence, the first toggle of SCLK in this mode (CPHA=0) will cause the receivers to latch data; placing a constraint on the transmitters to set up data before the first toggle of SCLK.
  • Page 34 FX3 Overview Table 3-1. Block IO Selection Blk I/O Choose IO Choose IO Choose IO Choose IO Choose IO Choose IO Selection Pins from Pins from Pins from Pins from Pins from Pins from Table blocks: GPIF blocks: GPIF, blocks: GPIF, blocks: GPIF, blocks: blocks:...
  • Page 35 FX3 Overview Table 3-2. Block IO override as simple/complex GPIO FX3 Pin I/O selection Override block IO as simple Override block IO as simple Override block IO as n = 0 to 60 GPIO [pin n] = False GPIO [pin n] = True complex GPIO [pin n] = True Override block IO as Override block IO as...
  • Page 36 FX3 Overview Table 3-3. GPIF IO block pin connection for a few configurations Overall GPIF Pin Count 47-pin 43-pin 35-pin 31-pin 31-pin 47-pin 43-pin 35-pin 31-pin 31-pin Data Bus Width Address Data lines Muxed? GPIF IO [16] GPIF IO[0] D1 / GPIF IO[1] GPIF IO[2] GPIF IO[3]...
  • Page 37 FX3 Overview D21/ D21/ GPIF IO[35] D22/ D22/ GPIF IO[36] D23/ D23/ GPIF IO[37] D24/ GPIF IO[38] D25/ C15/ GPIF IO[39] D26/ C14/ GPIF IO[40] D27/ C13/ GPIF IO[41] D28/ GPIF IO[42] D29/ C15/ GPIF IO[43] D30/ C14/ GPIF IO[44] D31/ C13/ GPIF IO[45]...

  • Page 38: Gpif

    FX3 Overview Certain pins, like the USB lines have specific electrical characteristics and are connected directly to the USB IO-System. They do not have GPIO capability. Pins belonging to the same block share the same group setting (say alpha) for drive strengths. Pins of a block overridden as GPIO share the same group setting (say beta) for their drive strength.

  • Page 39: Dma Mechanism

    FX3 Overview DMA Mechanism Figure 3-11. DMA Mechanism SYSTEM MEMORY PERIPHERAL 1 Non-CPU intervened data chunk transfers between a peripheral and CPU or system memory, between two different peripherals or between two different gateways of the same peripheral, loop back between USB end points, are collectively referred to as DMA in FX3. Figure 3-11 shows a logical paths of data flow;...
  • Page 40 FX3 Overview As explained earlier, the CPU accesses the System Memory (Sysmem) using the System AHB and the DMA paths of the peripherals are all hooked up to the DMA AHB. Bridge(s) between the System bus and the DMA bus are essential in routing the DMA traffic through the Sysmem. The following figure illustrates a typical arrangement of the major DMA components of any DMA capable peripheral of FX3.
  • Page 41 FX3 Overview Figure 3-14. .DMA Configurations (B) multiple buffers of (C) multiple buffers of (E) circular buffer (A) a single large (D) a single large the same size different sizes using multiple buffer of fixed size circular buffer chained to create chained to create sub buffers a large buffer...

  • Page 42: Memory Map And Registers

    FX3 Overview chain. This process goes on until either the buffer chain ends or the next buffer in chain is not available. The producer and consumer socket only share the buffer/descriptor chain. It is not necessary for them to be executing the same descriptor in the chain at any given instant. In nonconventional DMA transactions, the producer and consumer sockets can be two different sockets on the same peripheral.

  • Page 43: Reset, Booting, And Renum

    When plugged into the host, the device enumerates with a Cypress default VID and PID. The actual firmware is then downloaded using Cypress drivers. If required, the firmware can then reconfigure the USB block (such as change the IDs and enable more end points) and simulate a disconnect-event (soft disconnect) of the FX3 device from the USB bus.

  • Page 44: Clocking

    FX3 Overview The boot loader is also responsible for restoring the state of FX3 when the device transitions back from a low power mode to the normal active power mode. The process of system restoration is called 'Warm boot'. 3.10 Clocking Clocks in FX3 are generated from a single 19.2 MHz (±100 ppm) crystal oscillator.
  • Page 45 FX3 Overview Figure 3-18. Clock Generation Structure PLL_SYS_CLK_SEL SEL_CLK _DIV[N:0] PLL_SYS_ CLKS[3:0] peripheral_core_clk DIV_CLK _OUT PLL_SYS_ CLK_SEL FX3_PERIPH_CLK_CFG. SYSCLK_SEL FX3_I2S_CLK_CFG. SELCLK_DIV SEL_CLK _DIV[N:0] DIV_CLK CLKIN _OUT DIV_CLK i2s_core_clk CLKIN _OUT FX3_I2S_CLK_CFG. SYSCLK_SEL FX3_I2S_CLK_CFG. mclk_i2s_in SEL_M_CLK PLL_CFG.MUL CLKOUT_1 MULTIPLY CLKOUT_2 PLL_CFG.DIV DIVIDE CLKOUT_4 FX3_GPIO_FCLK_CFG.

  • Page 46: Power

    FX3 Overview Figure 3-19. DMA Adaptor (a) Core Clock >Bus clock (b) Bus clock>Core Clock Block XYZ Power Domain Block XYZ Power Domain I / O I / O I / O I / O / Bus Core Logic / Bus Core Logic Matrix Pads...
  • Page 47 FX3 Overview logic blocks are first saved to the System RAM. Following this, the System RAM itself is forced into low power memory retention only mode. Warm boot setting is enabled in the global configuration block. Finally the core is powered down. When FX3 comes out of standby, the CPU goes through a reset;...
  • Page 48 FX3 Overview FX3 Programmers Manual, Doc. # 001-64707 Rev. *C...

  • Page 49: Fx3 Software

    FX3 Software Cypress EZ-USB FX3 is the next generation USB 3.0 peripheral controller. This is a highly integrated and flexible chip which enables system designers to add USB 3.0 capability to any system. The FX3 comes with the easy-to-use EZ-USB tools providing a complete solution for fast application development.

  • Page 50: Fx3 Software Development Kit (Sdk)

    USB Driver Assembler Linker JTAG Windows USB DI RTOS Customer Software Cypress provided Software Third Party Software FX3 Firmware Stack Powerful and flexible applications can be rapidly built using FX3 firmware framework and FX3 API libraries. 4.3.1 Firmware Framework The firmware (or application) framework has all the startup and initialization code. It also contains the individual drivers for the USB, GPIF, and serial interface blocks.

  • Page 51: Fx3 Firmware Examples

    A comprehensive host side (Microsoft Windows) stack is included in the FX3 SDK. This stack includes the Cypress generic USB 3.0 driver, APIs that expose the driver interfaces, and application examples. Each of these components are described in brief in this section. Detailed explanations are...

  • Page 52: Fx3 Development Tools

    FX3 Software FX3 Development Tools FX3 is a device with open firmware framework and driver level APIs allowing the customer to develop firmware that matches the application. This approach requires ARM code development and debug environment. A set of development tools is provided with the SDK, which includes the GPIF II Designer and third party toolchain and IDE.

  • Page 53: Fx3 Firmware

    FX3 Firmware The chapter presents the programmers overview of the FX3 device. The boot and the initialization sequence of the FX3 device is described. This sequence is handled by the firmware framework. A high level overview of the API library is also presented, with a description of each programmable block.
  • Page 54 FX3 Firmware Figure 5-1. Initialization Sequence Firmware Entry Point Tool Chain Initialization Firmware Main RTOS Initialization FX3 Application Thread 1. The execution starts from the firmware image entry point. This is defined at the compile time for a given FX3 firmware image. This function initializes the MMU, VIC, and stacks. 2.

  • Page 55: Device Boot

    FX3 Firmware 5.1.1 Device Boot The boot operation of the device is handled by the boot-loader in the boot ROM. On CPU reset, the control is transferred to boot-ROM at address 0xFFFF0000. For cold boot, download the firmware image from various available boot modes of FX3. The bootloader identifies the boot source from the PMODE pins or eFuses and loads the firmware image into the system memory (SYS_MEM).
  • Page 56 FX3 Firmware Figure 5-2. FX3 Memory Map DMA BUFFER AREA (BASE: 0x4004 0000, SIZE: 0x40000) SYSTEM MEMORY (BASE 0x4000 0000, RTOS HEAP AREA (BASE: 0x4003 8000, SIZE: 0x8000) SIZE: 0x80000) OPTIONAL COMPILER HEAP AREA (BASE: 0x4003 7000, SIZE: 0x1000) DATA AREA (BASE: 0x4003 0000, SIZE: 0x8000 – If no compiler heap / 0x7000 if compiler heap is enabled) CODE AREA (BASE: 0x4000 3000, SIZE: 0x2D000) DMA DESCRIPTORS (BASE: 0x4000 0000, SIZE: 0x3000)
  • Page 57 FX3 Firmware MEMORY I-TCM : ORIGIN = 0x100, LENGTH = 0x3F00 SYS_MEM : ORIGIN = 0x40003000 LENGTH = 0x2D000 DATA : ORIGIN = 0x40030000 LENGTH = 0x8000 SECTIONS . = 0x100; .vectors : *(CYU3P_ITCM_SECTION); } >I-TCM . = 0x40003000; .text : *(.text) *(.rodata) *(.constdata)
  • Page 58 FX3 Firmware __exidx_start = .; .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } __exidx_end = .; The contents of each section of the memory map are explained below. 5.1.3.1 I-TCM All instructions that are recommended to be placed under I-TCM are labeled under section CYU3P_ITCM_SECTION.

  • Page 59: Api Library

    FX3 Firmware The thread stacks are allocated from the RTOS managed heap area using the CyU3PMemAlloc() function. 5.1.3.6 DMA buffer area DMA buffer area is managed by helper functions provided as source in     file. These are cyfxtx.c CyU3PDmaBufferInit(), CyU3PDmaBufferAlloc(), CyU3PDmaBufferFree() CyU3PDmaBufferDeInit().
  • Page 60 FX3 Firmware 5.2.1.1 USB Device Mode The USB device mode handling is described in the following sections. USB Descriptors Descriptors must be formed by the application and passed on to the USB driver. Each descriptor (such as Device, Device Qualifier, String, and Config) must be framed as an array and passed to the USB driver through an API call.
  • Page 61 FX3 Firmware The application can perform the necessary event handling and then return from the callback ■ function. If no action is required for a specific event, the application can simply return from the issued call- ■ back function. In both cases, the USB driver completes the default handling of the event. Stall The USB driver provides a set of APIs for stall handling.

  • Page 62: Gpif Ii Block

    FX3 Firmware Connect and disconnect the USB pins ■ Set and get the endpoint configuration ■ Get the endpoint status ■ Set up data transfer on an endpoint ■ Flush and endpoint ■ Stall or Nak an endpoint ■ Get or send data on endpoint 0 ■...
  • Page 63 FX3 Firmware Figure 5-3. GPIF II Flow FX3 Development Environment User Input FX3 Firmware State Machine CHeader GPIF Interface Application Firmware Designer FX3 Firmware APIs and Drivers Figure 5-3 illustrates the flow of the GPIF II interface: The GPIF II Interface Design tool allows to synthesize the configuration by specifying the state ■...

  • Page 64: Serial Interfaces

    FX3 Firmware Disable the GPIF state machine ■ Start the GPIF state machine from a specified state ■ Switch the GPIF state machine to a required state ■ Pause and resume the GPIF state machine ■ Configure a GPIF socket for data transfers ■...
  • Page 65 FX3 Firmware C APIs These include APIs to Initialize/De-initialize the I ■ Configure the I ■ Setup the I C for block data transfer ■ Read/Write bytes from/to the I ■ Send a command to the I ■ 5.2.3.3 The I2S interface must be initialized and configured before it can be used. The interface can be used to send stereo or mono audio output on the I2S link.

  • Page 66: Dma Engine

    FX3 Firmware These include APIs to Initialize/de-initialize the SPI ■ Configure the SPI interface ■ Assert/deassert the SSN line ■ Set up block transfers ■ Read/write a sequence of bytes ■ Enable callbacks on SPI events ■ Register an interrupt handler ■...
  • Page 67 FX3 Firmware Figure 5-4. Auto Channel Produce and consume event signaling Incoming data Outgoing data Consumer Producer (Egress) (Ingress) Socket Socket Buffer Callback function invoked at the end of transfer Descriptor chain Auto Channel with Signaling This channel is a minor variant of the DMA_TYPE_AUTO channel. The channel set up and data flow remains the same.
  • Page 68 FX3 Firmware This type of channel is used when the data flow from many producer (at least 2 producers) has to be directed to one consumer in an interleaved fashion. This model provides RAID0 type of data traffic. One-to-Many Auto Channel This channel is defined as DMA_TYPE_AUTO_ONE_TO_MANY is a variation of the auto channel.
  • Page 69 FX3 Firmware Figure 5-6. Manual Channel Producer descriptor list Consumer descriptor list D0_P D1_P D2_P Dn_P D0_C D1_C D2_C D3_C Outgoing data Incoming data Producer Consumer Buffer (Ingress) (Egress) Socket Socket Consume event signaling Consume event signaling CPU interrupt on every Callback function invoked at Ingress buffer end of transaction...
  • Page 70 FX3 Firmware Figure 5-7. Manual In Channel Producer Incoming data (Ingress) Socket Buffer Buffer low threshold interrupt (optional) Consume event signaling CPU interrupt on every N Ingress buffers Use buffer Buffer ready? Descriptor chain Manual Out Channel The DMA_TYPE_MANUAL_OUT channel is a special channel where the CPU (FX3 firmware) is the producer of data.

  • Page 71: Rtos And Os Primitives

    FX3 Firmware be directed to one consumer in an interleaved fashion with CPU intervention. One-to-Many Manual Channel This channel is defined as DMA_TYPE_MANUAL_ONE_TO_MANY is a variation of the manual channel. It is defined by one valid producer sockets, more than valid consumer socket, and a predetermined amount of buffering;...

  • Page 72: Debug Support

    FX3 Firmware Thread suspend and resume ❐ Thread priority change ❐ Thread sleep ❐ Thread information ❐ Message queues ■ Queue create and delete ❐ Message send and priority send ❐ Message get ❐ Queue flush ❐ Semaphores ■ Semaphore create and destroy ❐...

  • Page 73: Power Management

    FX3 Firmware User code can also use the debug logging mechanism and use the debug log and print functions to insert debug messages. 5.2.7 Power Management Power management support is provided. APIs are available for putting the device into a suspend mode with the option of specifying a wakeup source.
  • Page 74 FX3 Firmware FX3 Programmers Manual, Doc. # 001-64707 Rev. *C...

  • Page 75: Fx3 Apis

    FX3 APIs The FX3 APIs consist of APIs for programming the main hardware blocks of the FX3. These include the USB, GPIF II, DMA and the Serial I/Os. Please refer to the corresponding sections of the FX3API Guide for details of these APIs. FX3 Programmers Manual, Doc.
  • Page 76 FX3 APIs FX3 Programmers Manual, Doc. # 001-64707 Rev. *C...

  • Page 77: Fx3 Application Examples

    FX3 Application Examples The FX3 SDK includes various application examples in source form. These examples illustrate the use of the APIs and firmware framework putting together a complete application. The examples illus- trate the following: Initialization and application entry ■ Creating and launching application threads ■...

  • Page 78: Cyfxbulklpmaninout - Manual_In And Manual_Out Channels

    FX3 Application Examples 7.1.4 cyfxbulklpmaninout – MANUAL_IN and MANUAL_OUT Channels This example demonstrates the use of DMA MANUAL_IN and MANUAL_OUT channels. The data received in EP1 OUT through a MANUAL_IN channel and is copied to a MANUAL_OUT channel so that it can be looped back to EP1 IN. MANUAL_IN channel is used to receive data into the FX3 device.

  • Page 79: Cyfxbulklplowlevel - Descriptor And Socket Apis

    FX3 Application Examples IN after removing the header and footer. The removal of header and footer does not require the copy of data. 7.1.12 cyfxbulklplowlevel – Descriptor and Socket APIs The DMA channel is a helpful construct that allows for simple data transfer. The low level DMA descriptor and DMA socket APIs allow for finer constructs.

  • Page 80: Cyfxisolpmaninout - Iso Loopback Using Manual_In And Manual_Out

    FX3 Application Examples 7.2.5 cyfxisolpmaninout – ISO loopback using MANUAL_IN and MANUAL_OUT Channels This example demonstrates the loopback of data through ISO endpoints. This example is similar to the cyfxbulklpmaninout except for the fact that the endpoints used here are isochronous instead of bulk.

  • Page 81: Cyfxgpioapp - Simple Gpio

    FX3 Application Examples 7.3.1 cyfxgpioapp – Simple GPIO This example demonstrates the use of simple GPIOs to be used as input and output. It also implements the use of GPIO interrupt on the input line. 7.3.2 cyfxgpiocomplexapp – Complex GPIO The FX3 device has eight complex GPIO blocks that can be used to implement various functions such as timer, counter and PWM.

  • Page 82: Uvc Examples

    FX3 Application Examples UVC examples The UVC example is an implementation of a USB Video Class (UVC) device in FX3. This example illustrates: Class device implementation ■ Class and Vendor request handling ■ Multi-threaded application development ■ 7.4.1 cyfxuvcinmem – UVC from System Memory This example demonstrates the USB video class device stack implementation for FX3.

  • Page 83: Usb Audio Class Example

    FX3 Application Examples USB Audio Class Example This example implements a microphone compliant with the USB Audio Class specification. The audio data is not sourced from an actual microphone, but is read from an SPI flash connected to the FX3 device. The audio data is then streamed over isochronous endpoints to the USB host. Two Stage Booter Example (boot_fw) A simple set of APIs have been provided as a separate library to implement two stage booting.
  • Page 84 FX3 Application Examples FX3 Programmers Manual, Doc. # 001-64707 Rev. *C...

  • Page 85: Fx3 Application Structure

    FX3 Application Structure All FX3 application code will consist of two parts Initialization code - This will be mostly common to all applications ■ Application code - This will be the application specific code ■ The Slave FIFO loop application (Slave FIFO Sync) is taken as an example to present the FX3 application structure.
  • Page 86 FX3 Application Structure Figure 8-1. Initializing Sequence 8.1.1.1 Firmware Entry The entry point for the FX3 firmware is CyU3PFirmwareEntry() function. The function is defined in the FX3 API library and is not visible to the user. As part of the linker options, the entry point is be specified as the CyU3PFirmwareEntry() function.
  • Page 87 FX3 Application Structure 8.1.1.2 Tool Chain Initialization The next step in the initialization sequence is the tool chain initialization. This is defined by the specific Toolchain used and provides a method to initialize the stacks and the C library. As all the required stack initialization is performed by the firmware entry function, the Toolchain initialization is over ridden, i.e., the stacks are not re-initialized.
  • Page 88 FX3 Application Structure 2. Device cache configuration: The second step is to configure the device caches. The device has 8KB data cache and 8KB instruction cache. In this example only instruction cache is enabled as the data cache is useful only when there is a large amount of CPU based memory accesses. When used in simple cases, it can decrease performance due to large number of cache flushes and cleans and it also adds complexity to the code.

  • Page 89: Application Code

    FX3 Application Structure 8.1.1.4 Application Definition The function CyFxApplicationDefine() is called by the FX3 library after the OS is invoked. In this function application specific threads are created. In the Slave FIFO example, only one thread is created in the application define function. This is shown below: /* Allocate the memory for the thread */ ptr = CyU3PMemAlloc (CY_FX_SLFIFO_THREAD_STACK);...
  • Page 90 FX3 Application Structure /* Initialize the slave FIFO application */ CyFxSlFifoApplnInit(); for (;;) CyU3PThreadSleep (1000); if (glIsApplnActive) /* Print the number of buffers received so far from the USB host. */ CyU3PDebugPrint (6, "Data tracker: buffers received: %d, buf- fers sent: %d.\n", glDMARxCount, glDMATxCount);...
  • Page 91 FX3 Application Structure The verbosity of the debug. This is set to level 8, so all debug prints which are below this level ❐ (0 to 7) will be printed. /* Initialize the Debug application */ apiRetStatus = CyU3PDebugInit (CY_U3P_LPP_SOCKET_UART_CONS, 8); 8.1.2.3 Application initialization The application initialization consists of the following steps:...
  • Page 92 FX3 Application Structure The next step is to register for callbacks. In this example, callbacks are registered for USB Setup ■ requests and USB Events. /* The fast enumeration is the easiest way to setup a USB connection, * where all enumeration phase is handled by the library. Only the * class / vendor requests need to be handled by the application.
  • Page 93 FX3 Application Structure break; case CY_U3P_SUPER_SPEED: size = 1024; break; default: CyU3PDebugPrint (4, "Error! Invalid USB speed.\n"); CyFxAppErrorHandler (CY_U3P_ERROR_FAILURE); break; CyU3PMemSet ((uint8_t *)&epCfg, 0, sizeof (epCfg)); epCfg.enable = CyTrue; epCfg.epType = CY_U3P_USB_EP_BULK; epCfg.burstLen = 1; epCfg.streams = 0; epCfg.pcktSize = size; /* Producer endpoint configuration */ apiRetStatus = CyU3PSetEpConfig(CY_FX_EP_PRODUCER, &epCfg);...
  • Page 94 FX3 Application Structure 8.1.2.6 USB Event Callback The USB events of interest are: Set Configuration, Reset and Disconnect. The slave FIFO loop is started on receiving a SETCONF event and is stopped on a USB reset or USB disconnect. /* This is the callback function to handle the USB events. */ void CyFxSlFifoApplnUSBEventCB ( CyU3PUsbEventType_t evtype,...
  • Page 95 FX3 Application Structure /* Enabling the callback for produce event. */ dmaCfg.notification = CY_U3P_DMA_CB_PROD_EVENT; dmaCfg.cb = CyFxSlFifoUtoPDmaCallback; dmaCfg.prodHeader = 0; dmaCfg.prodFooter = 0; dmaCfg.consHeader = 0; dmaCfg.prodAvailCount = 0; apiRetStatus = CyU3PDmaChannelCreate (&glChHandleSlFifoUtoP, CY_U3P_DMA_TYPE_MANUAL, &dmaCfg); if (apiRetStatus != CY_U3P_SUCCESS) CyU3PDebugPrint (4, "CyU3PDmaChannelCreate failed, Error code = %d\n", apiRetStatus);...
  • Page 96 FX3 Application Structure The GPIF-II socket ■ USB In Endpoint ■ The two call back functions are shown below /* DMA callback function to handle the produce events for U to P trans- fers. */ void CyFxSlFifoUtoPDmaCallback ( CyU3PDmaChannel *chHandle, CyU3PDmaCbType_t type, CyU3PDmaCBInput_t *input...
  • Page 97 FX3 Application Structure /* This is a produce event notification to the CPU. This notifica- tion is * received upon reception of every buffer. The buffer will not be sent * out unless it is explicitly committed. The call shall fail if there * is a bus reset / usb disconnect or if there is any application error.
  • Page 98 FX3 Application Structure FX3 Programmers Manual, Doc. # 001-64707 Rev. *C...

  • Page 99: Fx3 Serial Peripheral Register Access

    FX3 Serial Peripheral Register Access Serial Peripheral (LPP) Registers The EZ-USB FX3 device implements a set of serial peripheral interfaces (I2S, I C, UART, and SPI) that can be used to talk to other devices. This chapter lists the FX3 device registers that provide con- trol and status information for each of these interfaces.
  • Page 100 FX3 Serial Peripheral Register Access Default Bits Field Name Description Access Access Value I2S_MODE: 0: WS = 0 denotes the left Channel 1: WS = 0 denotes the right channel. WSMODE In left/right justified modes: 1: WS = 0 denotes the left Channel 0: WS = 0 denotes the right channel.
  • Page 101 FX3 Serial Peripheral Register Access 9.1.1.2 I2S_STATUS Register The I2S_STATUS register reports the current status of the I2S master interface. Default Bits Field Name Description Access Access Value Indicates no more data is available for transmis- sion on left channel. Non sticky. If DMA_MODE = 0, this is defined as TX FIFO empty and shift register empty but asserts only when ENABLE = 0.
  • Page 102 FX3 Serial Peripheral Register Access Default Bits Field Name Description Access Access Value Error code, only relevant when ERROR = 1. ERROR logs only the FIRST error to occur and will never change value as long as ERROR = 1. 11: Left TX FIFO/DMA socket underflow 27:24 ERROR_CODE W...
  • Page 103 FX3 Serial Peripheral Register Access 9.1.1.4 I2S_INTR_MASK Register The I2S_INTR_MASK is used to enable the desired I2S related interrupt sources. Default Bits Field Name Description Access Access Value TXL_DONE Enable reporting of I2S_INTR.TXL_DONE to CPU. Enable reporting of I2S_INTR.TXL_SPACE to TXL_SPACE CPU.
  • Page 104 FX3 Serial Peripheral Register Access I2S_COUNTER register 9.1.1.7 The I2S_COUNTER register counts the number of data samples written to the output (Left output + Right output counts as 1). This can be used to control the audio decoder software. Default Bits Field Name Description...

  • Page 105: I2C Registers

    FX3 Serial Peripheral Register Access I2S_POWER register 9.1.1.10 The I2S_POWER register is used to turn power to the I2S block ON/OFF. Default Bits Field Name Description Access Access Value Indicates that the block is powered up and ready ACTIVE for operation. Other I2S registers should be only accessed after this bit has been set to 1.
  • Page 106 FX3 Serial Peripheral Register Access 9.1.2.1 I2C_CONFIG register The I2C_CONFIG register is used to configure I2C interface parameters and to enable the block. Default Bits Field Name Description Access Access Value 0: Register-based transfers DMA_MODE 1: DMA-based transfers 1: I2C is in the 100-KHz mode, use clock with I2C_100KHz 50% duty cycle.
  • Page 107 FX3 Serial Peripheral Register Access Default Bits Field Name Description Access Access Value Indicates no more data is available for transmis- sion. Non sticky. If DMA_MODE = 0, this is defined as TX FIFO empty and shift register empty. TX_DONE If DMA_MODE = 1, this is defined as BYTES_TARNSFERRED=BYTE_COUNT and shift register empty.
  • Page 108 FX3 Serial Peripheral Register Access 9.1.2.3 I2C_INTR register The I2C_INTR register reports the status of I C-related interrupt conditions. The interrupt status bits correspond to status bits in the I2C_STATUS, but are sticky; that is, the interrupt status bit stays set until cleared by firmware.
  • Page 109 FX3 Serial Peripheral Register Access 9.1.2.5 I2C_TIMEOUT register This register specifies the bus timeout interval for I C operations. This specifies the limit to which the slave can delay a transfer by stretching the clock. Note that the timeout is specified in terms of the C core clock, which is 10 times as fast as the I C interface clock frequency specified.
  • Page 110 FX3 Serial Peripheral Register Access 9.1.2.8 I2C_PREAMBLE_DATAx register This register contains the slave and device-specific address data that is sent to the slave during the preamble phase. A maximum of eight bytes (two words) can be stored in these registers. The I2C_COMMAND register should be used to specify the actual length of the preamble.
  • Page 111 FX3 Serial Peripheral Register Access Default Bits Field Name Description Access Access Value 1: Send START before the first byte of preamble START_FIRST 0: Do nothing before the first byte of pre- amble 0: The data phase is a write operation 1: The data phase is a read operation READ After command, the HW will idle if no valid...
  • Page 112 FX3 Serial Peripheral Register Access 9.1.2.14 I2C_BYTES_TRANSFERRED register This register indicates the number of bytes remaining to be transferred in the data phase. The I block initializes this register with the I2C_BYTE_COUNT value and then counts down towards zero as the transfer progresses. Bits Field Name Default Value...

  • Page 113: Uart Registers

    FX3 Serial Peripheral Register Access 9.1.3 UART Registers The FX3 device implements a UART block that can communicate with other UART controllers at dif- ferent baud rates and supports different communication parameters, parity settings, and flow control. This section documents the UART related configuration and status registers. Width Name Address...
  • Page 114 FX3 Serial Peripheral Register Access Default Bits Field Name Description Access Access Value 00: Reserved 01: 1 Stop bit. 10: 2 Stop bits STOP_BITS 11: Reserved Note: STOP_BITS = 2 is supported only when PARITY=0. Behavior is undefined otherwise. 0: Register-based transfers DMA_MODE 1: DMA-based transfers Request To Send bit.
  • Page 115 FX3 Serial Peripheral Register Access 9.1.3.2 UART_STATUS register This register reflects the current status of the UART block. Default Bits Field Name Description Access Access Value Indicates receive operation completed, that is, the desired length of data is received. RX_DONE Only relevant when DMA_MODE = 1.
  • Page 116 FX3 Serial Peripheral Register Access Default Bits Field Name Description Access Access Value Indicates the block is busy transmitting data. This field may remain asserted after BUSY the block is suspended and must be polled before changing any configuration values. 9.1.3.3 UART_INTR register This register reports the status of various UART block interrupts on the FX3 device.
  • Page 117 FX3 Serial Peripheral Register Access 9.1.3.4 UART_INTR_MASK register This register enables/disables the reporting of UART block interrupts to the ARM CPU. Default Bits Field Name Description Access Access Value 1: Enables reporting of RX_DONE UART_INTR.RX_DONE to the CPU 1: Enables reporting of RX_DATA UART_INTR.RX_DATA to the CPU 1: Enables reporting of...
  • Page 118 FX3 Serial Peripheral Register Access 9.1.3.7 UART_SOCKET register This register is used to select the LPP DMA sockets through which the UART block will send or receive data. Default Bits Field Name Description Access Access Value Socket number for egress data 0 - 7: Supported EGRESS_SOCKET R This field should be set to 3.

  • Page 119: Spi Registers

    FX3 Serial Peripheral Register Access 9.1.3.11 UART_POWER register This register is used to power the UART block ON/OFF or to reset the block. Bits Field Name Default Value Description Access Access Indicates whether the block is active. Will be set to 0 for some time after the ACTIVE block is reset, and will be set to 1 after the block has been fully powered up.
  • Page 120 FX3 Serial Peripheral Register Access Default Bits Field Name Description Access Access Value This bit controls SSN behavior at the end of each received and transmitted word, if SSNC- TRL indicates firmware SSN control. This bit is transmitted over SSN line “as is”, without regards to how many cycles it is going out.
  • Page 121 FX3 Serial Peripheral Register Access Default Bits Field Name Description Access Access Value 0: Do nothing 1: Clear transmit FIFO TX_CLEAR Firmware must wait for TX_DONE before clearing this bit. Enable block here, but only after all of the con- figuration is set.
  • Page 122 FX3 Serial Peripheral Register Access Default Bits Field Name Description Access Access Value An internal error has occurred with cause ERROR_CODE. ERROR RW1S RW1C Sticky. Must be cleared by software. Error code. Only relevant when ERROR=1. ERROR logs only the FIRST error to occur and will never change value as long as ERROR=1.
  • Page 123 FX3 Serial Peripheral Register Access 1: Enable the reporting of TX_HALF SPI_INTR.TX_HALF interrupt to CPU 1: Enable the reporting of ERROR SPI_INTR.ERROR interrupt to CPU 9.1.4.5 SPI_EGRESS_DATA register This register is used to put data into the SPI transmit FIFO, while doing data transfers in register mode (SPI_CONFIG.DMA_MODE=0).
  • Page 124 FX3 Serial Peripheral Register Access 9.1.4.7 SPI_SOCKET register This register is used to select the LPP DMA sockets that are to be used for SPI data transfers in DMA mode. Default Bits Field Name Description Access Access Value Socket number for egress data 0 - 7: Supported EGRESS_SOCKET Should be set to 4.

  • Page 125: Fx3 Gpio Register Interface

    FX3 Serial Peripheral Register Access 9.1.4.11 SPI_POWER register This register is used to power the SPI block ON/OFF and also to reset the block when required. Default Bits Field Name Description Access Access Value Indicates whether the block is active. Will be set to 0 for some time after the ACTIVE block is reset, and will be set to 1 after...

  • Page 126: Gpio_Simple Register

    FX3 Serial Peripheral Register Access 9.2.2 GPIO_SIMPLE Register This register controls mode of operation and configuration for a single I/O Pin. It also exposes status and read value. There are 61 registers, one for each GPIO. This register is valid only for the I/Os configured as simple GPIO.

  • Page 127: Gpio_Invalue1 Register

    FX3 Serial Peripheral Register Access 9.2.4 Gpio_invalue1 Register Input state of the GPIO 32-60. Each bit indicates the state of GPIO. The upper three bits are reserved. Bits Name Default Description 28:0 INVALUE1 If bit <x> is set, state of GPIO <x + 32>is high. 9.2.5 GPIO_INTR0 Register This register holds the interrupt state of each GPIO 0 -31.

  • Page 128: Pin_Status Register

    FX3 Serial Peripheral Register Access Table 9-3. Complex GPIO Registers Offset Width Name Description 0xE0001000 + (GPIO_ID MOD PIN_STATUS Configuration, mode and status of I/O Pin. 8) * 0x10 0xE0001004 + (GPIO_ID MOD PIN_TIMER Timer/counter for pulse and measurement modes. 8) * 0x10 0xE0001008 + (GPIO_ID MOD...
  • Page 129 FX3 Serial Peripheral Register Access Bits Name Default Description Mode/command. Behavior is undefined when MODE>2 and TIMER_MODE=4,5,6. 0: STATIC 1: TOGGLE 2: SAMPLENOW 3: PULSENOW 4: PULSE 5: PWM 6: MEASURE_LOW 11:8 MODE 7: MEASURE_HIGH 8: MEASURE_LOW_ONCE 9: MEASURE_HIGH_ONCE 10: MEASURE_NEG 11: MEASURE_POS 12: MEASURE_ANY 13: MEASURE_NEG_ONCE...

  • Page 130: Pin_Timer Register

    FX3 Serial Peripheral Register Access 9.3.2 PIN_TIMER Register 32-bit revolving counter, using period (GPIO_PERIOD+1). Note that each GPIO pin has its own independent timer/counter. This register is valid only for complex GPIOs. Bits Name Default Description 32-bit timer-counter value. Use MODE=SAMPLE_NOW 31:0 TIMER to sample the timer into PIN_THRESHOLD.

  • Page 131: Fx3 P-Port Register Access

    10. FX3 P-Port Register Access FX3’s processor interface is a General Programmable parallel interface (GPIF) that can be pro- grammed to operate with: 1. 8 bit address 2. 8, 16 or 32 bit data bus widths 3. Burst sizes: 2 thru 2^14 4.

  • Page 132: Externally Visible Pp Registers

    FX3 P-Port Register Access 10.2 Externally Visible PP Registers The following table lists key registers of the P-port used in initialization and data transfer across the P-port. Table 10-1. PP Register Description Processor Port Register Map in GPIF space Offset Width Name Description...

  • Page 133: Pp_Init Register

    FX3 P-Port Register Access 10.2.2 PP_INIT Register P-Port reset and power control. This register is used for reset and power control and determines the endian orientation of the P-port. Bits Name Default Description Indicates system woke up through a power- on-reset or RESET# pin reset sequence.

  • Page 134: Pp_Config Register

    FX3 P-Port Register Access 10.2.3 PP_CONFIG Register P-Port Configuration Register. This register contains various P-Port configuration options. Many of these values need to be interpreted by firmware and converted into relevant GPIF setting changes. No direct hardware effects are implemented except where stated otherwise below. Writing to this register will lead to a firmware interrupt PIB_INTR.CONFIG_CHANGE.

  • Page 135: Pp_Intr_Mask Register

    FX3 P-Port Register Access 10.2.4 PP_INTR_MASK Register P-port Interrupt Mask register. This register has the same layout as PP_EVENT register and mask which event lead to assertion of INTR. Bits Name Default Description SOCK_AGG_AL 1: Forward EVENT onto INT line SOCK_AGG_AH 1: Forward EVENT onto INT line SOCK_AGG_BL...

  • Page 136: Pp_Error

    FX3 P-Port Register Access 10.2.7 PP_ERROR P-Port Error Indicator Register. This register indicates the error codes associated with PIB_INTR.PIB_ERR, MMC_ERR and GPIF_ERR. The different values for these error codes will be documented in the P-Port BROS document. This register is also visible to firmware as PIB_ERROR. Bits Name Default...

  • Page 137: Pp_Dma_Size

    FX3 P-Port Register Access 10.2.9 PP_DMA_SIZE P-Port DMA Transfer Size Register. This register indicates the (remaining) size of the transfer. This register is initialized to the number of bytes available in the buffer for egress transfers and the size of the buffer for ingress transfers.

  • Page 138: 12Pp_Rd_Mailbox

    FX3 P-Port Register Access Bits Name Default Description Usage of DMA_WMARK is explained in PAS. 0: P-Port has fewer than <watermark> words DMA_WMARK_EV left (can be 0) 1: P-Port is ready for transfer and at least <watermark> words remain Usage of DMA_READY is explained in PAS. DMA_READY_EV 0: P-port not ready for data transfer 1: P-port ready for data transfer...

  • Page 139: Transferring Data Into And Out Of Sockets

    FX3 P-Port Register Access 10.4 Transferring Data into and out of Sockets The following section describes how the Application Processor transfers blocks of data into and out of active sockets using the PP Register protocol. All GPIF PP-Mode based transfers use the same internal mechanisms but may differ in the usage of DRQ/INTR signaling.
  • Page 140 FX3 P-Port Register Access A/D depicts Address and Data bus independent of interface protocol. Full size transfer is illustrated in the figure below. Figure 10-1. Full-sized DMA Transfers 1. AP configures PP_SOCK_STAT[N] becomes active when data or space is available. 2.

  • Page 141: Short Transfer - Partial Buffer

    FX3 P-Port Register Access Figure 10-2. Short Transfer - DMA Transfer Sequence AP gets interrrupted by Application Benicia INTR#. AP reads Processor P-port PP_SOCK_STAT and GPMC port determins sockets ready SOCKET N has a for transfer. empty (full) buffer that causes Processor writes PP_SOCK_STAT[N] DMA_XFER with socket-...

  • Page 142: Short Transfer - Zero Length Buffers

    FX3 P-Port Register Access Note that simply reading or writing fewer than DMA_SIZE bytes does not terminate the transfer – the remaining bytes can be read at any time. Only when DMA_SIZE bytes have been transferred or when DMA_ENABLE is explicitly cleared (by writing to DMA_XFER) does the transfer end. The following diagrams illustrate both the normal partial and aborted transfer: Figure 10-3.

  • Page 143: Long Transfer - Integral Number Of Buffers

    FX3 P-Port Register Access The AP can observe the completion of a ZLB transfer by polling the DMA_XFER register. This should not take more than a couple of cycles. Figure 10-5. Zero Length Read (Egress) Transfer SOCK_STAT[N] DMA_ENABLE DMA_READY DMA_WMARK R/W# SOCK_ DMA _...

  • Page 144: Long Transfer - Aborted By Ap

    FX3 P-Port Register Access Figure 10-7. Long Transfer With Integral Number Of Buffers SOCK_STAT[N] DMA_ENABLE DMA_READY DMA_W MARK R/W# DMA _ B uffer 0 B uffer 0 B uffer 0 B uffer 0 B uffer N B uffer N B uffer N B uffer N DMA _ X FE R...

  • Page 145: Long Transfer - Partial Last Buffer On Ingress

    FX3 P-Port Register Access The AP may abort a transfer in the middle of a burst or at the end of a burst. Note that it is not pos- sible to implement a transfer of a non-integral number of bursts using the AP abort mechanism. This requires the adjustment of the DMA_SIZE register as illustrated in the next section.

  • Page 146: Odd Sized Transfers

    FX3 P-Port Register Access Figure 10-10. Egress Long Transfer - with Partial Last Buffer SOCK_STAT[N] DMA_ENABLE DMA_READY DMA_WMARK R/W# DMA_ Buffer 0 Buffer 0 Buffer 0 Buffer 0 Buffer N Buffer N DMA _ XFER Burst 0 Burst 1 Burst 2 Burst 3 Burst 0 Burst 1...
  • Page 147 FX3 P-Port Register Access Figure 10-12. Burst of 16 Read on ADMux Interface tCLKH tCLKL tCLK Valid A[0:7]/DQ[0:31] Address tS tH ADV# tAVWE High-Z Note: 1. 2-cycle latency is shown . 2. RDY active high shown. RDY can be programmed to either active low or active high. FX3 Programmers Manual, Doc.
  • Page 148 FX3 P-Port Register Access FX3 Programmers Manual, Doc. # 001-64707 Rev. *C...

  • Page 149: 11. Fx3 Boot Image Format

    11. FX3 Boot Image Format The FX3 bootloader is capable of booting various sources based on the PMODE pin setting. The bootloader requires the firmware image to be created with the following format: 11.1 Firmware Image Storage Format Binary Image Length Description Header...
  • Page 150 FX3 Boot Image Format Binary Image Length Description Header (16-bit) 1st section length, in long words (32-bit) dLength 0 When bImageType=0xB2, the dLength 0 will contain PID and VID. Boot Loader will ignore the rest of the any following data. 1st sections address of Program Code not the I2C address.

  • Page 151: 12. Fx3 Development Tools

    12. FX3 Development Tools A set of development tools is provided with the SDK, which includes the third party tool-chain and IDE. The firmware development environment will help the user to develop, build and debug firmware ® applications for FX3. The third party ARM software development tool provides an integrated development environment (IDE) with compiler, linker, assembler and debugger (via JTAG).
  • Page 152 FX3 Development Tools sample applications which are distributed with the FX3 SDK. It also explains how to create a new application project using FX3 SDK. 12.2.2.1 Importing Eclipse Projects Eclipse projects are provided with each FX3 firmware example. These have to be imported into eclipse before they can be used.
  • Page 153 FX3 Development Tools 2. Select General->Existing projects into Workspace. FX3 Programmers Manual, Doc. # 001-64707 Rev. *C...
  • Page 154 FX3 Development Tools 3. Select the root directory where the eclipse projects are available. This will be the directory where the FX3 SDK is installed. FX3 Programmers Manual, Doc. # 001-64707 Rev. *C...
  • Page 155 FX3 Development Tools 4. All the available FX3 projects are shown. Select all the projects displayed and click “Finish”. At the end of this step, all the projects for the FX3 firmware examples have been imported into the eclipse workbench. 12.2.2.2 Building Projects After the projects have been imported, they have to be built.
  • Page 156 FX3 Development Tools 2. The project view is opened up and projects will appear in the left pane. The projects are automat- ically built after an import. The build console displays the build messages. 12.2.2.3 Executing and Debugging 1. The GNU debugger (gdb) connects to the target (FX3 hardware) using the J-Link GDB server from Segger Systems.
  • Page 157 FX3 Development Tools port. Once the JTAG is connected and the GDB server is run, the ARM9 core will appear con- nected on the GDB server window as shown below. The “Init regs on start” will be checked by default. Please ensure to un-check this box. All initial- izations will be done by our debug configuration.
  • Page 158 FX3 Development Tools 2. The first step is to create a debug configuration for the project. Select Debug Configurations. FX3 Programmers Manual, Doc. # 001-64707 Rev. *C...
  • Page 159 FX3 Development Tools 3. Select Zylin Embedded debug (native) and launch a new configuration. A new configuration window opens up. 4. The debug settings must be modified. The first setting that needs to change is in the Debugger tab. The default setting uses the native gdb as the debugger. The default setting has to be modified to use “arm-none-eabi-gdb.exe”...
  • Page 160 FX3 Development Tools The verbose console mode is checked. 5. The commands have to be added next. The initialize commands are set prompt (arm-gdb) # This connects to a target via netsiliconLibRemote # listening for commands on this PC's tcp port 2331 target remote localhost:2331 monitor speed 1000 monitor endian little...
  • Page 161 FX3 Development Tools # correct value from list below. # Clock input is 19.2 MHz: Value = 0x00080015 # Clock input is 26.0 MHz: Value = 0x00080010 # Clock input is 38.4 MHz: Value = 0x00080115 # Clock input is 52.0 MHz: Value = 0x00080110 monitor memU32 0xE0052000 = 0x00080015 # Add a delay to let the clock stabilize.
  • Page 162 FX3 Development Tools 6. Once the debug is launched, the executable is loaded and the debug screen is displayed. The execution is halted at the instruction specified in the load command. FX3 Programmers Manual, Doc. # 001-64707 Rev. *C...
  • Page 163 FX3 Development Tools 7. If the execution is resumed, it will stop at a breakpoint, if one has been set. 12.2.2.4 Creating New Eclipse Projects New projects can be created in eclipse. The following steps illustrate the creation of a new project. FX3 Programmers Manual, Doc.
  • Page 164 FX3 Development Tools 1. Select File->New->C project 2. Select ARM Cross Target Application -> Empty project Select Arm Windows GCC (Sourcery G++ Lite) Select the folder where the project must be created. This must be the folder where the source files for this project are present.
  • Page 165 FX3 Development Tools Click next FX3 Programmers Manual, Doc. # 001-64707 Rev. *C...
  • Page 166 FX3 Development Tools 3. Click on Advanced Settings to get the settings window. Here we are updating the debug configu- ration. FX3 Programmers Manual, Doc. # 001-64707 Rev. *C...
  • Page 167 FX3 Development Tools 4. Click on C/C++ Build -> Settings. The first setting is the target processor. Select arm926ej-s as the processor. Click on Apply. FX3 Programmers Manual, Doc. # 001-64707 Rev. *C...
  • Page 168 FX3 Development Tools 5. The next settings are for debug. Select the default debug level (-g) and the dwarf-2 debug format. Click on Apply. FX3 Programmers Manual, Doc. # 001-64707 Rev. *C...
  • Page 169 FX3 Development Tools Select the default debug level none for release configuration. Click on Apply. FX3 Programmers Manual, Doc. # 001-64707 Rev. *C...
  • Page 170 FX3 Development Tools 6. The next settings are for Additional tools. Un check the “Create Flash Image” box. Click on Apply. FX3 Programmers Manual, Doc. # 001-64707 Rev. *C...
  • Page 171 FX3 Development Tools 7. The next settings are for the Assembler. Click on “ARM Sourcery Windows GCC Assembler”. Click on “Directories” and add “${FX3_INSTALL_PATH}\firmware\u3p_firmware\inc” as a direc- tory path. FX3 Programmers Manual, Doc. # 001-64707 Rev. *C...
  • Page 172 FX3 Development Tools 8. The next settings are for the Compiler. Click on “ARM Sourcery Windows GCC C Compiler”. Click on “Preprocessor” and add “__CYU3P_TX__=1”. Click on Apply. FX3 Programmers Manual, Doc. # 001-64707 Rev. *C...
  • Page 173 FX3 Development Tools 9. The next settings are also for the Compiler. Click on “ARM Sourcery Windows GCC C Compiler”. Click on “Directories” and add the relevant directories. Click on Apply. FX3 Programmers Manual, Doc. # 001-64707 Rev. *C...
  • Page 174 FX3 Development Tools 10.The next settings are also for the Compiler. Select optimization level “None (-O0)” for Debug mode. Click on Apply. FX3 Programmers Manual, Doc. # 001-64707 Rev. *C...
  • Page 175 FX3 Development Tools Select optimization level “Optimize size (Os)” for Release mode. Click on Apply. FX3 Programmers Manual, Doc. # 001-64707 Rev. *C...
  • Page 176 FX3 Development Tools 11.The next settings are for the Linker. Click on “ARM Sourcery Windows GCC C Linker”. In the “Command Line Pattern” box, move the “${INPUTS}” field to immediately after the “${COM- MAND}”. Click on Apply. FX3 Programmers Manual, Doc. # 001-64707 Rev. *C...
  • Page 177 FX3 Development Tools 12.The next settings are also for the Linker. Click on “ARM Sourcery Windows GCC C Linker”. Click on “General” and add the linker script file. Click on Apply. 13. The next settings are also for the Linker. Click on “ARM Sourcery Windows GCC C Linker”. Click on “Miscellaneous”...
  • Page 178 FX3 Development Tools Click on Apply. FX3 Programmers Manual, Doc. # 001-64707 Rev. *C...

  • Page 179: Attaching Debugger To A Running Process

    FX3 Development Tools 14.The project settings are over. Click on “Ok” and build the project. The project should build cor- rectly. 12.2.3 Attaching Debugger to a Running Process The debugger can be attached to an already running process. This is required when the executable has been downloaded to the FX3 by means other than JTAG (USB/I2C/SPI boot).
  • Page 180 FX3 Development Tools d. Start the GDB server FX3 Programmers Manual, Doc. # 001-64707 Rev. *C...
  • Page 181 FX3 Development Tools 2. Open the eclipse project which was used to build the currently running process. Create a new debug configuration for this project. Select ‘Zylin Embedded debug (Native)”. FX3 Programmers Manual, Doc. # 001-64707 Rev. *C...
  • Page 182 FX3 Development Tools 3. In the “Debugger” tab, change the GDB Debugger to arm-none-eabi-gdb.exe and leave the GDB command file blank. FX3 Programmers Manual, Doc. # 001-64707 Rev. *C...
  • Page 183 FX3 Development Tools 4. In the “Commands” tab, only a single Load command is specified “target remote localhost:2331”. Click on Debug. FX3 Programmers Manual, Doc. # 001-64707 Rev. *C...

  • Page 184: Using Makefiles

    FX3 Development Tools 5. The program will stop executing once the debugger attaches. The required breakpoints can be set and the program resumed. 12.2.4 Using Makefiles Makefiles are available for each of the examples that are distributed in the FX3 SDK. These make- files can be invoked in a Unix shell (on a unix/linux machine) or on windows which has a Cygwin environment.
  • Page 185 FX3 Development Tools FX3 Programmers Manual, Doc. # 001-64707 Rev. *C...
  • Page 186 FX3 Development Tools FX3 Programmers Manual, Doc. # 001-64707 Rev. *C...
  • Page 187 FX3 Development Tools FX3 Programmers Manual, Doc. # 001-64707 Rev. *C...
  • Page 188 FX3 Development Tools FX3 Programmers Manual, Doc. # 001-64707 Rev. *C...

  • Page 189: Fx3 Host Software

    13.1 FX3 Host Software A comprehensive host side (Microsoft Windows) stack in the FX3 SDK. This stack includes Cypress generic USB 3.0/2.0 driver (WDF) on Windows 7 (32/64 bit), Windows Vista (32/64 bit), ■ and Windows XP (32 bit only) Convenience APIs that expose generic ■...

  • Page 190: Cy Control Center

    13.1.4 Cy Control Center USB ControlCenter is a C Sharp application that is used to communicate with Cypress USB devices that are served by CyUSB3.sys device driver. Kindly refer to the CyControlCenter.pdf in the Cypress SuperSpeed USBSuite installation for more details.
  • Page 191 Getting Started Guide and the Application Note AN65974 - Designing with EX-USB FX3 Slave FIFO Interface for details on using these configuration headers. Please contact Cypress USB support team for any queries on GPIF-II configuration. FX3 Programmers Manual, Doc. # 001-64707 Rev. *C...
  • Page 192 GPIF™ II Designer FX3 Programmers Manual, Doc. # 001-64707 Rev. *C...

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