Table of Contents
Advertisement
6.5 Power ON/OFF Sequence
VDD power and lamp on/off sequence are as follows. Interface signals are also shown in the chart. Signals
from any system shall be Hi-Z state or low level when VDD is off.
Power Supply VDD
0V
LVDS Signal
Backlight On
Note1: insert a white pattern 360ms
Note2: insert a black pattern
Note3 :insert a white pattern after valid data and last until VDD falls to 10%.
Note4 :when AC on/off, timing rule of logo power on /off is the same as above.
Parameter
T
1
T
2
T
3
T
4
T
5
T
6
T
7
Panel Specification
T1
90%
10%
Note 1
T2
T3
90%
Note 2
T5
VALID
DATA
Note 3
T4
Value
Min.
Typ.
0
5 .
-
0
4
0
5
0
0
-
3
0
0
-
4
0
1
5
0
-
-
1
0
0
0
-
T6
10%
T7
Max.
1
0
5
0
-
-
0
-
-
-
Unit
[
m
] s
[
m
] s
[
m
] s
[
m
] s
[
m
] s
[
m
] s
[
m
] s
Advertisement
Table of Contents
