The Dw1000 Register Set; Register Map Overview; Table 15: Register Map Overview - decaWave DW1000 User Manual

DW1000 User Manual
7

The DW1000 register set

The DW1000 is controlled by an associated host microcontroller system using the SPI interface to access a
series of registers within the device. The DW1000 register set includes configuration registers, status
registers, control registers, data buffer registers, and diagnostic registers. Section
described the SPI interface and the low level transactions for reading and writing the parameters of the
DW1000. This section begins with
where each individual parameter is described in detail.
7.1

Register map overview

The register map overview is given in Table 15. This lists the registers in address order, by register file ID,
giving the register file length in octets, its type (RO = Read-Only, RW = Read & Write, SRW = Special Read
Write - see individual register descriptions for details about how the Read/Write access is special), and a
brief high level description of the register. Section 7.2 gives a detailed description of each register.
Note: When writing to any of the DW1000 registers care must be taken not to write beyond the published
length of the selected register and not to write to any of the reserved register locations. Doing so may cause
the device to malfunction.
Length
ID Type
(octets)
0x00 4 RO
0x01 8 RW
0x02 - -
0x03 4 RW
0x04 4 RW
0x05 - -
0x06 5 RO
0x07 - -
0x08 5 RW
0x09 1024 WO
0x0A 5 RW
0x0B - -
0x0C 2 RW
0x0D 4 SRW
0x0E 4 RW
0x0F 5 SRW
0x10 4 ROD
0x11 1024 ROD
0x12 8 ROD
0x13 4 ROD
0x14 5 ROD
© Decawave Ltd 2017
7.1- Register map overview

Table 15: Register map overview

Mnemonic
DEV_ID Device Identifier - includes device type and revision info
EUI Extended Unique Identifier
- Reserved
PANADR PAN Identifier and Short Address
SYS_CFG System Configuration bitmap
- Reserved
SYS_TIME System Time Counter (40-bit)
- Reserved
TX_FCTRL Transmit Frame Control
TX_BUFFER Transmit Data Buffer
DX_TIME Delayed Send or Receive Time (40-bit)
- Reserved
RX_FWTO Receive Frame Wait Timeout Period
SYS_CTRL System Control Register
SYS_MASK System Event Mask Register
SYS_STATUS System Event Status Register
RX_FINFO RX Frame Information
RX_BUFFER Receive Data
RX_FQUAL Rx Frame Quality information
RX_TTCKI Receiver Time Tracking Interval
RX_TTCKO Receiver Time Tracking Offset
and then
Version 2.12
2.2 - The SPI Interface
7.2- Detailed register
Description
(in double buffer set)
(in double buffer set)
(in double buffer set)
(in double buffer set)
(in double buffer set)
description,
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