Decawave Ltd - decaWave DW1000 User Manual

DW1000 User Manual
To configure DW1000 for OSTR mode, the OSTRM bit in the EC_CTRL register is set and the WAIT value is set
to the desired delay value. When a counter running on the 38.4 MHz external clock and initiated on the
rising edge of the SYNC signal equals the WAIT programmed value, the DW1000 timebase counter will be
reset. See Register file: 0x24 – External Synchronisation Control for register details.
At the time the SYNC signal is asserted, the clock PLL dividers generating the DW1000 125 MHz system clock
are reset, to ensure that a deterministic phase relationship exists between the system clock and the
asynchronous 38.4 MHz external clock. For this reason, the WAIT value programmed will dictate the phase
relationship and should be chosen to give the desired phase relationship, as given by WAIT modulo 4. A
WAIT value of 33 decimal is recommended, but if a different value is chosen it should be chosen so that
WAIT modulo 4 is equal to 1, i.e. 29, 37, and so on.
6.1.2 One Shot Transmit Synchronisation (OSTS) Mode
DW1000 allows the transmission of a frame at a deterministic time after the SYNC signal is asserted, using
the One Shot Transmit Synchronisation (OSTS) mode. OSTS mode provides for the transmission of a frame at
a well-defined time relative to the assertion of the SYNC DW1000 input. This time will vary slightly per part,
typically 12 ps, but may vary up to 3 ns across process for all parts.
This feature will be used where a local master locationing device is using the DW1000 as a slave to provide
additional location data. Calibration can be employed by the master device to tune for the constant offset
due to the SYNC trace and process variation and in that case, the delay variation across all parts will be less
than 100 ps.
Note that OSTS mode works identically to OSTR in every respect except for the final action performed, e.g. to
reset the timebase or to initiate a transmission.
To configure OSTSmode the OSTSM bit must be set in the EC_CTRL register and the WAIT value set to the
desired delay value, see Register file: 0x24 – External Synchronisation Control. A value of 33 is
recommended; see 6.1.1 – One Shot Timebase Reset (OSTR) Mode. When a counter running on the 38.4
MHz external clock and initiated on the rising edge of the SYNC signal equals the WAIT programmed value,
the DW1000 will initiate a transmission, by issuing a TX START signal from the external synchronisation
circuit in the clock PLL to the transmitter. The rising edge of the TX START signal is synchronised to the 125
MHz system clock domain before it is used to enable the transmission.
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