decaWave DW1000 User Manual page 173

DW1000 User Manual
Sub-Register 0x2C:0A – AON_CFG1
7.2.45.8
Length
ID Type
(octets)
2C:0A 2
Register file: 0x2C – Always-on system
parameters within the always-on (AON) block. The fields of this register are interpreted inside the AON
block, and this can only happen after the register is loaded into the AON block via the UPL_CFG command in
Sub-Register 0x2C:02 –
REG:2C:0A – AON_CFG1 – AON Configuration Register 1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
The fields of the AON_CFG1 register identified above are individually described below:
Field
SLEEP_CEN This bit enables the sleep counter. For correct operation of the sleep counter (down counter)
when loading a new value into the SLEEP_TIM field of
reg:2C:0A
recommended to set SLEEP_CEN to 0 before updating SLEEP_TIM. The recommended
bit:0
operating procedure is then as follows:
(a) Set SLEEP_CEN (in AON_CFG1) to 0.
(b) Set UPL_CFG (in AON_CTRL) to 1, to apply this to the AON block.
(c) Program the new value of SLEEP_TIM (in AON_CFG0).
(d) Set SLEEP_CEN to 1.
(e) Set UPL_CFG to 1, to apply the new sleep time and enable the counter in the AON.
SMXX This bit needs to be set to 0 for correct operation in the SLEEP state within the DW1000. By
reg:2C:0A
default this bit is set to 1. The host system should set this bit to zero as part of initialisation or
bit:1
controlling the entry of the DW1000 into the SLEEP state to ensure correct operation of the
SLEEP mode.
LPOSC_CAL This bit enables the calibration function that measures the period of the IC's internal low
powered oscillator. The operating frequency of this oscillator depends on process variations
reg:2C:0A
within the IC and also on the operating voltage and temperature. It should lie somewhere
bit:2
between approximately 7,000 and 13,000 Hz. Using this LPOSC_CAL bit then it is possible
measure the period of the oscillation in counts of the IC's internal XTAL_DIV2 clock, which runs
at a frequency of 19.2 MHz. Using this information it is then possible to more accurately
determine the value to set into the SLEEP_TIM field (of
a particular desired sleep period.
The recommended operating procedure for this is then using this is then is to:
(a) Ensure that the SPI operating frequency is set < 3MHz. (During procedure the system
uses the 19.2 MHz XTI clock which will not support higher SPI data rates).
© Decawave Ltd 2017
Mnemonic
RW AON_CFG1
control, sub-register 0x0A is a 16-bit configuration register for
AON_CTRL. The AON_CFG1 register contains the following fields:
Description of fields within Sub-Register 0x2C:0A – AON_CFG1
AON Configuration Register 1
- - - - -
0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1
Sub-Register 0x2C:06 – AON_CFG0
Sub-Register 0x2C:06 –
Version 2.12
Description
- - - - - - -
AON_CFG0) for
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it is